Anti-irradiation system based on dynamic memory refreshing

Abstract

The invention discloses an anti-radiation system based on dynamic memory refreshing, which comprises an FPGA (Field Programmable Gate Array), a Flash storage module and a CRC (Cyclic Redundancy Check) module, the FPGA is provided with an internal storage pool and a lookup table updating unit, and the lookup table updating unit periodically reads lookup table data which is stored in the Flash and dynamically updated and stores the lookup table data in the internal storage pool; and replacing expired data or data damaged by single event upset. According to the anti-radiation system based on dynamic memory refreshing, a dynamic memory refreshing mechanism is added on the basis of a plug-in refreshing chip and triple modular redundancy, and an FPGA can dynamically refresh an internal memory pool by reading lookup table data in a plug-in FLASH memory. According to the key technical scheme, a single event upset event in an internal memory pool of the FPGA is rapidly and efficiently processed by combining lookup table cyclic refreshing and CRC verification, the anti-irradiation capacity of a system is improved, and stable operation of the system in an extreme environment is ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory refresh, and particularly relates to an anti-radiation system based on dynamic memory refresh. Background Art

[0002] In applications in modern aerospace, nuclear energy, high-energy physics and other fields, FPGAs are widely used for high-performance computing and data processing. However, in extreme environments such as high-radiation areas, FPGAs are prone to single-event upsets (SEUs). There are mainly two traditional anti-radiation schemes:

[0003] 1. Triple modular redundancy (TMR):

[0004] Improve fault tolerance through triple redundant design to ensure data consistency and program stability. Although this method is effective, due to the high demand for hardware resources, the processing process is relatively complex, and the cost is large. Especially when implemented in resource-constrained FPGAs, performance bottlenecks may be encountered.

[0005] 2. Memory Refreshing:

[0006] Reduce the probability of memory data being flipped by regularly refreshing the memory content. Traditional refreshing methods are based on a timing mechanism, but they cannot efficiently solve the single-event upset problem in the memory pool because the occurrence time of single-event upsets is difficult to predict.

[0007] However, although the above two schemes are effective, there are still some limitations:

[0008] Although the triple modular redundancy scheme is effective, it will occupy a large amount of FPGA resources, resulting in performance loss.

[0009] The memory refreshing scheme usually has a refreshing delay and cannot effectively process single-event upset events in the memory pool in real time. Especially during high-frequency high-speed data transmission, it cannot quickly respond to memory flips.

[0010] Therefore, in view of the above problems, further improvements are made. Summary of the Invention

[0011] The main purpose of the present invention is to provide an anti-radiation system based on dynamic memory refresh. On the basis of an external memory refreshing chip and triple modular redundancy, a dynamic memory refresh mechanism is added. The FPGA can dynamically refresh the internal memory pool (RAM) by reading the look-up table data stored in the external FLASH. Its key technical solution is to quickly and efficiently process single-event upset events in the FPGA internal memory pool by combining look-up table cyclic refresh and CRC check, improve the anti-radiation ability of the system, and ensure the stable operation of the system in extreme environments.

[0012] To achieve the above object, the present invention provides an anti-radiation system based on dynamic memory refresh, including an FPGA, a Flash (external storage device) storage module, and a CRC check module. The FPGA is provided with an internal storage pool (RAM, used to store the results of real-time calculation and data processing) and a lookup table update unit, where:

[0013] The lookup table update unit periodically reads the lookup table data saved in the Flash and updated dynamically and stores it in the internal storage pool, replacing the expired or damaged data due to single-event upsets, so as to ensure that the data in the internal storage pool will not stay for a long time and reduce the impact of single-event upsets;

[0014] By periodically reading the lookup table data of the Flash, the internal storage pool reads new data in real time, automatically replaces the expired or possibly flipped data, and each read will verify the data through the CRC check module to ensure the integrity of the data (the CRC check module is responsible for detecting and verifying the correctness of the data in the internal storage pool to ensure that the integrity of the data can be correctly verified each time the data is refreshed);

[0015] When the CRC check module detects an error in the data of the internal storage pool, the system quickly restores the affected memory content through the lookup table and cache mechanism to ensure the integrity of the data and the stability of the system (the memory restoration is automatic, without additional manual intervention, and the restoration time is extremely short to ensure the real-time performance of the system).

[0016] As a further preferred technical solution of the above technical solution, each time the data is transmitted from the Flash to the internal storage pool, a CRC check is performed to ensure that the transmitted data has not undergone a single-event upset. If the CRC check fails, the system will read the data from the Flash again until the data is complete and passes the check.

[0017] As a further preferred technical solution of the above technical solution, when a single-event upset or other errors occur in the FPGA memory data, through an automated memory restoration mechanism, without manual intervention, the correct data is automatically obtained from the Flash and written into the internal storage pool to restore the correctness of the data (this process can be completed in an extremely short time to ensure the high real-time performance of the system).

[0018] As a further preferred technical solution of the above technical solution, the FPGA is used to refresh the chip control.

[0019] As a further preferred technical solution of the above technical solution, the FPGA communicates with the external control through control instructions.

[0020] The beneficial effects of the present invention are as follows:

[0021] By introducing dynamic memory refresh and CRC check technologies, the present invention significantly improves the stability, reliability, and self-healing ability of the FPGA system in a high-radiation environment. Compared with the existing technical solutions, the present invention has obvious advantages in the following aspects:

[0022] 1. High-efficiency single-event upset resistance

[0023] · Through the dynamic memory refresh mechanism, combined with the cyclic refresh of the lookup table and the data verification of the external FLASH, the present invention can quickly detect and repair memory errors caused by single-event upsets.

[0024] · Problems of the prior art: Triple modular redundancy (TMR) requires multiple times of hardware resources, and the method of refreshing the chip cannot quickly locate and repair single-event upset errors.

[0025] · Advantages of the present invention: The dynamic refresh mechanism can quickly restore correct data when the memory is flipped, avoiding the long-term accumulation of errors and improving the immediacy and efficiency of radiation resistance.

[0026] 2. High reliability of data transmission

[0027] · The present invention uses CRC check technology to verify the data read from the external FLASH, and only the data passing the check will be written into the FPGA memory pool (RAM). This method ensures that the written data is correct and complete, further improving the reliability of the system.

[0028] · Problems of the prior art: Traditional memory refresh schemes lack real-time guarantee for data integrity, easily leading to incorrect data entering the memory and affecting system operation.

[0029] · Advantages of the present invention: CRC check effectively avoids the problem of inconsistent memory data caused by single-event upsets or data transmission errors, ensuring that the data in the FPGA memory pool is always in the correct state.

[0030] 3. Quick recovery mechanism

[0031] · The present invention has an automated data repair function. When a data error is detected, the correct data in the memory can be quickly restored through dynamic refresh and the lookup table of the external FLASH.

[0032] · Problems of the prior art: Data recovery in traditional schemes usually requires manual intervention or a long repair delay.

[0033] · Advantages of the present invention: The automated recovery process can significantly shorten the repair time and can be completed without manual intervention, thus ensuring the high real-time performance and reliability of the system.

[0034] 4. The stability and real-time performance of the system operation are significantly improved

[0035] · Through the real-time refresh and automatic recovery mechanism, the present invention can quickly repair the memory data after being affected by single-event upsets, ensuring the stable operation of the system and not affecting the execution of critical tasks.

[0036] · Problems of the prior art: The traditional refresh chip method has a slow refresh speed, which may cause a short-term inconsistency of system data, thereby affecting systems with high real-time requirements.

[0037] · Advantages of the present invention: The dynamic refresh mechanism can refresh the memory data in real time and quickly recover when an error occurs, fully meeting the requirements of industrial control, aerospace equipment, high-energy physics experiments, etc. with high real-time requirements.

[0038] 5. Wide range of applications and high design flexibility

[0039] · The present invention is applicable to various application scenarios requiring anti-radiation protection, such as aerospace, military and other fields, and has flexible design, and can adjust the refresh strategy according to different memory sizes and refresh cycles.

[0040] · Problems of the prior art: The adaptability of the traditional solution in specific scenarios is limited and it is difficult to adjust according to actual needs.

[0041] · Advantages of the present invention: The flexible design of the dynamic refresh mechanism enables it to adapt to a variety of application scenarios, especially in scenarios with high radiation and high reliability requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a schematic structural diagram of the present invention.

[0043] Figure 2 is a schematic diagram of the verification process of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0044] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments in the following description are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other implementation schemes, variation schemes, improvement schemes, equivalent schemes, and other technical schemes without departing from the spirit and scope of the present invention.

[0045] In the preferred embodiment of the present invention, those skilled in the art should note that the external control and the like involved in the present invention can be regarded as the prior art.

[0046] Preferred embodiment.

[0047] As Figure 1-2 shown, the present invention discloses an anti-radiation system based on dynamic memory refresh, including an FPGA, a Flash (external storage device) storage module, and a CRC check module. The FPGA is provided with an internal storage pool (RAM, used to store the results of real-time calculation and data processing) and a look-up table update unit, wherein:

[0048] The look-up table update unit regularly reads the look-up table data saved in the Flash for dynamic update and stores it in the internal storage pool, replacing the expired or damaged data due to single-event upsets, so as to ensure that the data in the internal storage pool will not stay for a long time and reduce the impact of single-event upsets;

[0049] By regularly reading the look-up table data of the Flash, the internal storage pool reads new data in real time, automatically replaces the expired or possibly flipped data, and each read will verify the data through the CRC check module to ensure the integrity of the data (the CRC check module is responsible for detecting and verifying the correctness of the data in the internal storage pool to ensure that the integrity of the data can be correctly verified each time the data is refreshed);

[0050] When the CRC check module detects an error in the data of the internal storage pool, the system quickly restores the affected memory content through the look-up table and cache mechanism to ensure the integrity of the data and the stability of the system (the memory restoration is automatic, without additional manual intervention, and the restoration time is extremely short to ensure the real-time performance of the system).

[0051] Specifically, each time data is transferred from Flash to the internal storage pool, CRC check is performed to ensure that the transferred data has not undergone single-event upset. If the CRC check fails, the system will reread the data from Flash until the data is complete and passes the check. (In the data stored in Flash, there is a CRC check code from the identifier to before the checksum at the end of each packet of data. After the FPGA reads the internal data of Flash, it will compare the check bits of each packet of data. The specific check method is: perform CRC-16 calculation from the "frame header" (including the "frame header") to the "checksum" (excluding the "checksum"), and take the bitwise inversion of the calculation result as the checksum value).

[0052] More specifically, when single-event upset or other errors occur in the FPGA memory data, through the automated memory recovery mechanism, without manual intervention, the correct data is automatically obtained from Flash and written into the internal storage pool to restore the correctness of the data. (This process can be completed in an extremely short time to ensure the high real-time performance of the system). (This process is that the FPGA regularly reads the data in Flash and writes it into the memory pool in the FPGA to ensure that the data can also be restored after single-event inversion).

[0053] Furthermore, the FPGA is used to refresh the chip control.

[0054] Even further, the FPGA communicates with the external control through control instructions.

[0055] Regarding the present invention:

[0056] 1. Dynamic memory refresh mechanism

[0057] The core innovation of the present invention is the lookup table loop refresh mechanism, which continuously refreshes the data in the memory pool and uses CRC check to detect and recover the impact of single-event upset events on the memory data.

[0058] · Lookup table loop refresh: The FPGA reads the lookup table data stored in the external FLASH memory and stores it in the memory pool (RAM) of the FPGA. The data in the lookup table is regularly rotated for reading and updating to ensure that the data in the memory pool does not stay for a long time and reduce the impact of single-event upset.

[0059] · Dynamic refresh mechanism: By regularly reading the data of the external memory (such as the external FLASH), the memory pool of the FPGA can obtain new data in real time to replace the expired or possibly flipped data. This process is automatic, and each read will verify the data through CRC check to ensure the integrity of the data.

[0060] 2. CRC Check Mechanism

[0061] To ensure the accuracy and reliability of the data in the memory pool, the present invention uses CRC check technology to detect single event upsets in the memory pool. CRC (Cyclic Redundancy Check) can quickly detect whether there are upsets or errors in the memory, especially in the case where the memory data is frequently updated. Through CRC check, it can ensure that the incorrect data in the memory can be repaired in time after an upset event occurs.

[0062] 3. Memory Recovery Mechanism

[0063] When the CRC check detects an error in the memory data, the system can quickly recover the affected memory content through a lookup table and a caching mechanism, ensuring the integrity of the data and the stability of the system. The flow chart is as Figure 2 shown. Memory recovery is automatic, without the need for additional manual intervention, and the recovery time is extremely short, ensuring the real-time performance of the system.

[0064] 4. System Architecture

[0065] The system architecture of this radiation-hardened technology is as follows:

[0066] · FPGA Memory Pool (RAM): The internal storage of the FPGA, used to store the results of real-time calculations and data processing.

[0067] · External FLASH Storage: An external storage device that stores the lookup table data updated dynamically.

[0068] · CRC Check Module: Responsible for detecting and verifying the correctness of the memory pool data, ensuring that the integrity of the data can be correctly verified each time the data is refreshed.

[0069] · Lookup Table Update Unit: By regularly reading the FLASH data, the data in the lookup table is passed into the FPGA memory pool to replace the expired or damaged data due to single event upsets.

[0070] 5. Resource Optimization in System Design

[0071] The present invention effectively avoids the waste of resources in the traditional triple modular redundancy (TMR) scheme through lookup table refresh and CRC check, and at the same time avoids the delay of the traditional memory refresh scheme. By reducing the occupation of hardware resources, a more efficient radiation-hardened protection scheme is provided.

[0072] It is worth mentioning that the technical features such as external control involved in this invention patent application should be regarded as the prior art. For the specific structures, working principles, possible control methods, and spatial arrangement methods of these technical features, conventional selections in the art can be adopted, and they should not be regarded as the invention points of this invention patent. This invention patent will not be further specifically elaborated.

[0073] For those skilled in the art, it is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A radiation-resistant system based on dynamic memory refresh, characterized in that: It includes an FPGA, a Flash storage module and a CRC check module, wherein the FPGA is provided with an internal storage pool and a lookup table update unit, wherein: The lookup table update unit periodically reads the dynamically updated lookup table data stored in the Flash and stores it in the internal storage pool to replace the data that has expired or been damaged by the single-particle upset, so as to ensure that the data in the internal storage pool will not stay for a long time and reduce the impact of the single-particle upset; By periodically reading the Flash lookup table data, the internal storage pool reads new data in real time, automatically replacing data that has expired or may be affected by rollover, and each read will verify the data through the CRC check module to ensure data integrity; When the CRC check module detects an error in the data of the internal storage pool, the system quickly restores the affected memory content through a lookup table and cache mechanism to ensure data integrity and system stability.

2. The radiation-resistant system based on dynamic memory refresh according to claim 1, characterized in that: Each time data is transferred from Flash to the internal storage pool, a CRC check is performed to ensure that no single-event upset occurs in the transferred data. If the CRC check fails, the system reads the data from Flash again until the data is complete and passes the check.

3. The radiation-resistant system based on dynamic memory refresh according to claim 2, characterized in that: When a single-particle upset or other error occurs in the FPGA memory data, the automatic memory recovery mechanism automatically obtains the correct data from the Flash without human intervention and writes it to the internal storage pool to restore the correctness of the data.

4. The radiation-resistant system based on dynamic memory refresh according to claim 1, characterized in that: FPGA is used to refresh chip control.

5. The radiation-resistant system based on dynamic memory refresh according to claim 1, characterized in that: FPGA communicates with external control through control instructions.

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