Bootstrap boost circuit for realizing surge voltage suppression

Abstract

The invention discloses a bootstrap boost circuit for realizing surge voltage suppression, and belongs to the technical field of surge voltage suppression. Comprising a three-end voltage stabilizing circuit, the input end of the three-end voltage stabilizing circuit is connected with a pre-stage input circuit, and the output end of the three-end voltage stabilizing circuit is connected with an operational amplifier oscillation circuit and a surge voltage suppression circuit; the operational amplifier oscillation circuit is connected with the bootstrap boost circuit; the bootstrap boost circuit is connected with the surge voltage suppression circuit and the post-stage output circuit; the three-terminal voltage stabilizing circuit is used for providing stable voltage input for the operational amplifier oscillating circuit; the bootstrap boost circuit is used for enabling a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) AD1 in the surge voltage suppression circuit to work in a saturated conduction state; and the surge voltage suppression circuit is used for suppressing the instantaneous input voltage when the instantaneous input voltage comes and enabling the grid voltage of the power MOSFET AD1 to be smooth and controllable through instantaneous energy absorption and coupling so as to complete surge voltage suppression. The input surge voltage can be effectively suppressed, and a rear-end power supply circuit is prevented from being damaged.

Description

Technical Field

[0001] The present invention relates to the technical field of surge voltage suppression, and particularly to a bootstrap boost circuit for realizing surge voltage suppression. Background Art

[0002] During the power-on test of airborne electronic products, it is divided into steps such as ground power-on test (i.e., pre-takeoff function and performance inspection), aircraft power transfer, and pre-takeoff function and performance confirmation. During the aircraft power transfer process, when switching from ground power supply to aircraft power supply, there will be an instantaneous voltage surge. In GJB181-1986 (Requirements for Aircraft Power Supply Characteristics and Electrical Equipment), the specified maximum voltage surge is 80V / 50ms; in GJB181A-2003 (An earlier version of the aircraft power supply characteristics standard) and GJB181B-2003 (An updated version of the aircraft power supply characteristics standard), the specified maximum voltage surge is 50V / 50ms. At the same time, according to the operating characteristics of generators on different aircraft platforms, requirements are usually specified that the instantaneous surge voltage of 50V to 80V does not cause damage or allows normal operation. Similarly, in the vehicle-mounted platform, at the moment of starting the engine, an instantaneous surge voltage of up to 100V will be generated.

[0003] In order to prevent the 80V or 100V instantaneous surge voltage from causing catastrophic damage to the backend power supply, an overvoltage protection method is usually adopted. When the voltage exceeds a certain threshold, the input voltage is turned off, and when the instantaneous value of the surge voltage disappears, power is applied again. The current 28V input power module can usually only withstand an instantaneous surge voltage within 50V. When an 80V or 100V instantaneous surge voltage occurs in the vehicle-mounted or airborne platform, currently, an overvoltage protection method is usually adopted. When the voltage exceeds a certain threshold, the input voltage is turned off, and when the instantaneous value of the surge voltage disappears, power is applied again, thereby avoiding catastrophic damage to the backend power module caused by the surge voltage. As a result, it will cause the backend electronic products to lose power instantaneously and then power on again, leading to faults such as data loss and even equipment downtime. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a bootstrap boost circuit for realizing surge voltage suppression.

[0005] The object of the present invention is achieved by the following technical solutions: A bootstrap boost circuit for realizing surge voltage suppression, including a three-terminal voltage regulator circuit. The input end of the three-terminal voltage regulator circuit is connected to the front-stage input circuit, and the output end of the three-terminal voltage regulator circuit is connected to an operational amplifier oscillation circuit and a surge voltage suppression circuit; the operational amplifier oscillation circuit is connected to the bootstrap boost circuit; the bootstrap boost circuit is connected to the surge voltage suppression circuit and the rear-stage output circuit; the three-terminal voltage regulator circuit is used to provide a stable voltage input for the operational amplifier oscillation circuit; the bootstrap boost circuit is used to make the power MOSFET AD1 in the surge voltage suppression circuit work in a saturated conduction state; the surge voltage suppression circuit is used to suppress the instantaneous input voltage when it comes, and through instantaneous energy absorption and coupling, make the gate voltage of the power MOSFET AD1 smooth and controllable, completing the surge voltage suppression.

[0006] Preferably, the three-terminal voltage regulator circuit includes a capacitor BC1, a reference voltage source AN2, a resistor BR5, a resistor AR3, a resistor AR2, and a power transistor AN1; the first end of the capacitor BC1 is connected to the front-stage input circuit, the drain of the power MOSFET AD1, the collector of the power transistor AN1, and the first end of the resistor BR5. The second end of the capacitor BC1 is connected to the anode of the reference voltage source AN2, the first end of the resistor AR3, and the ground GND; the cathode of the reference voltage source AN2 is connected to the second end of the resistor BR5 and the base of the power transistor AN1, and the reference electrode of the reference voltage source AN2 is connected to the second end of the resistor AR3 and the first end of the resistor AR2; the second end of the resistor AR2 is connected to the emitter of the power transistor AN1 and the operational amplifier oscillation circuit.

[0007] Preferably, the operational amplifier oscillation circuit includes a comparator BN1, a resistor AR1, a resistor BR1, a resistor BR2, a resistor BR3, a resistor BR4, a resistor BR6, and a capacitor BC2; the first end of the resistor BR1 is connected to the three-terminal voltage regulator circuit, and the second end of the resistor BR1 is connected to the first end of the resistor AR1, the third terminal of the comparator BN1, and the first end of the resistor BR2; the second end of the resistor BR2 is connected to the fourth terminal of the comparator BN1 and the ground GND; the second end of the resistor AR1 is connected to the first end of the resistor BR3, the first terminal of the comparator BN1, the first end of the resistor BR4, and the first end of the resistor BR6; the second end of the resistor BR3 is connected to the first end of the capacitor BC2 and the second terminal of the comparator BN1; the second end of the capacitor BC2 is connected to the ground GND; the second end of the resistor BR4 is connected to the bootstrap boost circuit; the second end of the resistor BR6 is connected to the eighth terminal of the comparator BN1 and the three-terminal voltage regulator circuit.

[0008] Preferably, the bootstrap boost circuit includes a DC-blocking capacitor BC3, a diode BD1, a diode BD2, and a diode BD3; a first end of the DC-blocking capacitor BC3 is connected to the operational amplifier oscillation circuit, and a second end of the DC-blocking capacitor BC3 is connected to a positive electrode of the diode BD1 and a negative electrode of the diode BD2; a negative electrode of the diode BD1 is connected to a gate of the power MOSFET AD1 and a negative electrode of the diode BD3; a positive electrode of the diode BD3 is connected to a positive electrode of the diode BD2 and the subsequent-stage output circuit.

[0009] Preferably, the surge voltage suppression circuit includes a diode AD2, a power MOSFET AD1, a capacitor AC1, and a capacitor AC2; a drain of the power MOSFET AD1 is connected to the three-terminal voltage regulator circuit, a gate of the power MOSFET AD1 is connected to a negative electrode of the diode BD1, and a source of the power MOSFET AD1 is connected to a first end of the capacitor AC1, a positive electrode of the diode BD3, and a positive electrode of the diode BD2; a second end of the capacitor AC1 is connected to a first end of the capacitor AC2, a negative electrode of the diode AD2, and a negative electrode of the diode BD3; a second end of the capacitor AC2 and a positive electrode of the diode AD2 are connected to the ground GND.

[0010] The beneficial effects of the present invention are as follows: 1) It can effectively suppress the input surge voltage, prevent damage to the backend power supply circuit, ensure the normal operation of the backend power supply circuit, avoid the occurrence of faults such as data loss or equipment downtime, greatly improve the working reliability of the equipment. At the same time, the circuit is simple, can be used in multiple parallel connections, has a wide range of application scenarios, and has good economy. Description of the Drawings

[0011] Figure 1 Schematic diagram of the bootstrap boost circuit for surge voltage suppression. Detailed Embodiments

[0012] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present invention.

[0013] Refer to Figure 1, the present invention provides a technical solution: a bootstrap boost circuit for realizing surge voltage suppression, including a three-terminal voltage regulator circuit. The input end of the three-terminal voltage regulator circuit is connected to the front-stage input circuit, and the output end of the three-terminal voltage regulator circuit is connected to an operational amplifier oscillation circuit and a surge voltage suppression circuit; the operational amplifier oscillation circuit is connected to the bootstrap boost circuit; the bootstrap boost circuit is connected to the surge voltage suppression circuit and the rear-stage output circuit; the three-terminal voltage regulator circuit is used to provide a stable voltage input for the operational amplifier oscillation circuit; the bootstrap boost circuit is used to make the power MOSFET AD1 in the surge voltage suppression circuit work in the saturation conduction state; the surge voltage suppression circuit is used to suppress the instantaneous input voltage when it comes, and through instantaneous energy absorption and coupling, make the gate voltage of the power MOSFET AD1 smoothly controllable, and complete the surge voltage suppression.

[0014] In this embodiment, by adjusting the G-pole voltage of the power MOSFET and its transient value of the G-pole voltage change, the output voltage of the power MOSFET is suppressed to between 36V and 45V, ensuring that the power supply module can still work normally and supply power during the surge voltage device, so that the backend device can work normally. The three-terminal voltage regulator circuit is used to provide a stable voltage input for the operational amplifier oscillation circuit. The bootstrap boost circuit enables the power MOSFET on the input positive line to work in the saturation conduction state. When the instantaneous input voltage comes, the surge voltage suppression circuit suppresses the voltage, and at the same time, through instantaneous energy absorption and coupling, ensures that the gate voltage of the power MOSFET is smoothly controllable, and finally achieves the purpose of surge voltage suppression.

[0015] In some embodiments, the three-terminal voltage regulator circuit includes a capacitor BC1, a reference voltage source AN2, a resistor BR5, a resistor AR3, a resistor AR2, and a power transistor AN1; the first end of the capacitor BC1 is connected to the front-stage input circuit, the drain of the power MOSFET AD1, the collector of the power transistor AN1, and the first end of the resistor BR5, and the second end of the capacitor BC1 is connected to the anode of the reference voltage source AN2, the first end of the resistor AR3, and the ground GND; the cathode of the reference voltage source AN2 is connected to the second end of the resistor BR5 and the base of the power transistor AN1, and the reference pole of the reference voltage source AN2 is connected to the second end of the resistor AR3 and the first end of the resistor AR2; the second end of the resistor AR2 is connected to the emitter of the power transistor AN1 and the operational amplifier oscillation circuit.

[0016] In this embodiment, capacitor BC1 is connected between the input (C pole) terminal of the power transistor and the input negative, resistor BR5 is connected between the input (C pole) terminal of the power transistor and the control (B pole) terminal, the K terminal of the voltage reference is connected to the control (B pole) terminal of the power transistor, the A terminal of the voltage reference is connected to the input negative, resistor AR2 is connected between the output (E pole) terminal of the power transistor and the R terminal of the voltage reference, and resistor AR3 is connected between the R terminal of the voltage reference and the input negative. The three-terminal voltage regulator circuit ensures a 12V output under the condition of input voltage surge change.

[0017] In some embodiments, the operational amplifier oscillation circuit includes comparator BN1, resistor AR1, resistor BR1, resistor BR2, resistor BR3, resistor BR4, resistor BR6, and capacitor BC2; the first end of resistor BR1 is connected to the three-terminal voltage regulator circuit, the second end of resistor BR1 is connected to the first end of resistor AR1, the third end of comparator BN1, and the first end of resistor BR2; the second end of resistor BR2 is connected to the fourth end of comparator BN1 and ground GND; the second end of resistor AR1 is connected to the first end of resistor BR3, the first end of comparator BN1, the first end of resistor BR4, and the first end of resistor BR6; the second end of resistor BR3 is connected to the first end of capacitor BC2 and the second end of comparator BN1; the second end of capacitor BC2 is connected to ground GND; the second end of resistor BR4 is connected to the bootstrap boost circuit; the second end of resistor BR6 is connected to the eighth end of comparator BN1 and the three-terminal voltage regulator circuit.

[0018] In this embodiment, resistor AR1 is connected between the non-inverting input terminal and the output terminal of the comparator, resistor BR1 is connected to the input terminal of the comparator and the non-inverting input terminal of the comparator, resistor BR2 is connected between the non-inverting input terminal of the comparator and the input negative, resistor BR3 is connected between the inverting input terminal and the output terminal of the comparator, resistor BR4 is connected between the output terminal of the comparator and the input terminal of the comparator, resistor BR6 is connected in series at the output terminal of the comparator, capacitor BC2 is connected between the inverting input terminal of the comparator and the input negative, and the output terminal of the comparator. Thus, a square wave with a standard 12V voltage difference is generated, and the frequency is about 3KHz.

[0019] In some embodiments, the bootstrap boost circuit includes DC-blocking capacitor BC3, diode BD1, diode BD2, and diode BD3; the first end of DC-blocking capacitor BC3 is connected to the operational amplifier oscillation circuit, the second end of DC-blocking capacitor BC3 is connected to the positive electrode of diode BD1 and the negative electrode of diode BD2; the negative electrode of diode BD1 is connected to the gate of power MOSFET AD1 and the negative electrode of diode BD3; the positive electrode of diode BD3 is connected to the positive electrode of diode BD2 and the subsequent output circuit.

[0020] In this embodiment, the DC-blocking capacitor is connected between the resistor BR4 of the operational amplifier oscillation circuit and the transistor BD1, the transistor BD2 is connected between the DC-blocking capacitor BC3 and the voltage output, and the transistor BD3 is connected between the voltage output and the transistor BD1. After superimposing the DC voltage and the square-wave 12V voltage, this circuit is rectified into a high DC voltage for driving the power MOSFET in the surge voltage suppression circuit.

[0021] In some embodiments, the surge voltage suppression circuit includes a diode AD2, a power MOSFET AD1, a capacitor AC1, and a capacitor AC2; the drain of the power MOSFET AD1 is connected to the three-terminal voltage regulator circuit, the gate of the power MOSFET AD1 is connected to the negative electrode of the diode BD1, and the source of the power MOSFET AD1 is connected to the first terminal of the capacitor AC1, the positive electrode of the diode BD3, and the positive electrode of the diode BD2; the second terminal of the capacitor AC1 is connected to the first terminal of the capacitor AC2, the negative electrode of the diode AD2, and the negative electrode of the diode BD3; the second terminal of the capacitor AC2 and the positive electrode of the diode AD2 are connected to the ground GND.

[0022] In this embodiment, the input end (D pole) of the power MOSFET is connected to the input positive, the output end (S pole) of the power MOSFET is connected to the output positive, the transistor AD1 is connected between the control end (G pole) of the power MOSFET and the input negative, the capacitor AC1 is connected between the output end (S pole) of the power MOSFET and the control end (G pole) of the power MOSFET, and the capacitor AC2 is connected between the output end (S pole) of the power MOSFET and the input negative.

[0023] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications, and environments, and can be changed within the scope of the concept described herein through the above teachings or the technology or knowledge in the relevant field. And the changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention should all be within the protection scope of the appended claims of the present invention.

Claims

1. A bootstrap boost circuit for achieving surge voltage suppression, characterized in that: It comprises a three-terminal voltage stabilizing circuit, wherein the input end of the three-terminal voltage stabilizing circuit is connected to a front-stage input circuit, and the output end of the three-terminal voltage stabilizing circuit is connected to an operational amplifier oscillating circuit and a surge voltage suppression circuit; the operational amplifier oscillating circuit is connected to a bootstrap boosting circuit; the bootstrap boosting circuit is connected to a surge voltage suppression circuit and a rear-stage output circuit; the three-terminal voltage stabilizing circuit is used to provide a stable voltage input for the operational amplifier oscillating circuit; the bootstrap boosting circuit is used to make the power MOSFET tube AD1 in the surge voltage suppression circuit work in a saturated conduction state; the surge voltage suppression circuit is used to suppress the instantaneous input voltage when it comes, and make the gate voltage of the power MOSFET tube AD1 smooth and controllable through instantaneous energy absorption and coupling, thereby completing surge voltage suppression.

2. The bootstrap boost circuit for realizing surge voltage suppression according to claim 1, characterized in that: The three-terminal voltage stabilizing circuit includes a capacitor BC1, a reference voltage source AN2, a resistor BR5, a resistor AR3, a resistor AR2 and a power transistor AN1; the first end of the capacitor BC1 is connected to the front-stage input circuit, the drain of the power MOSFET tube AD1, the collector of the power transistor AN1 and the first end of the resistor BR5, and the second end of the capacitor BC1 is connected to the anode of the reference voltage source AN2, the first end of the resistor AR3 and the ground GND; the cathode of the reference voltage source AN2 is connected to the second end of the resistor BR5 and the base of the power transistor AN1, and the reference electrode of the reference voltage source AN2 is connected to the second end of the resistor AR3 and the first end of the resistor AR2; the second end of the resistor AR2 is connected to the emitter of the power transistor AN1 and the operational amplifier oscillation circuit.

3. The bootstrap boost circuit for realizing surge voltage suppression according to claim 1, characterized in that: The operational amplifier oscillator circuit includes a comparator BN1, a resistor AR1, a resistor BR1, a resistor BR2, a resistor BR3, a resistor BR4, a resistor BR6, and a capacitor BC2; the first end of the resistor BR1 is connected to a three-terminal voltage stabilizing circuit, the second end of the resistor BR1 is connected to a first end of the resistor AR1, a third end of the comparator BN1, and a first end of the resistor BR2; the second end of the resistor BR2 is connected to a fourth end of the comparator BN1 and a ground GND; the second end of the resistor AR1 is connected to a first end of the resistor BR3, a first end of the comparator BN1, a first end of the resistor BR4, and a first end of the resistor BR6; the second end of the resistor BR3 is connected to a first end of the capacitor BC2 and a second end of the comparator BN1; the second end of the capacitor BC2 is connected to the ground GND; the second end of the resistor BR4 is connected to a bootstrap voltage boosting circuit; the second end of the resistor BR6 is connected to an eighth end of the comparator BN1 and a three-terminal voltage stabilizing circuit.

4. The bootstrap boost circuit for realizing surge voltage suppression according to claim 1, characterized in that: The bootstrap boost circuit includes a DC blocking capacitor BC3, a diode BD1, a diode BD2 and a diode BD3; the first end of the DC blocking capacitor BC3 is connected to the operational amplifier oscillation circuit, and the second end of the DC blocking capacitor BC3 is connected to the positive electrode of the diode BD1 and the negative electrode of the diode BD2; the negative electrode of the diode BD1 is connected to the gate of the power MOSFET tube AD1 and the negative electrode of the diode BD3; the positive electrode of the diode BD3 is connected to the positive electrode of the diode BD2 and the post-stage output circuit.

5. The bootstrap boost circuit for realizing surge voltage suppression according to claim 4, characterized in that: The surge voltage suppression circuit includes a diode AD2, a power MOSFET tube AD1, a capacitor AC1 and a capacitor AC2; the drain of the power MOSFET tube AD1 is connected to a three-terminal voltage stabilizing circuit, the gate of the power MOSFET tube AD1 is connected to the cathode of the diode BD1, the source of the power MOSFET tube AD1 is connected to the first end of the capacitor AC1, the anode of the diode BD3 and the anode of the diode BD2; the second end of the capacitor AC1 is connected to the first end of the capacitor AC2, the cathode of the diode AD2 and the cathode of the diode BD3; the second end of the capacitor AC2 and the anode of the diode AD2 are connected to the ground GND.

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