Semiconductor device, preparation method thereof and electronic product

Abstract

The invention provides a semiconductor device and a preparation method thereof, and an electronic product. The semiconductor device comprises a two-dimensional material layer; the tunneling layer is arranged on one side of the two-dimensional material layer along the thickness direction; the electrode structure is arranged on the side, away from the two-dimensional material layer, of the tunneling layer, the electrode structure comprises a first electrode and a second electrode which are arranged in a spaced mode in the first direction, and the first direction is parallel to the plane where the two-dimensional material layer is located; wherein the tunneling layer is made of gallium oxide. According to the semiconductor device provided by the invention, the gallium oxide insulating material is adopted between the electrode structure and the two-dimensional material layer to serve as the material of the tunneling layer, so that the contact quality between the two-dimensional material layer and the electrode structure can be optimized, the contact resistance and the Schottky barrier are reduced by using the quantum tunneling effect, the device performance is optimized, and the reliability of the device is improved. A good packaging effect can be achieved for the two-dimensional material layer, and the Fermi level pinning phenomenon and erosion of environmental pollutants such as water and oxygen can be effectively resisted.

Description

Technical Field

[0001] The present application relates to the technical field of electronic devices, and in particular to a semiconductor device and a method for preparing the same, as well as an electronic product. Background Art

[0002] Two-dimensional (2D) materials have occupied an important position in the field of advanced electronic and optoelectronic technologies due to their high carrier mobility, tunable band gap, and easy van der Waals (vdW) integration. However, to fully tap the application potential of 2D materials in practical devices, major obstacles related to electrode contacts and environmental stability need to be addressed. In the design process of 2D semiconductor devices, it is crucial to fabricate high-quality electrode contacts. Traditional metal electrode preparation processes, such as evaporation or sputtering, involve high-energy particle radiation, which easily causes Fermi level pinning effect on the surface of 2D semiconductors, resulting in the formation of large Schottky barriers (SBs) at the interface between metal electrodes and 2D materials, increasing contact resistance and limiting charge injection and transfer efficiency.

[0003] In order to optimize the electrode contact quality of 2D materials, traditional methods have adopted a variety of strategies, including using low-melting-point metals, semi-metals and graphene to adjust the Fermi level, and using mechanical transfer technology to achieve van der Waals contact. However, the effect of improving the electrode contact quality is not good, and the contact resistance and Schottky barrier are still large, resulting in a small improvement in device performance. Summary of the invention

[0004] Based on this, the present application provides a semiconductor device with small contact resistance and Schottky barrier, a preparation method thereof, and an electronic product.

[0005] The present application provides a semiconductor device, comprising:

[0006] Two-dimensional material layers;

[0007] A tunneling layer, disposed on one side of the two-dimensional material layer along the thickness direction thereof;

[0008] An electrode structure is arranged on a side of the tunneling layer away from the two-dimensional material layer, and the electrode structure includes a first electrode and a second electrode arranged at intervals along a first direction, wherein the first direction is parallel to the plane where the two-dimensional material layer is located;

[0009] Wherein, the material of the tunneling layer includes gallium oxide.

[0010] In one embodiment, the thickness of the tunneling layer is 1 nm to 5 nm.

[0011] In one embodiment, the two-dimensional material layer includes one or more layers selected from a transition metal chalcogenide layer, a phosphorene layer, a graphene layer, a silicene layer, a two-dimensional perovskite material layer, a transition metal two-dimensional carbide layer, and a transition metal two-dimensional nitride layer.

[0012] In one embodiment, the thickness of the two-dimensional material layer is 0.1 nm to 50 nm.

[0013] In one embodiment, the semiconductor device is a field-effect transistor, the first electrode and the second electrode are a source electrode and a drain electrode respectively, the semiconductor device further includes a dielectric layer, the electrode structure further includes a gate, the gate is disposed on a side of the two-dimensional material layer away from the tunneling layer, and the dielectric layer is disposed between the gate and the two-dimensional material layer.

[0014] In one embodiment, the two-dimensional material layer includes a transition metal chalcogenide layer.

[0015] In one embodiment, the two-dimensional material layer includes one or two layers selected from a tungsten disulfide layer and a molybdenum ditelluride layer.

[0016] In one embodiment, the semiconductor device is a solar cell, the first electrode and the second electrode are a positive electrode and a negative electrode respectively, and the semiconductor device further includes a transparent substrate layer disposed on a side of the two-dimensional material layer away from the tunneling layer.

[0017] The present application further provides a method for manufacturing a semiconductor device, including the following steps:

[0018] Prepare a tunneling layer on one side of the two-dimensional material layer along its thickness direction,

[0019] Prepare an electrode structure on a side of the tunneling layer away from the two-dimensional material layer, and the electrode structure includes a first electrode and a second electrode spaced apart along a first direction, the first direction being parallel to a plane where the two-dimensional material layer is located;

[0020] Wherein, the material of the tunneling layer includes gallium oxide.

[0021] The present application further provides an electronic product including the semiconductor device as described above.

[0022] In the semiconductor device provided by the present application, using a material including gallium oxide insulating material as the material of the tunneling layer between the electrode structure and the two-dimensional material layer can not only optimize the contact quality between the two-dimensional material layer and the electrode structure, utilize the quantum tunneling effect to reduce the contact resistance and the Schottky barrier, optimize the device performance, but also achieve a good encapsulation effect for the two-dimensional material layer, effectively resist the Fermi level pinning phenomenon and the erosion of environmental pollutants such as water and oxygen. Description of the Drawings

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for use in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained as these drawings.

[0024] Figure 1 It is a schematic structural diagram of a semiconductor device being a field effect transistor.

[0025] Figure 2 It is a schematic structural diagram of a semiconductor device being a solar cell.

[0026] Figure 3 It is the transfer and output characteristic curves of the semiconductor device in Example 1, where V g is the gate voltage, V d is the voltage between the source and the drain, I ON / I OFF is the on-off ratio, I ds is the current between the source and the drain, μ n is the carrier mobility.

[0027] Figure 4 It is the atomic force microscope image of the tunneling layer and the two-dimensional material layer in the semiconductor device of Example 1.

[0028] Figure 5 It is the transfer characteristic curves of the two semiconductor devices of Example 1 and Comparative Example 1, V d is the voltage between the source and the drain, I ds is the current between the source and the drain.

[0029] Figure 6 It is the comparison diagram of the Schottky barrier height of the two semiconductor devices of Example 1 and Comparative Example 1, where V gs is the voltage between the gate and the source, V FB is the flat-band voltage, φ B is the Schottky barrier.

[0030] Figure 7 It is the comparison diagram of the contact resistance of the two semiconductor devices of Example 1 and Comparative Example 1.

[0031] Figure 8 It is the performance statistical chart of the semiconductor device in Example 2, where V gs is the voltage between the gate and the source, V ds is the voltage between the drain and the source, I ds is the current between the source and the drain.

[0032] Figure 9 Relationship diagram of the device performance of the semiconductor device in Example 2 changing with time.

[0033] Figure 10 For the transfer characteristic curve of the semiconductor device in Example 3, where V gs is the voltage between the gate and the source, V ds is the voltage between the drain and the source, I ds is the current between the source and the drain.

[0034] Description of reference numerals:

[0035] 10: Field effect transistor; 110: Gate; 120: Dielectric layer; 130: Two-dimensional material layer; 140: Tunneling layer; 150: Electrode structure; 151: First electrode; 152: Second electrode;

[0036] 20: Solar cell; 210: Transparent substrate layer; 220: Two-dimensional material layer; 230: Tunneling layer; 240: Electrode structure; 241: First electrode; 242: Second electrode. Detailed implementation manners

[0037] For ease of understanding of this application, the following will provide a more comprehensive description of this application with reference to the relevant drawings. The preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure content of this application more thorough and comprehensive.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0039] The term "and / or" used herein includes any one of two or more related listed items, as well as any and all combinations of the related listed items. The said any and all combinations include combinations of any two related listed items, any more related listed items, or all related listed items. For example, "A and / or B" includes three parallel solutions: A, B, and "the combination of A and B".

[0040] In this article, unless otherwise stated, "one or more" means any one of the listed items or any combination of the listed items. Similarly, in other cases where "one or more" and other expressions indicating "one or more" are used, the same understanding is made unless otherwise stated.

[0041] In this text, terms such as "further", "furthermore", "in particular", "for example", "such as", "example", "exemplification", etc. are used for descriptive purposes, indicating an association in terms of covered content between different technical solutions before and after. However, they should not be construed as a limitation on the previous technical solution, nor as a limitation on the scope of protection of this text. In this text, unless otherwise specified, A (such as B) means that B is a non-restrictive example of A, and it can be understood that A is not limited to B.

[0042] In this text, "optionally", "optional", "option" mean that it can be either present or absent, that is, it refers to either of the two parallel options of "present" or "absent". If "optional" appears multiple times in a technical solution, unless otherwise specified and there are no contradictions or mutual constraints, each "optional" is independent. In this application, descriptions such as "optionally contain" and "optionally include" mean "contain or not contain". "Optional component X" means that component X is present or absent, or means containing or not containing this component X.

[0043] In this text, in "first aspect", "second aspect", "third aspect", "fourth aspect", etc., the terms "first", "second", "third", "fourth", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or quantity, nor can they be construed as implicitly indicating the importance or quantity of the indicated technical features. Moreover, "first", "second", "third", "fourth", etc. only serve the purpose of non-exhaustive enumerative description and should be understood not to constitute a closed limitation on quantity.

[0044] In this text, for technical features described in an open-ended manner, it includes both closed technical solutions composed of the listed features and open-ended technical solutions containing the listed features.

[0045] In this text, regarding numerical intervals (i.e., numerical ranges), unless otherwise specified, the distribution of optional numerical values within this numerical interval is considered continuous and includes the two numerical endpoints of this numerical interval (i.e., the minimum value and the maximum value), as well as each numerical value between these two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to integers within this numerical interval, it includes the two endpoint integers of this numerical range, as well as each integer between the two endpoints, which is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be combined. In other words, unless otherwise specified, the numerical ranges disclosed in this text should be understood to include any and all sub-ranges subsumed therein. The "numerical value" in this numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. The "numerical interval" allows for a broad inclusion of numerical interval types such as percentage intervals, ratio intervals, and ratio value intervals.

[0046] Herein, the term "room temperature" or "normal temperature" generally refers to 4°C to 35°C, for example, 20°C ± 5°C. In some embodiments herein, "room temperature" or "normal temperature" refers to 10°C to 30°C. In some embodiments herein, "room temperature" or "normal temperature" refers to 20°C to 30°C.

[0047] In this article, if there are multiple steps involved in the method flow, unless there is a clear different description in this article, there is no strict order restriction for the execution of these steps, and they can be executed in other orders than described. Moreover, any step can include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn, alternating or simultaneously with other steps or parts of sub-steps or stages of other steps.

[0048] The present application provides a semiconductor device, comprising:

[0049] Two-dimensional material layers;

[0050] A tunneling layer is arranged on one side of the two-dimensional material layer along the thickness direction thereof;

[0051] An electrode structure is arranged on a side of the tunneling layer away from the two-dimensional material layer, and the electrode structure includes a first electrode and a second electrode arranged at intervals along a first direction, and the first direction is parallel to the plane where the two-dimensional material layer is located;

[0052] The material of the tunneling layer includes gallium oxide. Further, the material of the tunneling layer is amorphous gallium oxide.

[0053] Understandably, gallium oxide not only possesses good mechanical flexibility and environmental stability, but can also be efficiently transferred to the surface of 2D materials through van der Waals (vdW) stacking technology.

[0054] In the semiconductor device provided in the present application, a gallium oxide insulating material is used as a tunneling layer material between the electrode structure and the two-dimensional material layer, which can not only optimize the contact quality between the two-dimensional material layer and the electrode structure, reduce the contact resistance and Schottky barrier by using the quantum tunneling effect, and optimize the device performance, but also achieve a good packaging effect for the two-dimensional material layer, and effectively resist the Fermi level pinning phenomenon and the erosion of environmental pollutants such as water and oxygen.

[0055] In a specific example, the thickness of the tunneling layer is 1 nm to 5 nm. Specifically, the thickness of the tunneling layer may be, but is not limited to, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, or 5 nm.

[0056] In a specific example, the two-dimensional material layer includes one or more layers of a transition metal chalcogenide layer, a phosphorene layer, a graphene layer, a silicene layer, a two-dimensional perovskite material layer, a transition metal two-dimensional carbide layer, and a transition metal two-dimensional nitride layer. It can be understood that the two-dimensional material layer includes one or more layers of a transition metal chalcogenide layer, a phosphorene layer, a graphene layer, a silicene layer, a two-dimensional perovskite material layer, and a MXenes layer. The chemical formula of MXenes is M n+1 X n T x , where M represents a transition metal element (such as chromium, molybdenum, manganese, iron, cobalt, copper, aluminum, silver, nickel, palladium, platinum, ruthenium, etc.), X represents one or two of carbon and nitrogen, n ranges from 1 to 3, and T represents a functional group on the surface of the material, such as hydroxyl (-OH), halogen group (-F, -Cl), etc.

[0057] In a specific example, the thickness of the two-dimensional material layer is 0.1 nm to 50 nm. Further, the thickness of the two-dimensional material layer is 5 nm to 15 nm. Specifically, the thickness of the two-dimensional material layer can be, but is not limited to, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, 10.5 nm, 11 nm, 11.5 nm, 12 nm, 12.5 nm, 13 nm, 13.5 nm, 14 nm, 14.5 nm, or 15 nm.

[0058] In a specific example, the semiconductor device is a field effect transistor, the first electrode and the second electrode are the source and the drain respectively, the semiconductor device also includes a dielectric layer, the electrode structure also includes a gate, the gate is arranged on the side of the two-dimensional material layer away from the tunneling layer, and the dielectric layer is arranged between the gate and the two-dimensional material layer.

[0059] It can be understood that the gate can cover between the first electrode and the second electrode and not overlap with the first electrode and the second electrode, or the gate covers between the first electrode and the second electrode and overlaps with the first electrode and the second electrode. The two-dimensional material layer between the source and the drain is a channel region.

[0060] Furthermore, the semiconductor device is a field effect transistor, and the two-dimensional material layer includes a transition metal chalcogenide layer. The two-dimensional material layer includes one or two layers of a tungsten disulfide layer and a molybdenum ditelluride layer.

[0061] In a specific example, the thickness of the dielectric layer is 100 nm to 500 nm. Specifically, the thickness of the dielectric layer may be, but is not limited to, 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.

[0062] In a specific example, the material of the dielectric layer includes one or more of oxides, nitrides, organic polymers, self-assembled monolayer materials, and self-assembled multilayer materials. Further, the material of the dielectric layer includes inorganic oxides. Specifically, the dielectric layer material can be, but is not limited to, silicon dioxide.

[0063] As Figure 1 shown in FIG. 1, a field effect transistor 10 includes a stacked gate 110, a dielectric layer 120, a two-dimensional material layer 130, a tunneling layer 140, and an electrode structure 150. The electrode structure 150 includes a first electrode 151 and a second electrode 152 that are spaced apart parallel to the plane where the two-dimensional material layer 130 is located. The first electrode 151 and the second electrode 152 are the source electrode and the drain electrode, respectively.

[0064] In a specific example, the semiconductor device is a solar cell, the first electrode and the second electrode are the positive electrode and the negative electrode, respectively, and the semiconductor device further includes a transparent substrate layer disposed on the side of the two-dimensional material layer facing away from the tunneling layer. It can be understood that the first electrode and the second electrode, as the positive electrode and the negative electrode of the solar cell, are connected to an external circuit through wires to form a conductive loop.

[0065] As Figure 2 shown in FIG. 2, a solar cell 20 includes a stacked transparent substrate layer 210, a two-dimensional material layer 220, a tunneling layer 230, and an electrode structure 240. The electrode structure 240 includes a first electrode 241 and a second electrode 242. The first electrode 151 and the second electrode 152 are the positive electrode and the negative electrode, respectively.

[0066] It can be understood that the preparation method of the above semiconductor device includes the following steps:

[0067] Prepare a tunneling layer on one side of the two-dimensional material layer along its thickness direction,

[0068] Prepare an electrode structure on the side of the tunneling layer facing away from the two-dimensional material layer, and the electrode structure includes a first electrode and a second electrode spaced apart along a first direction, and the first direction is parallel to the plane where the two-dimensional material layer is located;

[0069] Among them, the material of the tunneling layer includes gallium oxide.

[0070] Specifically, the preparation method of the semiconductor device includes the following steps S10 to step S40:

[0071] Step S10: Place liquid gallium on a substrate and heat it to 50 °C to 90 °C. After maintaining for 1 minute to 10 minutes, a thin oxide layer (Ga 2 O 3 ) with a nanoscale thickness is formed.

[0072] It can be understood that the purpose of heating is to maintain the fluidity of the liquid gallium.

[0073] The surface of the above-mentioned substrate has a low surface energy material layer and a transparent substrate. Specifically, the low surface energy material layer can be, but is not limited to, one or more of a silicone layer, a polytetrafluoroethylene (PTFE) layer, a polyethylene layer, a polypropylene layer, a polydimethylsiloxane layer, and an organic monomolecular self-assembled layer. The transparent substrate can be, but is not limited to, one or more of silicon, glass, quartz, ceramics, polyimide, and polycarbonate propylene. The liquid gallium is placed on the side of the substrate with the low surface energy material layer.

[0074] Step S20: Press a glass slide on the droplet and extrude the excess droplet to prepare a tunneling layer on the substrate.

[0075] Specifically, quickly press the glass slide down from top to bottom on the droplet to expand the Ga 2 O 3 thin film to the low surface energy substrate and extrude the excess droplet, then vertically lift the upper glass slide to leave a large-area, flat Ga 2 O 3 thin film with a thickness of about 1 nm to 5 nm on the substrate surface.

[0076] Step S30: Transfer the tunneling layer to the target two-dimensional material layer. Specifically, through a dry transfer platform, using polydimethylsiloxane (PDMS) coated with polypropylene carbonate (PPC) as the transfer medium, after the tunneling layer on the substrate contacts with the polypropylene carbonate (PPC), it is first transferred to the polypropylene carbonate (PPC) and then released to the two-dimensional material layer, and finally transferred to the target two-dimensional material layer.

[0077] It can be understood that for the semiconductor device being the field effect transistor 10, the two-dimensional material layer 130 is disposed on the dielectric layer 120, and the dielectric layer 120 is disposed on the gate 110; for the semiconductor device being the solar cell 20, the two-dimensional material layer 220 is disposed on the transparent substrate layer 210.

[0078] Step S40: Prepare an electrode structure on the above-mentioned Ga 2 O 3 thin film. Specifically, the method for preparing the electrode structure can be, but is not limited to, one or both of thermal evaporation electrodes and mechanical transfer electrodes. Further, the thickness of the electrode structure can be, but is not limited to, 20 nm to 70 nm. Specifically, the thickness of the electrode structure can be, but is not limited to, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, or 70 nm.

[0079] This application also provides an electronic product, including the semiconductor device as described above.

[0080] The following specific embodiments will further illustrate the present application in detail. It should be understood that the following embodiments are only used to further illustrate the present application and should not be construed as limiting the protection scope of the present application. Some non-essential improvements and adjustments made by those skilled in the art based on the above content of the present application fall within the protection scope of the present application. The specific process parameters and the like in the following embodiments are also only an example within a suitable range, that is, those skilled in the art can make selections within a suitable range through the description herein, and do not necessarily have to be limited to the specific values in the following embodiments.

[0081] Embodiment 1

[0082] This embodiment provides a semiconductor device, and its specific preparation steps are as follows:

[0083] 1. WS 2 The nanosheets are obtained from single crystals by mechanical exfoliation and transferred onto a SiO 2 / Si substrate (the thickness of the SiO 2 layer is 300 nm).

[0084] 2. The preparation steps of the continuous thin Ga 2 O 3 film are specifically as follows:

[0085] Place a drop of liquid gallium (Sigma-Aldrich, 99.99% trace metal basis) on a polydimethylsiloxane (PDMS) sheet, which is supported by a glass slide, and heat it to 80 °C to maintain the fluidity of the liquid gallium. After 1 - 10 minutes, a thin oxide layer with a thickness of several nanometers is formed;

[0086] Quickly press another glass slide down onto the droplet from top to bottom to spread the Ga 2 O 3 film to the PDMS area and squeeze out the excess droplet;

[0087] Vertically lift the upper glass slide, leaving a large-area, flat Ga 2 O 3 film with a thickness of about 1 nm - 5 nm and some gallium residues on the PDMS surface;

[0088] Select a clean continuous Ga 2 O 3 film area without gallium residues, and use PDMS coated with polypropylene carbonate (PPC) as the transfer medium to transfer the Ga 2 O 3 film to the target WS 2 nanosheets. The transfer process is as follows: Vertically attach the PPC to the clean Ga 2 O 3The thin film area is heated to 43 °C to make it adhere to the thin film. The PPC is quickly lifted to extract Ga from the bottom PDMS substrate. 2 O 3 thin film, and then it is released onto the WS 2 nanosheets at 80 °C. Subsequently, the residual PPC is cleaned with acetone to obtain WS 2 O 3 thin film-covered WS 2 nanosheets.

[0089] 3. Use lithography technology to design the required electrode pattern, and then deposit a 50-nm-thick gold electrode by thermal evaporation and strip and clean it to prepare a semiconductor device, specifically a WS 2 / Ga 2 O 3 tunnel contact transistor.

[0090] The electrical properties of the device are tested using a Keysight B1500A semiconductor parameter analyzer and a probe station. For example, Figure 3 for the transfer and output characteristic curves of the WS 2 / Ga 2 O 3 tunnel contact transistor, the carrier mobility at room temperature is calculated to be as high as 263 cm² / V·s, which is much higher than the performance of transistor devices made of the same two-dimensional materials reported, and the on-off ratio is greater than 10 6 . Its thickness is measured by a Bruker / Dimension Icon atomic force microscope (AFM), as shown in the appendix Figure 4 The thicknesses of Ga 2 O 3 and WS 2 are 2.6 nm and 7.8 nm, respectively.

[0091] Comparative Example 1

[0092] This comparative example provides a semiconductor device, which is different from Example 1 in that there is no tunneling layer of gallium oxide.

[0093] The specific preparation steps are as follows: WS 2 nanosheets are prepared by mechanical exfoliation and transferred to a SiO 2 / Si substrate. The thicknesses of WS 2 nanosheets and SiO 2 are the same as those in Example 1. A 50-nm-thick gold electrode is prepared on the surface of WS 2 to obtain a semiconductor device without a Ga 2 O 3 tunneling layer, specifically a WS 2 field effect transistor.

[0094] As Figure 5As shown, the transfer characteristic curves of two semiconductor devices, Example 1 and Comparative Example 1, are compared. The on-state current of the semiconductor device of Example 1 with a Ga 2 O 3 tunneling layer is significantly higher than that of the semiconductor device of Comparative Example 1 without a Ga 2 O 3 tunneling layer.

[0095] As Figure 6 shown, the Schottky barrier heights of two devices, Example 1 and Comparative Example 1, are compared. The Schottky barrier height (SBH) is significantly reduced from 258 meV of the device in Comparative Example 1 to 3.70 meV of the device in Example 1, approaching the ideal state of an ohmic contact. As Figure 7 shown, the contact resistances of two devices, Example 1 and Comparative Example 1, are compared. The contact resistance of the semiconductor device of Comparative Document 1 without a Ga 2 O 3 tunneling layer is 32.5 kΩ·μm, while the contact resistance of the semiconductor device of Example 1 with a Ga 2 O 3 tunneling layer is only 2.38 kΩ·μm.

[0096] Example 2

[0097] A large-area Ga 2 O 3 thin film is prepared using a self-made doctor blade in the laboratory and transferred to a 1.5 cm 2 SiO 2 substrate by the transfer method in Example 1. Multiple WS 2 nanofacets have been previously transferred onto this substrate. Then, metal electrodes are fabricated on the Ga 2 O 3 surface to obtain a WS 2 / Ga 2 O 3 tunnel contact transistor array.

[0098] As Figure 8 shown, the performance of 25 devices in the WS 2 / Ga 2 O 3 tunnel contact transistor array of Example 2 is statistically analyzed. The average mobility is 191 ± 43.5 cm² V -1 s -1 , and the on / off ratio is between 10 6 ~10 8 . This demonstrates the application potential of semiconductor devices including Ga 2 O 3 as the tunneling layer material in the large-scale semiconductor technology industry.

[0099] AsFigure 9 The figure shows the relationship between the performance of the semiconductor device in Example 2 and time. The device remains basically stable within a 21-day time period, which also verifies that Ga 2 O 3 The tunneling layer also has a good device encapsulation effect.

[0100] Example 3

[0101] This example provides a semiconductor device. The difference from the example is that the material of the two-dimensional material layer is changed from WS 2 to MoTe 2 ;

[0102] Use the mechanical exfoliation method to prepare MoTe 2 nanosheets with a thickness of 8 nm and transfer them to a SiO 2 / Si substrate (the thickness of the SiO 2 layer is 300 nm). Repeat the preparation steps of the Ga 2 O 3 thin film and the electrode in Example 1 to obtain a semiconductor device, MoTe 2 / Ga 2 O 3 tunnel contact transistor.

[0103] Figure 10 The specific semiconductor device in Example 3 is the transfer characteristic curve of the MoTe 2 / Ga 2 O 3 tunnel contact transistor. The inset is the schematic diagram of the device structure. The electron mobility of the device can reach 96.6 cm 2 V -1 s -1 , demonstrating the universality of the application of Ga 2 O 3 as the tunneling layer in two-dimensional field-effect transistors.

[0104] In this application, the Ga 2 O 3 thin film is used as the tunneling layer of the two-dimensional field-effect transistor to improve the basic performance of the semiconductor device. Among them, the Schottky barrier height (SBH) is significantly reduced from 258 meV to 3.70 meV, approaching the ideal state of ohmic contact. At the same time, the compact Ga 2 O 3 film provides a strong encapsulation to protect the functional layer from Fermi level pinning and environmental pollutants such as water and oxygen molecules. Based on this, the prepared two-dimensional WS 2 transistor has a mobility as high as 263 cm² / V·s at room temperature and a contact resistance as low as 2.38 kΩ·μm, and its performance is better than that of WS 2transistors and demonstrate Ga 2 O 3 thin film in large-scale device fabrication. The above results show that Ga 2 O 3 thin film has practical applications and commercial feasibility in the field of high-performance semiconductor technology.

[0105] This application highlights the significant potential of Ga 2 O 3 thin film as a tunneling contact layer for 2D semiconductor devices. It not only addresses performance challenges but also improves the scalability of the technology, thus opening up new paths for the practical application and commercialization of 2D semiconductor technology. This approach is expected to drive 2D semiconductor technology towards broader application areas by enhancing device performance and reducing manufacturing costs.

[0106] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity in description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0107] The above-described embodiments merely represent several implementation manners of this application, facilitating a specific and detailed understanding of the technical solutions of this application, but should not be construed as limiting the protection scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all fall within the protection scope of this application. It should be understood that the technical solutions obtained by those skilled in the art through logical analysis, reasoning, or limited experiments based on the technical solutions provided in this application are all within the protection scope of the appended claims of this application. Therefore, the protection scope of this patent application should be subject to the content of the appended claims, and the specification can be used to interpret the content of the claims.

Claims

1. A semiconductor device, characterized in that: include: Two-dimensional material layers; A tunneling layer, disposed on one side of the two-dimensional material layer along the thickness direction thereof; An electrode structure is arranged on a side of the tunneling layer away from the two-dimensional material layer, and the electrode structure includes a first electrode and a second electrode arranged at intervals along a first direction, wherein the first direction is parallel to the plane where the two-dimensional material layer is located; Wherein, the material of the tunneling layer includes gallium oxide.

2. The semiconductor device according to claim 1, wherein The thickness of the tunneling layer is 1 nm to 5 nm.

3. The semiconductor device according to claim 1, wherein The two-dimensional material layer includes one or more layers of a transition metal chalcogenide layer, a phosphorene layer, a graphene layer, a silicene layer, a two-dimensional perovskite material layer, a transition metal two-dimensional carbide layer, and a transition metal two-dimensional nitride layer.

4. The semiconductor device according to claim 1, wherein The thickness of the two-dimensional material layer is 0.1 nm to 50 nm.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The semiconductor device is a field effect transistor, the first electrode and the second electrode are a source and a drain respectively, the semiconductor device also includes a dielectric layer, the electrode structure also includes a gate, the gate is arranged on the side of the two-dimensional material layer away from the tunneling layer, and the dielectric layer is arranged between the gate and the two-dimensional material layer.

6. The semiconductor device according to claim 5, characterized in that The two-dimensional material layer includes a transition metal chalcogenide layer.

7. The semiconductor device according to claim 6, wherein: The two-dimensional material layer includes one or both of a tungsten disulfide layer and a molybdenum ditelluride layer.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that: The semiconductor device is a solar cell, the first electrode and the second electrode are respectively a positive electrode and a negative electrode, and the semiconductor device further comprises a transparent substrate layer arranged on a side of the two-dimensional material layer away from the tunneling layer.

9. A method for preparing a semiconductor device, characterized in that: The following steps are involved: A tunneling layer is prepared on one side of the two-dimensional material layer along its thickness direction. An electrode structure is prepared on a side of the tunneling layer facing away from the two-dimensional material layer, wherein the electrode structure comprises a first electrode and a second electrode spaced apart along a first direction, wherein the first direction is parallel to a plane where the two-dimensional material layer is located; Wherein, the material of the tunneling layer includes gallium oxide.

10. An electronic product, characterized in that: Comprising a semiconductor device as described in any one of claims 1 to 8.

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