PCIE verification device and system

Abstract

The invention relates to the technical field of serial interfaces, and discloses a PCIe verification device and system, and the device comprises a bus conversion model unit, a register model unit and a synchronizer unit. The bus conversion model unit is used for receiving an access request sent for the verification component and converting the access request into a command in a specified format; the access request is used for accessing an extended configuration space of the to-be-tested device; the register model unit is used for generating a target expansion configuration space; the target expansion configuration space is used for storing each register value; the command in the specified format is used for accessing a target expansion configuration space; and the synchronizer unit is used for performing data synchronization on the to-be-tested equipment and the target expansion configuration space. According to the scheme, the verification compatibility can be improved while the accuracy of the verification result is ensured, so that each sub-layer can be verified in the development process of each sub-layer of the chip, and the verification convergence rate is improved.

Description

Technical Field

[0001] The present application relates to the technical field of serial interface, and in particular to a PCIE verification device and system. Background Art

[0002] The PCIe (Peripheral Component Interconnect Express, a high-speed serial bus standard) bus is often used for interconnection between chips.

[0003] For PCIe high-speed interface chips, due to the large scale of the protocol and the many details involved, the development of PCIe high-speed interface IP needs to be carried out in layers, and a large number of use cases need to be tested to cover all related functions. Therefore, it is necessary to adopt a large number of third-party use case sets in the IP development process and reuse the use case sets developed at each sub-level at a higher level to increase the scope of verification coverage and reduce the time for verification convergence. However, due to the different use cases used in the sub-layers of the IP system, for example, the use cases developed in the PL layer verification process are based on the interface of the PL layer DUT, and thus these use cases cannot be directly reused in the pcie_system. Therefore, the third-party use case set needs to be regressed for verification convergence only after the entire PCIe IP system is fully developed. Therefore, its verification convergence rate is low, resulting in greater development risks. Summary of the invention

[0004] In view of this, the present application provides a PCIE verification device and system to improve the verification convergence rate.

[0005] In a first aspect, the present application provides a PCIe verification device, the device comprising a bus conversion model unit, a register model unit and a synchronizer unit;

[0006] The bus conversion model unit is used to receive an access request sent to the verification component and convert the access request into a command in a specified format; the access request is used to access the extended configuration space of the device under test;

[0007] The register model unit is used to generate a target extended configuration space; the target extended configuration space is used to store various register values; the command of the specified format is used to access the target extended configuration space;

[0008] The synchronizer unit is used to synchronize data between the device under test and the target extended configuration space.

[0009] In an optional implementation, the target extended configuration space is one of a PCIe 4K Cap space, a CXL configuration space, and a USB configuration space.

[0010] In an optional implementation, the bus conversion model unit includes:

[0011] A bus conversion subunit, configured to receive an access request sent to the verification component and convert the access request into a command in a specified format;

[0012] The automatic response subunit is used to send the command in the specified format to the register model unit and return a corresponding return result for the access request.

[0013] In an optional embodiment, when the access request is a write request, the bus conversion subunit is used to convert the write request into a command in a specified format; the automatic response subunit is used to send the command in the specified format to the register model unit and return a corresponding write completion result for the write request.

[0014] In an optional implementation, when the access request is a read request, the bus conversion subunit is used to convert the read request into a command in a specified format;

[0015] The automatic response subunit is used to send a command of a specified format to the register model unit, and when receiving the register information returned by the register model unit, return the register information in response to the read request.

[0016] In an optional implementation, the register model unit includes:

[0017] A register space, wherein a target extension configuration space is provided in the register space for storing various register values;

[0018] The space application subunit is used to create a target expansion configuration space;

[0019] The space protection subunit is used to ensure that a unique register space exists for each virtual function or physical function of the link.

[0020] In an optional implementation, the space protection subunit is used to:

[0021] When initiating a configuration space application for a physical function or a virtual function in a target link, detecting whether there is allocated space for the physical function or the virtual function in the target link;

[0022] If it exists, the allocated space is returned.

[0023] In an optional implementation manner, the synchronizer unit comprises:

[0024] An output register synchronization subunit, configured to synchronize the updated state to the register in the target extended configuration space when detecting that the register information in the device under test has changed;

[0025] The input register synchronization subunit is used to synchronize the updated state to the register in the device under test when the register model unit updates the register information in the target extended configuration space according to the write request.

[0026] In an optional implementation, the synchronizer unit further includes:

[0027] The power-on synchronization subunit is used to synchronize the register signal in the device under test to the register in the target extended configuration space after the device is powered on.

[0028] In a second aspect, a PCIe verification system is provided, wherein the PCIe verification system includes a device under test, a verification component, and a verification device as described in any one of claims 1 to 9; the verification component is used to send an access request to the verification device to implement verification of the device under test through the verification device.

[0029] In a third aspect, a computer-readable storage medium is provided, on which computer instructions are stored, and the computer instructions are used to enable the above-mentioned PCIe verification device and verification system to achieve corresponding functions.

[0030] The technical solution provided by this application may have the following beneficial effects:

[0031] The present application can verify the PCIe high-speed interface chip through the PCIe verification device, wherein the PCIe verification device includes a bus conversion model unit, a register model unit and a synchronizer unit; wherein the bus conversion model unit is used to receive the access request sent to the verification component and convert the access request into a command of a specified format; the access request is used to access the extended configuration space of the device under test; wherein the register model unit is used to generate a target extended configuration space; the target extended configuration space is used to store various register values; the command of the specified format is used to access the target extended configuration space; wherein the synchronizer unit is used to synchronize the data between the device under test and the target extended configuration space. Through the above-mentioned verification device, different types of access requests for the verification component can be converted into commands of a specified format, so as to access the target extended configuration space, and because the verification device can synchronize the data between the target extended configuration space and the device under test, it can ensure the accuracy of the verification result while improving the verification compatibility, so that each sub-level can be verified separately during the development process of each sub-layer of the chip, thereby improving the verification convergence rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic diagram showing a set of third-party use cases adopted in the process of developing PCIe IP.

[0034] Figure 2 A PL layer verification architecture is shown.

[0035] Figure 3 It is a logical schematic diagram of a PCIe verification device provided in an embodiment of the present application.

[0036] Figure 4 A schematic diagram of the structure of a bus conversion model unit involved in an embodiment of the present application is shown.

[0037] Figure 5 A data write flow chart involved in an embodiment of the present application is shown.

[0038] Figure 6 A data read flow chart involved in an embodiment of the present application is shown.

[0039] Figure 7 A schematic diagram of the structure of a register model unit involved in an embodiment of the present application is shown.

[0040] Figure 8 A schematic structural diagram of a synchronizer involved in an embodiment of the present application is shown.

[0041] Fig. 9 A power-on synchronization logic flow chart involved in an embodiment of the present application is shown.

[0042] Fig.10 An output register synchronization flow chart involved in an embodiment of the present application is shown.

[0043] Fig.11 It is a structural schematic diagram of a computer device provided in an optional embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0045] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between two items, or an association relationship between the two items, or a relationship between indication and being indicated, configuration and being configured, and the like.

[0046] As chip complexity increases, project deadlines are tight and delivery tasks are heavy, the efficiency of chip verification is becoming an increasingly important factor affecting the successful delivery of the entire chip. For the entire chip development cycle, the verification intervention time is generally about 50% of the design and development code is completed before the verification platform is built. In this way, the early stage of the project becomes very precious, and finding as many problems as possible within a limited time, thereby improving the reliability of the chip becomes an important factor affecting whether the chip can be successfully taped out.

[0047] Being able to test all existing use case sets as much as possible at each sub-level of chip verification; being able to reuse the developed use cases at each sub-level as much as possible is one of the important means to improve chip verification efficiency and quality.

[0048] In the chip field, the PCIe interface is a common universal bus interface that provides a reliable data transmission channel and high bandwidth capabilities and is widely used in various computer systems. PCIe IP (Intellectual Property) refers to a verified, reusable integrated circuit design module with a certain specific function. The research and development of PCIe IP is generally divided into four sub-levels: app (Application Layer), tl (Transaction Layer), dl (Data Link Layer), and pl (Physical Layer). However, in the early verification and development process of each PCIe sub-level, due to the lack of 4KCap configuration space in the PCIe protocol in the DUT, the use cases of the third-party use case set cannot be tested; nor can the reusability and scalability of the newly developed use cases at a higher level be guaranteed.

[0049] Please refer to Figure 1 , which shows a schematic diagram of a third-party use case set adopted in the process of developing PCIe IP. Figure 1 As shown, it directly sends a cfg tlp (Configuration Transaction Layer Packet) request to the DUT; therefore, the DUT needs to have complete PL layer, DL layer, and TL layer parsing package cfg tlp message, and requires 4k CAP register space inside the DUT to achieve real access to the 4K CAP space; and these DUT components are also required to return the corresponding response (cpl / cpld) to the verification component.

[0050] Please refer to Figure 2 , which shows a PL layer verification architecture. Figure 2 As shown, the development of all use cases must be driven directly based on the interface of the PLDUT. The limitation of this method is that when the relevant characteristics are verified at a higher level, since there is no interface of this pl DUT, the use cases need to be redeveloped, and the reuse of the use cases cannot be achieved; in addition, since the third-party use case set cannot perceive the existence of the interface of this pl DUT, the third-party use case set cannot be regressed. Therefore, since the PL layer verification does not include other DUT components in the pcie_system DUT except the PL layer, the regression test of the third-party use case set cannot be performed in the PL layer development stage; in addition, since the use cases developed in the PL layer verification process are developed based on the interface of the PL layer DUT, these use cases cannot be directly reused in the pcie_system.

[0051] Therefore, the above solution has the following problems:

[0052] Verification needs to be completed after the entire PCIe IP system is fully developed before regression verification and convergence can be performed on the third-party use case set. For the entire project, the development cycle is already very late, and there is not enough time to fully regress the third-party use case set, which greatly increases the risk of the project being able to converge on time;

[0053] Only the third-party use case set can be regressed on the entire PCIe IP system. When the use case test fails, the relevant problem location cannot be responded to quickly and in time, thus affecting the convergence progress of the entire PCIe system verification;

[0054] The current solution verification found that the problem was complex to locate. Based on the familiarity with the entire business, it was necessary to confirm layer by layer whether the problem occurred in the TL layer, DL layer, or PL layer of the PCIe IP system.

[0055] Since the use cases developed based on the PL layer DUT interface in the PL layer verification development cannot be directly reused in the entire PCIe IP system, it takes time to carry out secondary development and debugging of the use cases, which will greatly increase the time schedule for project convergence.

[0056] To solve the above problems, please refer to Figure 3 , which is a logical schematic diagram of a PCIe verification device provided by an embodiment of the present application, the device includes a bus conversion model unit, a register model unit and a synchronizer unit;

[0057] The bus conversion model unit is used to receive an access request sent to the verification component and convert the access request into a command in a specified format; the access request is used to access the extended configuration space of the device under test;

[0058] The register model unit is used to generate a target extended configuration space; the target extended configuration space is used to store various register values; the command of the specified format is used to access the target extended configuration space;

[0059] The synchronizer unit is used to synchronize data between the device under test and the target extended configuration space.

[0060] It should be noted that if Figure 3 As shown, the PCIe verification device (hereinafter referred to as PCIe Cap Shadow) needs to be communicated with the verification component on the one hand, and also needs to be communicated with the DUT (Device Under Test) on the other hand.

[0061] Generally, in the PCIe verification device, the bus conversion model unit is communicatively connected with the verification component.

[0062] In an embodiment of the present application, the verification component may be a verification component for accessing the PCIe 4K Cap, and the target expansion configuration space is the PCIe 4K Cap space, as well as similar CXL (Compute Express Link) configuration space and USB (Universal Serial Bus) configuration space. In an embodiment of the present application, the logic of the verification device is described as a whole by taking the target expansion configuration space as the PCIe 4K Cap space as an example; when the target expansion configuration space of the embodiment of the present application is the CXL configuration space or the USB configuration space, the same logical function can also be achieved, and this application will not repeat it. At this time, the bus conversion model unit is mainly used to process the access requests of each verification component to the PCIe 4K Cap space, which can convert the access requests of the remaining verification components to the PCIe 4K Cap space into commands that can be recognized by the register model unit (i.e., commands of a specified format); it can also automatically respond to various access requests to the PCIe4k Cap space and return a response.

[0063] In the embodiment of the present application, the register model unit is the main body of the PCIe Cap Shadow. The PCIe 4K Cap space built by the UVM register model is provided in the register model unit, that is, the target expansion configuration space. At this time, the target expansion configuration space can be used to store various register values, and the command of the specified format generated by the bus conversion model unit can be used to access the target expansion configuration space.

[0064] In an embodiment of the present application, the synchronizer unit is mainly used to synchronize various status information between the PCIe Cap Shadow and the actual DUT, that is, whenever data changes occur in either the PCIe Cap Shadow or the actual DUT, the data change information is synchronized to the other, thereby synchronizing the register values ​​between the PCIe Cap Shadow and the DUT.

[0065] Through the above design, the bus conversion model unit converts the access request to the PCIe 4K Cap space into a command in a specified format for the target extended configuration space, thereby ensuring that the access has high compatibility; and because the register values ​​between the PCIeCap Shadow and the DUT are synchronized, the data in the target extended configuration space is actually the data stored in the DUT, so the access result will not be affected, thereby ensuring the accuracy of the verification process.

[0066] Optional, Figure 4 A schematic diagram of the structure of a bus conversion model unit involved in an embodiment of the present application is shown. The bus conversion model unit includes:

[0067] The bus conversion subunit is used to receive access requests sent to the verification component and convert the access requests into commands in a specified format. Specifically, the bus conversion subunit can be used to receive access requests including pcie, cfg, tlp, apb, and access requests customized by various third-party use cases, and convert them into general access requests and forward them to the automatic response subunit.

[0068] The automatic response subunit is used to send the command in the specified format to the register model unit and return the corresponding return result for the access request.

[0069] Specifically, the bus conversion model unit is mainly used to process the access requests of various verification components to the PCIe 4K Cap space. It mainly consists of a bus conversion sub-unit that converts the access requests of other verification components to the PCIe 4K Cap space into commands that the register model unit can recognize; and an automatic response sub-unit that can automatically respond to various access requests to the PCIe 4k Cap space and return a response.

[0070] The bus conversion subunit is specifically used to receive various access requests for the PCIe 4K Cap space, including pcie cfg tlp, apb access requests and various third-party use case set customized access requests, and convert them into general access requests and forward them to the automatic response subunit.

[0071] The automatic response subunit automatically returns a write completion response to the 4K Cap write request received by the bus conversion subunit, and sends the corresponding write request to the register model unit, thereby synchronizing the corresponding register status information to the PCIe 4K Cap space in the register model unit. For the 4K Cap read request received by the bus conversion subunit, the corresponding response is returned after obtaining the corresponding register value by accessing the register unit.

[0072] In an optional embodiment, when the access request is a write request, the bus conversion subunit is used to convert the write request into a command in a specified format; the automatic response subunit is used to send the command in the specified format to the register model unit and return a corresponding write completion result for the write request.

[0073] Please refer to Figure 5 , which shows a data write flow chart involved in an embodiment of the present application. Figure 5As shown, if the access request sent by the PCIe 4K Cap verification component to the bus conversion unit is a write request, the bus conversion sub-unit converts the write request into a command in a specified format and sends it to the register model unit, so that the register model unit writes the data into the PCIe 4K Cap space and synchronizes it to the DUT through the synchronizer, and the automatic response sub-unit returns the write completion result.

[0074] In an optional implementation, when the access request is a read request, the bus conversion subunit is used to convert the read request into a command in a specified format;

[0075] The automatic response subunit is used to send a command of a specified format to the register model unit, and when receiving the register information returned by the register model unit, return the register information in response to the read request.

[0076] Please refer to Figure 6 , which shows a data read flow chart involved in an embodiment of the present application. Figure 6 As shown, if the access request sent by the PCIe 4K Cap verification component to the bus conversion unit is a read request, the bus conversion sub-unit in the bus conversion unit converts the read request into a command of a specified format and sends it to the register model unit, thereby reading the corresponding register value from the register model unit; then the automatic response sub-unit in the bus conversion unit returns the read register value to the PCIe 4K Cap verification component.

[0077] Please refer to Figure 7 , which shows a schematic diagram of the structure of a register model unit involved in an embodiment of the present application. Figure 7 As shown, the register model unit includes:

[0078] A register space, in which a target extension configuration space is provided for storing various register values;

[0079] The space application subunit is used to create a target expansion configuration space;

[0080] The space protection subunit is used to ensure that a unique register space exists for each virtual function or physical function of the link.

[0081] Furthermore, the space protection subunit is used to:

[0082] When initiating a configuration space application for a physical function or a virtual function in a target link, detecting whether there is allocated space for the physical function or the virtual function in the target link;

[0083] If it exists, the allocated space is returned.

[0084] Specifically, the register model unit is the main body of PCIe Cap Shadow. It is mainly composed of the PCIe 4K Cap space (i.e. the above-mentioned register space) built by the UVM register model; the PCIe 4K Cap space protection subunit used to ensure the uniqueness, globality and security of the PCIe 4K Cap space; and the PCIe 4k Cap space application subunit used to apply for the PCIe 4k Cap space.

[0085] PCIe 4K Cap space: implements the Capabilities specified in the PCIe protocol based on the UVM register model; used to store the actual register values ​​of each Capability;

[0086] PCIe 4K Cap space protection subunit: By checking the corresponding link, PF (Physical Function), and VF (Virtual Function) numbers in the PCIe protocol, it ensures the uniqueness and independence of each link, PF, and VF in the entire verification environment architecture; when the same PF or VF of the same link is repeatedly applied for, the previously applied PCIe 4K Cap space will be directly returned;

[0087] PCIe 4K Cap space application subunit: The application and creation of PCIe 4K Cap space can only be done through this subunit, which will create a PCIe 4K Cap space entity inside the register model unit.

[0088] In an optional implementation, the synchronizer unit comprises:

[0089] An output register synchronization subunit, for synchronizing the updated state to the register in the target extended configuration space when detecting that the register information in the device under test has changed;

[0090] The input register synchronization subunit is used to synchronize the updated state to the register in the device under test when the register model unit updates the register information in the target extended configuration space according to the write request.

[0091] Please refer to Figure 8 , which shows a schematic diagram of the structure of a synchronizer unit involved in an embodiment of the present application. The synchronizer unit also includes:

[0092] The power-on synchronization subunit is used to synchronize the register signal in the device under test to the register in the target extended configuration space after the device is powered on.

[0093] It should be noted that the synchronizer unit is mainly used to synchronize the status information between PCIe Cap Shadow and the actual DUT; it is mainly composed of a power-on synchronization subunit that synchronizes the DUT status to the PCIe Cap Shadow after the power-on reset is released; an output register synchronization subunit that monitors the changes in the DUT output register signal at all times and synchronizes it to the PCIe Cap Shadow; and an input register synchronization subunit that synchronizes the status of the register model unit to the DUT input register.

[0094] Among them, the power-on synchronization subunit will directly synchronize all relevant register states in the DUT to the PCIe 4K Cap space after the corresponding power-on reset is released;

[0095] Output register synchronization subunit: This subunit will always detect whether the relevant register signal in the DUT has changed. Once the corresponding signal is detected to have changed, the updated state of the corresponding register signal will be synchronized to the PCIe 4KCap space;

[0096] Input register synchronization subunit: After the register model subunit receives the corresponding write request, this subunit will synchronize the updated state of the corresponding register to the relevant register input signal in the DUT.

[0097] Please refer to Fig. 9 , which shows a power-on synchronization logic flow chart involved in an embodiment of the present application. Fig. 9 As shown, after the power-on reset is released, the power-on synchronization subunit waits until the corresponding reset release indication signal is triggered, then synchronizes all inputs of the DUT and outputs the register status to the PCIe 4K Cap space.

[0098] Please refer to Fig.10 , which shows an output register synchronization flow chart involved in an embodiment of the present application. Fig.10 As shown, the output register synchronization subunit starts working after the power-on synchronization is completed. It will monitor the changes of the DUT output register at all times, and after the corresponding output register changes, the output register synchronization subunit will send the latest output register status information to the PCIe 4K Cap space; the PCIe 4K Cap space will store the corresponding latest output register status in its own internal space.

[0099] In summary, the present application can verify the PCIe high-speed interface chip through the PCIe verification device, wherein the PCIe verification device includes a bus conversion model unit, a register model unit and a synchronizer unit; wherein the bus conversion model unit is used to receive the access request sent to the verification component and convert the access request into a command of a specified format; the access request is used to access the extended configuration space of the device under test; wherein the register model unit is used to generate the target extended configuration space; the target extended configuration space is used to store each register value; the command of the specified format is used to access the target extended configuration space; wherein the synchronizer unit is used to synchronize the data between the device under test and the target extended configuration space. Through the above-mentioned verification device, different types of access requests for the verification component can be converted into commands of a specified format, so as to access the target extended configuration space, and because the verification device can synchronize the data of the target extended configuration space with the device under test, it can ensure the accuracy of the verification result while improving the verification compatibility, so that each sub-level can be verified separately during the development process of each sub-layer of the chip, thereby improving the verification convergence rate.

[0100] A PCIe verification system is also provided in an embodiment of the present application. The PCIe verification system includes a device under test, a verification component, and a verification device with the above functions; wherein the verification component is used to send an access request to the verification device to implement verification of the device under test through the verification device.

[0101] The specific workflow of the above system can be found in Figure 3 The embodiments shown will not be described in detail here.

[0102] The data transmission system in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0103] The present application also provides a computer device, which can be implemented as a verification component in the PCIe verification system shown in the present application embodiment to send an access request to implement verification of the device under test. Fig.11 , Fig.11 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present application, such as Fig.11As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphic information in a graphical user interface on an external input / output device (such as a display device coupled to an interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig.11 A processor 10 is taken as an example.

[0104] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0105] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0106] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0107] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0108] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0109] The embodiment of the present application also provides a computer-readable storage medium. The above method according to the embodiment of the present application can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0110] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A PCIe verification device, characterized in that: The device comprises a bus conversion model unit, a register model unit and a synchronizer unit; The bus conversion model unit is used to receive an access request sent to the verification component and convert the access request into a command in a specified format; the access request is used to access the extended configuration space of the device under test; The register model unit is used to generate a target extended configuration space; The target extended configuration space is used to store various register values; the command of the specified format is used to access the target extended configuration space; The synchronizer unit is used to synchronize data between the device under test and the target extended configuration space.

2. The device according to claim 1, characterized in that The target extended configuration space is one of a PCIe4K Cap space, a CXL configuration space, and a USB configuration space.

3. The device according to claim 1 or 2, characterized in that: The bus conversion model unit comprises: A bus conversion subunit, configured to receive an access request sent to the verification component and convert the access request into a command in a specified format; The automatic response subunit is used to send the command in the specified format to the register model unit and return a corresponding return result for the access request.

4. The device according to claim 3, characterized in that When the access request is a write request, the bus conversion subunit is used to convert the write request into a command in a specified format; the automatic response subunit is used to send the command in the specified format to the register model unit and return a corresponding write completion result for the write request.

5. The device according to claim 3, characterized in that When the access request is a read request, the bus conversion subunit is used to convert the read request into a command in a specified format; The automatic response subunit is used to send a command of a specified format to the register model unit, and when receiving the register information returned by the register model unit, return the register information in response to the read request.

6. The device according to claim 1 or 2, characterized in that: The register model unit comprises: A register space, wherein a target extension configuration space is provided in the register space for storing various register values; The space application subunit is used to create a target expansion configuration space; The space protection subunit is used to ensure that a unique register space exists for each virtual function or physical function of the link.

7. The device according to claim 6, characterized in that The space protection subunit is used for: When initiating a configuration space application for a physical function or a virtual function in a target link, detecting whether there is allocated space for the physical function or the virtual function in the target link; If it exists, the allocated space is returned.

8. The device according to claim 1 or 2, characterized in that: The synchronizer unit comprises: An output register synchronization subunit, configured to synchronize the updated state to the register in the target extended configuration space when detecting that the register information in the device under test has changed; The input register synchronization subunit is used to synchronize the updated state to the register in the device under test when the register model unit updates the register information in the target extended configuration space according to the write request.

9. The device according to claim 8, characterized in that The synchronizer unit further comprises: The power-on synchronization subunit is used to synchronize the register signal in the device under test to the register in the target extended configuration space after the device is powered on.

10. A PCIe verification system, characterized in that: The PCIe verification system includes a device under test, a verification component, and a verification device as described in any one of claims 1 to 9; the verification component is used to send an access request to the verification device to implement verification of the device under test through the verification device.

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