Logic comprehensive stage delay prediction method and system based on machine learning

Abstract

The invention relates to a logic comprehensive stage delay prediction method and system based on machine learning, and belongs to the technical field of digital integrated circuit design automation. According to the method, a concept in the field of natural language processing is used for reference, a time sequence path is analogous to a sentence in a natural language processing task, and a basic element forming the sentence is called token. One time sequence path is formed by connecting a plurality of standard units and a wire net, and each token forming one time sequence path contains both the information of the standard units and the information of the wire net. The method comprises the following steps: firstly, predicting the physical size of a line network in a time sequence path by using a graph attention network, and then capturing the time sequence correlation and physical correlation of each part of the whole time sequence path by using an LSTM-Attention network. According to the method, the time sequence performance after wiring is accurately and efficiently fed forward to the logic synthesis process, so that time sequence optimization and time sequence convergence in the logic synthesis stage are guided, and the number of iterations of chip design is greatly reduced.

Description

Technical Field

[0001] The present invention relates to a method and system for predicting delay in a logic synthesis phase based on machine learning, which are applied in a digital chip design process and belong to the technical field of digital integrated circuit design automation. Background Art

[0002] As the chip scale becomes larger and the chip complexity becomes higher, the chip design cycle is extended accordingly. Using machine learning technology to achieve an "unattended" agile chip design process is the development direction of chip design methodology. The primary challenge in achieving agile chip design is to shorten the running time of electronic design automation (EDA) tools. Timing is an important performance indicator of the chip. Static timing analysis (STA) tools need to be called at each design stage of the digital chip design process to ensure that the design at the current stage meets the timing constraints. If the design at the current stage has a timing violation and the timing violation cannot be fixed at the current stage, it is necessary to go back to the previous stage and redesign. In the traditional digital chip design process, in order to achieve timing convergence, designers often need to perform repeated static timing analysis (STA) and multiple iterations between logic synthesis and placement and routing. Traditional logic synthesis tools use "lookup tables" to estimate delays. This method assumes that most of the delays in the timing path are related to logic gates and ignores the interconnect delay. In advanced processes, wire delays dominate the total path delay, which makes the cost of traditional design processes more expensive and unacceptable.

[0003] Accurate and efficient timing prediction can feed forward the timing performance of the later design stage to the early design stage, guide the timing convergence and timing optimization of the early design, and thus greatly reduce chip design iterations. Existing timing prediction methods based on machine learning are mostly applied to the post-layout stage. For example, predicting the wire delay based on random forest or graph neural network in the post-layout stage, predicting the path delay after wiring based on transformer in the post-layout stage, etc. These works are done under the premise of knowing the location coordinates of the circuit unit or module. In the logic synthesis stage before layout, designers cannot obtain the actual unit location information and the interconnection line information between units, which makes the timing prediction in the logic synthesis stage more difficult. Existing timing prediction methods in the logic synthesis stage based on machine learning have the following shortcomings. First, the method for predicting whether the timing path is a critical path and the method for predicting the wire length of the entire path or the total wire length cannot provide the necessary timing information (timing length, slack) to guide the circuit optimization in the subsequent design stage. Secondly, timing prediction at the net level or cell level instead of the path level will lead to error accumulation due to ignoring the timing correlation and physical correlation on the path. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention provides a path delay prediction method in the logic synthesis stage based on machine learning, which is used to predict the timing path delay after wiring in the logic synthesis stage. The present invention draws on the concepts in the field of natural language processing (NLP) and compares the timing path to a sentence in the natural language processing task. The basic elements that make up a sentence are called tokens. A timing path is composed of multiple standard cells and wire nets. Each "token" that makes up a timing path contains both standard cell information and wire net information. The present invention first uses a graph attention network to predict the physical size of a single wire net in the timing path, and then uses an LSTM-Attention network to capture the timing correlation and physical correlation of each part of the entire timing path.

[0005] Terminology explanation:

[0006] 1. Logic synthesis: Logic synthesis is the process of converting a higher level of abstraction description of a circuit design into an optimized gate-level netlist.

[0007] 2. Static timing analysis (STA): STA (Static timing analysis) is essentially a timing check, and its purpose is to check whether all triggers in the design can work properly. Static timing analysis includes setup time check and hold time check. The setup time check ensures that the data signal reaches the register before the register starts sampling a certain time; the hold time check ensures that the data signal remains valid for a certain time after the register starts sampling, to prevent the register from missing the signal.

[0008] 3. Natural Language Processing: Natural Language Processing (NLP) studies the theories and methods of computer processing text to achieve representation reasoning.

[0009] 4. Layout planning: Layout planning determines the overall structure of the chip, including the chip area, the location of input and output modules, the location of hard macros (modules with fixed area and shape), etc.

[0010] 5. Layout: Layout determines the location of all modules (mainly the location of standard units).

[0011] 6. CTS: CTS (Clock Tree Synthesis) is clock tree synthesis. The clock tree is the physical implementation of the clock signal. Clock tree synthesis aims to generate a clock distribution network to ensure that all components on the chip receive clock signals at the same frequency.

[0012] 7. Wiring: The purpose of wiring is to find the appropriate path according to the logical relationship to interconnect the macro modules, standard cells and input / output interface units (I / O Pad) in the chip core.

[0013] 8. HPWL: HPWL is the Half-perimeter Wirelength model. This model first determines the maximum and minimum values ​​of the coordinates of all pins in a wire net, thereby obtaining a minimum rectangle containing all pins of the wire net. Half of the perimeter of the rectangle is the estimated wire length of the wire net.

[0014] The technical solution of the present invention is as follows:

[0015] A method for predicting delay in a logic synthesis phase based on machine learning comprises the following steps:

[0016] Step 1: Call the electronic design automation tool (EDA) to perform logic synthesis, layout and routing, and timing analysis processes on multiple chip designs to obtain the corresponding netlist and timing report;

[0017] Step 2: Use C++ program to parse the netlist and timing report before and after layout to obtain the wire net features and labels required for training the wire length prediction model;

[0018] Step 3: Input the samples in step 2, i.e., line network features and corresponding labels, into the graph attention network (GAT) for training to obtain the line length prediction model and prediction results;

[0019] Step 4: Use the C++ program to parse the timing report and netlist of the logic synthesis stage, obtain the characteristics of each unit of each timing path, and combine the corresponding wire net related characteristics used to predict the wire length in step 2 and the wire length predicted in step 3 (that is, the output of the prediction model in step 3) to obtain the characteristics of the entire timing path; that is, the characteristics of the entire timing path include the unit related information obtained from the timing report and netlist, as well as the wire net characteristics used by the wire length prediction model in step 2 and the wire length output by the prediction model in step 3; parse the timing report after routing to obtain the corresponding timing path delay label;

[0020] Step 5: Compare the timing path to a sentence in the natural language processing task. The basic element that makes up a sentence is called a token. A timing path consists of multiple standard cells and wire networks. Each "token" that makes up a timing path contains both standard cell information and wire network information. Each "token" is a vector with several features. Embed the entire timing path into a low-dimensional vector.

[0021] Step 6: Input the samples processed by steps 4 and 5, i.e., the features of the entire timing path and the corresponding delay labels of the timing path after routing, into the LSTM-Attention network for training to obtain the path delay model. The model output is the prediction result.

[0022] Furthermore, in step 1, the commercial logic synthesis tool Cadence Genus and the commercial layout and routing tool Cadence Innovus are used to perform logic synthesis and layout and routing on the chip design respectively; static timing analysis (STA) is performed on the netlist of each stage to obtain the corresponding timing report; the content of the timing report mainly includes the timing path and the timing and physical characteristics of each unit constituting the timing path.

[0023] Furthermore, in step 2, the entire netlist is expressed as a directed graph, each net is a node in the graph, and each cell is an edge; the selected net features include: the sum of the cell areas in the entire netlist, the area of ​​the cell connected to the net input, the area of ​​all cells connected to the net, the fan-in size, the fan-out size, the sum and standard deviation of the fan-in and fan-out values ​​of 2-hop neighbors, and the sum of the cell type encoding values ​​connected to the net; all selected net features of each node constitute the feature vector of the node; the label is the HPWL value of the net after layout.

[0024] Furthermore, in step 3, the graph attention network is used to automatically learn the importance of each neighbor node; in order to better reflect the structural information of the graph, the present invention only focuses on the attention coefficient of each node and its 1-hop neighbor node; the initial input of the graph attention network is the combination of feature vectors of each node, and the number of attention heads is set to 2; the graph attention network includes three graph attention layers and two fully connected layers. After the initial input passes through the three graph attention layers h1, h2, and h3, the output results of the first three layers are spliced, instead of using only the output results of the last layer like most GNN-related works.

[0025] Furthermore, in step 4, the characteristics of the selected units on the timing path are: unit type, number of unit fan-outs, unit output load, and unit input transmission delay; these unit characteristics are also closely related to the online delay of the timing path. The number of units constituting different timing path sequences in a circuit design is not unique. The present invention selects the number of units of the timing path with the maximum number of units as the length of all timing path sequences; the timing path sequence with a number of units less than the maximum number of units is filled with 0 to make the sequence length reach the maximum number of units; the corresponding timing path delay label can be extracted from the timing report after wiring, and the timing path characteristics in the logic synthesis stage (i.e., the model input characteristics in step 6) and the timing path delay label after wiring can be matched according to the "start_point" and "end_point" of the timing path in the timing report.

[0026] Furthermore, in step 6, the sequence data representing the timing path is input into the LSTM-Attention network, the circuit delay is propagated step by step along the timing path, and the LSTM can calculate the dependency of the elements in the sequence step by step, and each level will consider the current input and the hidden state of the previous level and other information; the output of the hidden state of the LSTM layer is the input of the attention layer, and the function of the attention layer is to highlight key information; the LSTM-Attention network includes an input layer (X1, X2, X3, X4), an LSTM layer (LSTM1, LSTM2, LSTM3, LSTM4), a hidden state (h1, h2, h3, h4), an attention layer, two fully connected layers, and an output, and the LSTM layer is used to process the sequence data and generate a hidden state, and each hidden state corresponds to the output of a time step.

[0027] A terminal device includes a memory and a processor, wherein the memory stores a computer program, and when the program is executed by the processor, the steps in the aforementioned method for predicting delay in a logic synthesis stage based on machine learning are implemented.

[0028] The beneficial effects of the present invention are:

[0029] The present invention proposes a path delay prediction method in the logic synthesis stage based on machine learning. The timing performance after wiring is fed forward to the logic synthesis process, guiding the timing optimization and timing convergence in the logic synthesis stage, greatly reducing the number of iterations of chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of the path embedding of this method;

[0031] Figure 2 The overall process diagram of this method is shown in FIG.

[0032] Figure 3 Schematic diagram of the graph attention network structure;

[0033] Figure 4 Schematic diagram of the LSTM-Attention network structure. DETAILED DESCRIPTION

[0034] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings, but is not limited thereto.

[0035] Embodiment 1:

[0036] The embodiment of the present invention provides a method for predicting path delay in a logic synthesis phase based on machine learning, such as Figure 2 As shown, it is used to predict the timing path delay of the wiring stage in the logic synthesis stage of chip design. The specific implementation steps are as follows:

[0037] Step 1: The circuit design details used in the embodiment of the present invention are shown in Table 1.

[0038] Table 1 Circuit design details

[0039]

[0040] Call electronic design automation tools (EDA) to perform logic synthesis, layout and routing, and timing analysis processes on multiple chip designs to obtain corresponding netlists and timing reports.

[0041] The commercial logic synthesis tool Cadence Genus and the commercial layout and routing tool Cadence Innovus are used to perform logic synthesis and layout and routing on the RTL circuit design respectively; static timing analysis (STA) is performed on the netlist of each stage to obtain the corresponding timing report; the content of the timing report mainly includes the timing path and the timing and physical characteristics of each unit that constitutes the timing path.

[0042] Step 2: Use a C++ program to parse the netlist and timing reports before and after layout to obtain the wire net features and labels required for training the wire length prediction model.

[0043] The entire netlist is expressed as a directed graph, where each net is a node in the graph and each cell is an edge; the selected net features include: the sum of the cell areas in the entire netlist, the area of ​​the cell connected to the net input, the area of ​​all cells connected to the net, the fan-in size, the fan-out size, the sum and standard deviation of the fan-in and fan-out values ​​of 2-hop neighbors, and the sum of the cell type encoding values ​​connected to the net; all selected net features of each node constitute the feature vector of the node; the label is the HPWL value of the net after layout.

[0044] Step 3: Input the samples in step 2, i.e., line network features and corresponding labels, into the graph attention network (GAT) for training to obtain the line length prediction model and prediction results.

[0045] The graph attention network is used to automatically learn the importance of each neighbor node. In order to better reflect the structural information of the graph, the present invention only focuses on the attention coefficient of each node and its 1-hop neighbor node. The initial input of the graph attention network is the combination of feature vectors of each node, and the number of attention heads is set to 2. The graph attention network includes three graph attention layers and two fully connected layers. The structural diagram is shown in Figure 3 After the initial input passes through the three-layer graph attention layer h1, h2, and h3, the output results of the first three layers are concatenated, instead of using only the output result of the last layer as in most GNN-related works.

[0046] Step 4: Use a C++ program to parse the timing report and netlist of the logic synthesis stage, obtain the characteristics of each unit of each timing path, and combine the corresponding wire net related characteristics used to predict the wire length in step 2 and the wire length predicted in step 3 (that is, the output of the prediction model in step 3) to obtain the characteristics of the entire timing path; that is, the characteristics of the entire timing path include the unit related information obtained from the timing report and netlist, as well as the wire net characteristics used by the wire length prediction model in step 2 and the wire length output by the prediction model in step 3; parse the timing report after routing to obtain the corresponding timing path delay label.

[0047] The characteristics of the cells on the selected timing path are: cell type, cell fan-out number, cell output load, and cell input transmission delay; these cell characteristics are also closely related to the delay on the timing path. The number of cells constituting different timing path sequences in a circuit design is not unique. The present invention selects the number of cells of the timing path with the maximum number of cells as the length of all timing path sequences; the timing path sequence with a cell number less than the maximum number of cells is filled with 0 to make the sequence length reach the maximum number of cells; the corresponding timing path delay label can be extracted from the timing report after wiring, and the timing path characteristics in the logic synthesis stage (i.e., the model input characteristics in step 6) and the timing path delay label after wiring can be matched according to the "start_point" and "end_point" of the timing path in the timing report.

[0048] Step 5: Compare the timing path to a sentence in the natural language processing task. The basic elements that make up a sentence are called tokens. A timing path consists of multiple standard cells and wire networks. Each "token" that makes up a timing path contains both standard cell information and wire network information. Each "token" is a vector with several features. The entire timing path is embedded into a low-dimensional vector. The path embedding diagram is shown below. Figure 1 As shown. Figure 1 In the figure, dff, and2, not, or2, xor2, nand2, and nor2 represent standard cells.

[0049] Step 6: Input the samples processed by steps 4 and 5, i.e., the features of the entire timing path and the corresponding delay labels of the timing path after routing, into the LSTM-Attention network for training to obtain the path delay model. The model output is the prediction result.

[0050] The sequence data representing the timing path is input into the LSTM-Attention network. The circuit delay is propagated step by step along the timing path. LSTM can calculate the dependency of elements in the sequence step by step. Each level will consider the current input and the hidden state of the previous level. The output of the hidden state of the LSTM layer is the input of the attention layer. The function of the attention layer is to highlight key information. The LSTM-Attention network includes an input layer (X1, X2, X3, X4), an LSTM layer (LSTM1, LSTM2, LSTM3, LSTM4), a hidden state (h1, h2, h3, h4), an attention layer, two fully connected layers, and an output. The LSTM layer is used to process sequence data and generate hidden states. Each hidden state corresponds to the output of a time step. The structure is as follows: Figure 4 shown.

[0051] Example 2

[0052] A terminal device includes a memory and a processor, wherein the memory stores a computer program, and when the program is executed by the processor, the steps in the method for predicting the delay in the logic synthesis stage based on machine learning as described in Example 1 are implemented.

[0053] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0054] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A method for predicting delay in logic synthesis phase based on machine learning, characterized in that: The steps include: Step 1: Call electronic design automation tools to perform logic synthesis, layout and routing, and timing analysis processes on multiple chip designs to obtain corresponding netlists and timing reports; Step 2: Use C++ program to parse the netlist and timing report before and after layout to obtain the wire net features and labels required for training the wire length prediction model; Step 3: Input the samples in step 2, i.e., line network features and corresponding labels, into the graph attention network for training to obtain the line length prediction model and prediction results; Step 4: Use the C++ program to parse the timing report and netlist of the logic synthesis stage, obtain the characteristics of each unit of each timing path, and combine the corresponding wire net characteristics used to predict the wire length in step 2 and the wire length predicted in step 3 to obtain the characteristics of the entire timing path; that is, the characteristics of the entire timing path include the unit-related information obtained from the timing report and netlist, as well as the wire net characteristics used by the wire length prediction model in step 2 and the wire length output by the prediction model in step 3; parse the timing report after routing to obtain the corresponding timing path delay label; Step 5: Compare the timing path to a sentence in the natural language processing task. The basic element that makes up a sentence is called a token. A timing path consists of multiple standard cells and wire networks. Each token that makes up a timing path contains both standard cell information and wire network information. Each token is a vector with several features. Embed the entire timing path into a low-dimensional vector. Step 6: Input the samples processed by steps 4 and 5, i.e., the features of the entire timing path and the corresponding delay labels of the timing path after routing, into the LSTM-Attention network for training to obtain the path delay model. The model output is the prediction result.

2. The method for predicting delay in logic synthesis phase based on machine learning according to claim 1, characterized in that: In the step 1, the logic synthesis tool Cadence Genus and the layout and routing tool Cadence Innovus are used to perform logic synthesis and layout and routing on the chip design respectively; Perform static timing analysis on the netlist of each stage to obtain a corresponding timing report; the content of the timing report includes the timing path and the timing and physical characteristics of each unit constituting the timing path.

3. The method for predicting delay in logic synthesis phase based on machine learning according to claim 1, characterized in that: In step 2, the entire netlist is expressed as a directed graph, each net is a node in the graph, and each cell is an edge; the selected net features include: the total area of ​​cells in the entire netlist, the area of ​​cells connected to the net input, the area of ​​all cells connected to the net, the fan-in size, the fan-out size, the sum and standard deviation of the fan-in and fan-out values ​​of 2-hop neighbors, and the sum of the cell type encoding values ​​connected to the net; all selected net features of each node constitute the feature vector of the node; the label is the HPWL value of the net after layout.

4. The method for predicting delay in logic synthesis phase based on machine learning according to claim 1, characterized in that: In step 3, the graph attention network is used to automatically learn the importance of each neighbor node; only the attention coefficient of each node and its 1-hop neighbor node is paid attention; the initial input of the graph attention network is the combination of feature vectors of each node, and the number of attention heads is set to 2; the graph attention network includes three graph attention layers and two fully connected layers.

5. The method for predicting delay in logic synthesis phase based on machine learning according to claim 1, characterized in that: In the step 4, the characteristics of the cells on the selected timing path are: cell type, cell fan-out number, cell output load, and cell input transmission delay; the number of cells of the timing path with the maximum number of cells is selected as the sequence length of all timing paths; the timing path sequence with a cell number less than the maximum number of cells is filled with 0 to make the sequence length reach the maximum number of cells; the corresponding timing path delay label is extracted from the timing report after routing, and the timing path characteristics in the logic synthesis stage and the timing path delay label after routing are matched according to the "start_point" and "end_point" of the timing path in the timing report.

6. The method for predicting delay in logic synthesis phase based on machine learning according to claim 1, characterized in that: In step 6, the sequence data representing the timing path is input into the LSTM-Attention network, the circuit delay is propagated step by step along the timing path, and the LSTM calculates the dependency of the elements in the sequence step by step, and each level considers the current input and the hidden state information of the previous level; the output of the hidden state of the LSTM layer is the input of the attention layer, and the function of the attention layer is to highlight the key information; the LSTM-Attention network includes an input layer (X1, X2, X3, X4), an LSTM layer (LSTM1, LSTM2, LSTM3, LSTM4), a hidden state (h1, h2, h3, h4), an attention layer, two fully connected layers, and an output, and the LSTM layer is used to process the sequence data and generate a hidden state, and each hidden state corresponds to the output of a time step.

7. A terminal device comprises a memory and a processor, wherein the memory stores a computer program, and when the program is executed by the processor, the steps in the method for predicting delay in a logic synthesis stage based on machine learning as described in any one of claims 1 to 6 are implemented.

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