Polarization code optimization method for TLC flash memory

Abstract

The invention provides a polarization code optimization method for a TLC flash memory, which belongs to the technical field of polarization code optimization of an NAND flash memory, and comprises the following steps of: firstly, constructing a polarization code based on a Monte Carlo method: randomly generating code words in each simulation, coding after setting frozen bits, transmitting and reading data through a flash memory channel, counting and accumulating sub-channel error times by using SC decoding, and calculating an error probability; the information bit determination process is optimized according to P / E cycle times for flash memory characteristics; data to be stored in a flash memory are coded based on PC-CASCL, an original binary bit sequence is averagely segmented, PC codes of all sub-segments are added with check bits, after the sub-segments are combined, CRC coding is carried out through a preset polynomial, polar code coding is carried out on a result, and the result is stored in the flash memory. After the coded data is read from the flash memory, decoding is carried out through PC-CASCL, a decoder is initialized, the maximum path number is set, a path list is created, whether the bits are odd-even check bits or not is judged and checked bit by bit, and after all the bits are decoded, an optimal path is selected as output through CRC code check.

Description

Technical Field

[0001] The present invention belongs to the technical field of polarization code optimization of NAND flash memory, and in particular, relates to a polarization code optimization method for TLC flash memory. Background Art

[0002] With the continuous development of high-density flash memory technology, more and more scholars are paying attention to the application of error correction codes to improve the reliability of flash memory. There are two main challenges in the error correction technology using polarization codes in triple-level cell (TLC) flash memory.

[0003] First, in the encoding step of polar codes, the most important step is to obtain the position of information bits through reliability measurement for transmitting information bits. However, since the channel conditions of flash memory chips under different storage conditions are difficult to estimate, the polar code construction method commonly used in the communication field cannot meet the characteristics of flash memory.

[0004] Secondly, in the decoding process of polar codes, since the flash memory read operation is completed by detecting the bit line voltage, only bit information of 0 or 1 can be obtained, which cannot be used directly for decoding. Polar code decoding requires accurate LLR information, that is, the read 0 or 1 bit needs to be converted into LLR information for decoding. The decision basis for polar code decoding is:

[0005]

[0006] Among them, on the one hand, for the frozen bit, since the index position of the frozen bit during polar code encoding is known, it is directly translated into the set frozen bit during decoding, and is set to 0 in this system. On the other hand, for the information bit, decoding is performed by calculating the LLR of the subchannel, that is:

[0007]

[0008] in, is the LLR of each subchannel, which is generally obtained by iterative calculation using a recursive method. The decoder calculates the initial value LLR required for iteration based on the received information, and then calculates the LLR of the odd index bit and the even index bit respectively through the iterative formula, and finally obtains the decision LLR.

[0009]

[0010] in, Formula (3) outputs the LLR of odd indexes, and formula (4) outputs the LLR of even indexes.

[0011] In the SCL decoding method of polar codes, when the path extension value reaches twice the maximum number of paths (2L), path competition begins, and L paths with the smallest path metric values ​​are selected from the 2L paths and saved for the next information bit to be decoded. When the last bit is determined, the path with the smallest PM value is also selected as the decoding result output. The PM value is calculated as follows:

[0012]

[0013] However, selecting the optimal path by PM value is not always reliable. It may cause two problems:

[0014] (1) The path with the smallest PM value selected in the final decision step of SCL decoding is not necessarily the correct decoding result;

[0015] (2) During the SCL decoding process, the L paths selected during path competition do not necessarily include the correct path. The correct path may be pruned incorrectly, and the subsequent extended paths are all obtained on the incorrect path.

[0016] Problem (1) can be improved by using a cyclic redundancy check (CRC)-aided SCL (CASCL) decoding method. However, the CRC check method is only helpful for the final selection of results, and does not help with the error pruning that may occur during the SCL decoding process.

[0017] At present, the flash memory field is more inclined to hard decision sensing, that is, only one bit line voltage detection is performed in the overlapping area of ​​the threshold voltage, and the read data can only be converted into a pair of positive and negative LLRs with equal absolute values. This extremely quantized LLR will cause the quantization of the decision LLR, and the PM value used to select the best path in the SCL decoding algorithm will also be quantized. The quantization of the PM value will also cause problem (2) to be further aggravated, making the PM value in the quantized SCL decoder unable to reliably guide the selection of the winning codeword, and the wrong path is more likely to be expanded, which has a serious impact on the overall decoding performance of the algorithm. As a result, the performance of the polar code used in the flash memory will inevitably degrade. Summary of the invention

[0018] In view of the shortcomings of the prior art, the present invention proposes a polar code optimization method for TLC flash memory, and designs and improves the polar code encoding and decoding for flash memory respectively. For the polar code construction for flash memory, the flash memory chip status with different program / erase (P / E) cycle numbers is tested by the Monte Carlo method to solve the problem that the channel conditions of the real flash memory chip are difficult to estimate, and a polar code construction scheme that meets the characteristics of flash memory is proposed. The information bit results under different P / E cycle numbers and residence times are statistically collated and merged. For polar code decoding, a PC-assisted polar code decoding algorithm is proposed to solve the LLR quantization caused by the flash memory reading characteristics.

[0019] The present invention is implemented by the following technical solution: A polarization code optimization method for TLC flash memory:

[0020] The method specifically comprises the following steps:

[0021] Step 1: construct a polar code based on the Monte Carlo method, determine the code length, number of information bits, and number of simulations of the polar code; randomly generate a code word in each simulation, set the frozen bit and then encode it, transmit and read data through the flash channel, use SC decoding to count and accumulate the number of sub-channel errors, calculate the error probability, and sort the sub-channels to determine the information bit sequence;

[0022] Step 2: Encode the data to be stored in the flash memory based on PC-CASCL, divide the original binary bit sequence into segments evenly, perform PC encoding and check bits on each sub-segment, merge the sub-segments, perform CRC encoding with a preset polynomial, and then perform polar code encoding on the result to generate a codeword to be written into the flash memory and store it in the flash memory;

[0023] Step 3, after reading the encoded data from the flash memory, decode it through PC-CASCL, initialize the decoder, set the maximum number of paths and create a path list, determine and check each bit to see if it is a parity bit, and when all bits are decoded, use CRC code to check and select the optimal path as the output.

[0024] Furthermore, in step 1, it includes:

[0025] Step 1.1, determine the code length N and the number of information bits K of the polar code, and set the total number of Monte Carlo simulations;

[0026] Step 1.2, performing a Monte Carlo simulation cycle; randomly generating a codeword with a code length of N, presetting all positions as frozen bits, and performing polar code encoding on the generated codeword; storing the encoding result in a flash memory chip, transmitting through a channel, and performing error statistics on each sub-channel after SC decoding after reading the data;

[0027] Step 1.3, screening subchannels and determining bit sequence indexes: Through a large number of Monte Carlo simulations, the error frequency of each subchannel is calculated based on the accumulated number of errors and the total number of simulations, and this is used as an approximation of its error probability; all subchannels are sorted from small to large according to the error probability, and the first K subchannels with low error probability are used as information transmission channels, and the remaining NK subchannels are used as frozen channels, so as to determine the sequence index of the information bit;

[0028] Step 1.4, based on the flash memory characteristics, optimize the information bit determination process by analyzing the number of P / E cycles:

[0029] Analyze the impact of P / E cycle times: For different P / E cycle times, the information bit positions obtained using the Monte Carlo method are counted and analyzed.

[0030] Further, in step 1.2, the number of errors in each sub-channel bit is accumulated during multiple simulations;

[0031] In step 1.4, when the P / E number is low, there are fewer different information bits, and the polarization code information bit positions with similar structures are merged; when the P / E number is high, the polarization code information bit positions are selected separately.

[0032] Furthermore, in step 2, it includes:

[0033] Step 2.1, divide the original bit sequence into several sub-segments evenly. If the last part is not long enough, it is also regarded as a sub-segment.

[0034] Step 2.2, PC encoding: perform parity encoding on each sub-segment and add a parity bit to each sub-segment;

[0035] Step 2.3, sub-segment merging: merge the PC-encoded sub-segments in order to obtain a new bit sequence with a specific length;

[0036] Step 2.4, CRC encoding: Use the generating polynomial to perform CRC encoding on the new bit sequence to obtain a bit sequence with a specific length;

[0037] Step 2.5, polarization code encoding: polarization code encoding is performed on a bit sequence with a specific length to obtain a code word with a length of N to be written into the flash memory, thereby completing the encoding process.

[0038] Furthermore, in step 3,

[0039] Step 3.1, initialize the decoder, set the maximum number of paths, and create a path list;

[0040] Step 3.2, perform bit judgment and check pruning: when judging each bit, determine whether the current bit is a parity check bit; retain the path that passes the parity check;

[0041] Step 3.3, perform CRC check on all paths, and select the best path from the paths that pass the CRC check as the final decoding output; if no path passes the CRC check, select the path with the best path metric value as the final output.

[0042] Furthermore, in step 3.2:

[0043] If it is not a parity check bit, skip this step and do not perform parity check operation;

[0044] If it is a parity check bit, a parity check is performed on the leading bits on each path. If the check result is the same as the judgment result of the position, it means that the parity check has passed and the path is retained; otherwise, the path is considered to be decoded incorrectly and is deleted from the path list.

[0045] Furthermore, the polar code optimization method also includes a verification step: using a low-density parity check code widely used in flash memory and a CASCL decoding algorithm commonly used in polar codes as comparisons, respectively verifying the performance of the polar code optimization method in terms of improved error correction success rate, reduced uncorrectable error code rate, and decoding delay compared to the comparison code.

[0046] A polar code optimization system for TLC flash memory:

[0047] The polar code optimization system includes a polar code construction module, a PC-CASCL encoding module, a PC-CASCL decoding module and a verification module;

[0048] The polar code construction module constructs the polar code based on the Monte Carlo method, determines the polar code length, the number of information bits and the number of simulations; randomly generates a code word in each simulation, sets the frozen bit and then encodes it, transmits and reads data through the flash channel, uses SC decoding to count and accumulate the number of sub-channel errors, calculates the error probability, and sorts the sub-channels to determine the information bit sequence;

[0049] The PC-CASCL encoding module encodes the data to be stored in the flash memory based on PC-CASCL, divides the original binary bit sequence into segments evenly, performs PC encoding and check bits on each sub-segment, combines the sub-segments, performs CRC encoding with a preset polynomial, and then performs polar code encoding on the result to generate a codeword to be written into the flash memory and store it in the flash memory;

[0050] After the PC-CASCL decoding module reads the encoded data from the flash memory, it decodes it through PC-CASCL, initializes the decoder, sets the maximum number of paths and creates a path list, determines and checks whether it is a parity bit bit by bit, expands the retained path and updates the path list, and when all bits are decoded, uses CRC code to check and selects the optimal path as output.

[0051] The verification module verifies the advantages of the polar code optimization system in terms of improved error correction success rate, reduced uncorrectable error code rate and decoding delay through a comparison algorithm.

[0052] An electronic device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0053] A computer-readable storage medium is used to store computer instructions, and when the computer instructions are executed by a processor, the steps of the above method are implemented.

[0054] Beneficial effects of the present invention

[0055] The present invention can effectively reduce the pre-order work in polar code encoding without affecting the error correction performance of the polar code applied in the flash memory, thereby increasing the reliability of the flash memory at the end of its life.

[0056] The uncorrectable error bit rate (UBER) is reduced, and the accuracy of data transmission is improved; the present invention can improve the error correction success rate of data stored in the flash memory and the UBER after decoding, thereby increasing the life of the flash memory.

[0057] The present invention greatly reduces the decoding delay required for processing data after reading from the flash memory, has an obvious decoding delay advantage, and improves decoding efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 This is a flow chart of the Monte Carlo reliability measurement for TLC flash memory of the present invention.

[0059] Figure 2 Schematic diagram of the impact of information bit position differences on polar code performance.

[0060] Figure 3 This is a diagram showing the difference in information bit positions under different P / E cycle numbers.

[0061] Figure 4 Schematic diagram of adding PC bits and CRC check bits to the original bit sequence u, where (a) is a schematic diagram of segmenting the original bit sequence u, (b) is a schematic diagram of adding PC bits, and (c) is a schematic diagram of adding CRC check bits.

[0062] Figure 5 This is the flow chart of the segmented PC-CASCL decoding algorithm.

[0063] Figure 6 is the error correction success rate of different ECC methods under different RBER.

[0064] Figure 7 It is the UBER of different ECC methods under different RBER.

[0065] Figure 8 Decoding delay of different ECC methods at different RBER. DETAILED DESCRIPTION

[0066] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] The experimental methods used in the following examples are conventional methods unless otherwise specified. The materials, reagents, methods and instruments used are conventional materials, reagents, methods and instruments in the art unless otherwise specified, and can be obtained through commercial channels by those skilled in the art.

[0068] Combination Figures 1 to 8 In order to correct the errors caused by channel noise, interference and other factors during the storage and reading of data in TLC flash memory, the present invention proposes a polar code optimization method for TLC flash memory. After the steps of PC-CASCL parity pruning, path extension and update, and final CRC check, the output is restored to the binary representation of the information such as files, images, videos, etc. originally stored in the flash memory.

[0069] The method specifically comprises the following steps:

[0070] Step 1: construct a polar code based on the Monte Carlo method, determine the code length, number of information bits, and number of simulations of the polar code; randomly generate a code word in each simulation, set the frozen bit and then encode it, transmit and read data through the flash channel, use SC decoding to count and accumulate the number of sub-channel errors, calculate the error probability, and sort the sub-channels to determine the information bit sequence;

[0071] Regardless of the channel for which polar code error correction is applied, the reliability measurement in polar code encoding, i.e. determining the sequence of information bits and frozen bits in all code words, is the most important step, which largely determines the error correction performance of polar code. In the present invention, the Monte Carlo method is used for reliability measurement: the probability of event occurrence is estimated by the frequency of event occurrence obtained by a large number of repeated experiments.

[0072] The corresponding approach in flash memory is to obtain the specific performance estimation of each polarization sub-channel through a large number of simulations, that is, to count the error probability of each polarization sub-channel, so as to screen the sub-channels. The specific process is as follows: Figure 1 shown.

[0073] First, a codeword with a code length of N is randomly generated, and then all positions are preset to be frozen bits and encoded. The encoding result is stored in the flash memory chip through the channel. After the data is read out, the number of errors in each sub-channel after SC decoding is counted. The first K sub-channels with the least number of errors are used as information transmission channels, and the remaining channels are frozen. In the process, the number of errors in each sub-channel bit is accumulated. When the sub-channel at this position is a sub-channel with low reliability, an error will be accumulated each time a Monte Carlo simulation is performed. Finally, their error probability is approximately determined by the error frequency. After sorting, K sub-channels with low error probability are selected as information bits, and the remaining NK sub-channels are frozen bits, so that the sequence index of the information bit can be obtained. Although the time complexity of the Monte Carlo method is very high, since the present invention selects information bits based on real TLC channels, the performance of the obtained polarization code is very good.

[0074] However, the actual channel status of flash memory is affected by many factors, among which the number of P / E cycles and the residence time are the two most important factors. If the Monte Carlo reliability measurement is performed on the flash memory status in all cases, the time and space overhead required are very large, which is impractical.

[0075] Figure 2 The influence of information bit position differences on the performance of polarization codes is given. As shown in the figure, taking the code length N = 1024 and the code rate R = 8 / 9 as an example, the error correction performance of the optimal information bit position sequence under the current channel conditions is set to 1.0. When the information bit position sequence is different from the optimal case, the error correction capability decreases with the increase in the number of different positions. Moreover, a sudden drop can be seen when the number of different bits reaches 7 and 15, which indicates that there is a change in the position of the key information bit. When the number of different bits is less than or equal to 7, the decrease in error correction capability is small enough to be ignored, so 7 is set as the maximum tolerable number of different bits.

[0076] In the actual application of flash memory, it is not known when the data will be read out when it is stored, and it is difficult to obtain the specific residence time of the data. However, the number of P / E cycles of the flash memory block each time data is stored can be obtained. Therefore, for a fixed number of P / E cycles, the information bit positions obtained using the Monte Carlo method are counted and analyzed, and then the information bit positions of polar codes with similar structures are merged. Figure 3The difference diagram of the information bit position obtained by testing at different P / E times is given. It can be seen that when the P / E times of the flash memory are low, the statistically obtained different information bits are very small and will not have a great impact on the performance of the polarization code. However, in the later period of the flash memory life, that is, when the P / E times are high, the information bit difference between every 100 P / E times is large, and at this time, a more accurate determination of the information bit position is required. Therefore, the information bit selection when the P / E times are low can be combined.

[0077] Step 2: Encode the data to be stored in the flash memory based on PC-CASCL, divide the original binary bit sequence into segments evenly, perform PC encoding and check bits on each sub-segment, merge the sub-segments, perform CRC encoding with a preset polynomial, and then perform polar code encoding on the result to generate a codeword to be written into the flash memory and store it in the flash memory;

[0078] Both CRC code and PC code have the function of correctness check, but compared with CRC code, PC code has much weaker checking ability. It can only detect odd bit errors, but at the same time, the code rate sacrificed is also less. Based on the comprehensive consideration of checking ability and sacrificing code rate, the PC-CASCL decoding algorithm is proposed. The main construction idea is: in the decoding process, PC code with low sacrificing code rate and weak checking ability is used to check the local information bits of the segment to assist the pruning operation in the process; when the decoding terminates and the final output decoding bits are selected, CRC code with high sacrificing code rate and strong checking ability is selected to check all global information bits. However, it should be noted that due to the checking performance limitation of PC code, even if the check bit passes the PC check, it does not mean that the path is correct. These paths that cannot be judged correct or not will be retained together and participate in the subsequent decoding process.

[0079] Figure 4 A schematic diagram of adding PC check bits and CRC check bits to the original bit sequence u is given. The original bit sequence is first segmented in a uniform segmentation manner, and each sub-segment is PC encoded. The sub-segments after PC check encoding are then merged in sequence, and finally CRC encoding and polar code encoding are performed in sequence. The specific encoding algorithm process is as follows:

[0080] (1) The original bit sequence u = (u 1 ,u 2 ,…,u k ) is divided into r 1 sub-segments, each sub-segment is If the last part is less than k 1 , also considered as a sub-segment, such as Figure 4 (a)

[0081] (2) For r 1 Parity coding is performed on each sub-segment;

[0082] (3) Merge the parity-check coded r in (2) in order 1 sub-segments, and the length is k+r 1 The bit sequence u′ is Figure 4 (b)

[0083] (4) Use the generating polynomial g(x) to perform CRC encoding on the bit sequence u′, and obtain a length of k+r 1 +r 2 The bit sequence u″ is Figure 4 (c)

[0084] (5) Polar code the bit sequence u″ to obtain a codeword to be written with a length of N, and the coding is completed.

[0085] Step 3, after reading the encoded data from the flash memory, decode it through PC-CASCL, initialize the decoder, set the maximum number of paths and create a path list, determine and check each bit to see if it is a parity bit, and when all bits are decoded, use CRC code to check and select the optimal path as the output.

[0086] For decoding, since the reading result of the flash memory brings a quantized log-likelihood ratio (LLR), the path metric (PM) value in the serial cancellation list (SCL) algorithm is quantized accordingly. The correct path is likely to be deleted during the decoding process, resulting in decoding errors.

[0087] The overall process of the decoding algorithm is as follows Figure 5 As shown. The difference between the PC-CASCL decoder and the traditional CASCL decoder is that each parity check bit is determined by the parity check function it follows, rather than by the PM value obtained by the likelihood calculation. That is, there is an additional check pruning step when each bit is judged. If it is not a parity check bit, skip this step; otherwise, perform a parity check on the leading bits on each path, and record the check result as c. If it is the same as the judgment result of the position, It means that the parity check has passed and the path is retained; otherwise, the path is considered to be decoded incorrectly and is deleted from the path list. After the parity check is completed for all paths, the pruning operation is completed.

[0088] This cascading method of adding PC codes locally allows the decoding end to remove the paths that have been verified to be erroneous in advance from the decoding list according to the local parity check results during the corresponding SCL decoding process, thereby reducing unnecessary time and space overhead later. At the same time, it makes room in the list for the paths that have not yet been verified to be erroneous, increasing the probability that the correct path will be retained.

[0089] The effect of the present invention is verified by the following examples:

[0090] The CASCL decoding algorithm commonly used in low-density parity check (LDPC) codes and polar codes, which are currently the most widely used in flash memory, is used as the comparison algorithm. In the experiment, the code rate of both polar codes and LDPC codes is set to 8 / 9, and the LDPC code uses the minimum sum decoding algorithm, and the maximum number of iterations is set to 40.

[0091] Figure 6 The error correction success rate of polar code under different raw bit error rates (RBER) is given. Compared with LDPC code, the RBER threshold of 100% error correction success rate of the polar code decoding method is increased by 4.3 times. At the same time, the trend of polar code error correction success rate decreasing with RBER increase is much smaller than that of LDPC code. When the error correction success rate is set to 90%, the RBER threshold of polar code is increased to 6.05 times compared with LDPC code. Since the P / E cycle life of flash memory is reflected in the RBER of read data, using the polar code as the ECC method can significantly improve the error correction success rate of flash memory under high RBER, greatly increasing the reliability of flash memory at the end of its life.

[0092] Figure 7 The uncorrectable bit error rate (UBER) of the polar code decoding algorithm under different RBER is given. The decoding capability of the polar code is related to the maximum decoding L. When L increases, the UBER decreases accordingly. Since the PC-CASCL algorithm provides additional PC checks for L paths to assist in path competition and selection, when L is larger, the method of adding PC checks brings greater performance improvement to the CASCL decoding algorithm. The experimental data that cannot be analyzed when the RBER is too small and a higher L value can make the stored data completely error corrected successfully and the UBER is 0 are excluded. When L=16, the PC-CASCL decoding algorithm can bring nearly 7 times the UBER performance improvement compared to the ordinary CASCL algorithm. At the same time, the performance of the PC-CASCL decoding algorithm is also better than the LDPC code commonly used in current flash memories, and can achieve up to 116 times the UBER performance improvement.

[0093] Figure 8 The decoding delay of the polar code decoding algorithm under different maximum path numbers L is given. The delay data in the figure does not include the time for flash memory reading and transmission. Each data point represents the time required to decode 1 page of data, that is, 131,072 bits of data. The decoding delay of LDPC code is reflected in the number of iterations required for decoding. When the RBER is high, the number of iterations required for successful decoding also increases, so the overall decoding delay will also increase. However, for polar code, the decoding delay does not change with RBER, but is only related to the set maximum path number L. Starting from the SC decoding algorithm, the SC algorithm can be regarded as a CASCL algorithm with only one decoding path. Every time the size of L doubles, the decoding delay increases accordingly. The extra PC check time of the PC-CASCL algorithm compared to the CASCL algorithm can be ignored in the entire decoding algorithm. With the increase of RBER, the advantage of polar code in decoding delay becomes greater and greater. Under the same decoding data volume, the decoding time required for polar code L=16 is only 0.113 times that of LDPC code.

[0094] A polar code optimization system for TLC flash memory, comprising a polar code construction module, a PC-CASCL encoding module, a PC-CASCL decoding module and a verification module;

[0095] The polar code construction module constructs the polar code based on the Monte Carlo method, determines the polar code length, the number of information bits and the number of simulations; randomly generates a code word in each simulation, sets the frozen bit and then encodes it, transmits and reads data through the flash channel, uses SC decoding to count and accumulate the number of sub-channel errors, calculates the error probability, and sorts the sub-channels to determine the information bit sequence;

[0096] The PC-CASCL encoding module encodes the data to be stored in the flash memory based on PC-CASCL, divides the original binary bit sequence into segments evenly, performs PC encoding and check bits on each sub-segment, combines the sub-segments, performs CRC encoding with a preset polynomial, and then performs polar code encoding on the result to generate a codeword to be written into the flash memory and store it in the flash memory;

[0097] After the PC-CASCL decoding module reads the encoded data from the flash memory, it decodes it through PC-CASCL, initializes the decoder, sets the maximum number of paths and creates a path list, determines and checks whether it is a parity bit bit by bit, expands the retained path and updates the path list, and when all bits are decoded, uses CRC code to check and selects the optimal path as output.

[0098] The verification module verifies the advantages of the polar code optimization system in terms of improved error correction success rate, reduced uncorrectable error code rate and decoding delay through a comparison algorithm.

[0099] An electronic device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0100] A computer-readable storage medium is used to store computer instructions, and when the computer instructions are executed by a processor, the steps of the above method are implemented.

[0101] The memory in the embodiment of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory readonly memory, ROM, a programmable read-only memory programmableROM, PROM, an erasable programmable read-only memory erasablePROM, EPROM, an electrically erasable programmable read-only memory electrically EPROM, EEPROM or flash memory. The volatile memory may be a random access memory random access memory, RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory staticRAM, SRAM, dynamic random access memory dynamicRAM, DRAM, synchronous dynamic random access memory synchronousDRAM, SDRAM, double data rate synchronous dynamic random access memory doubledatarateSDRAM, DDRSDRAM, enhanced synchronous dynamic random access memory enhancedSDRAM, ESDRAM, synchronous connection dynamic random access memory synchlinkDRAM, SLDRAM and direct memory bus random access memory directrambusRAM, DRRAM. It should be noted that memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0102] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired such as coaxial cable, optical fiber, digital subscriber line digital subscriber line, DSL or wireless such as infrared, wireless, microwave, etc. to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media integrated. The available medium may be a magnetic medium such as a floppy disk, a hard disk, a magnetic tape, an optical medium such as a high-density digital video disc (DVD), or a semiconductor medium such as a solid state disk (SSD).

[0103] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0104] It should be noted that the processor in the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method embodiment can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor can be a general-purpose processor, a digital signal processor DSP, an application-specific integrated circuit ASIC, a field programmable gate array FPGA or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor can be combined to perform. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0105] The above is a detailed introduction to the polar code optimization method for TLC flash memory described in the present invention, and the principles and implementation methods of the present invention are explained. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A polar code optimization method for TLC flash memory, characterized by: The method specifically comprises the following steps: Step 1: construct a polar code based on the Monte Carlo method, determine the code length, number of information bits, and number of simulations of the polar code; randomly generate a code word in each simulation, set the frozen bit and then encode it, transmit and read data through the flash channel, use SC decoding to count and accumulate the number of sub-channel errors, calculate the error probability, and sort the sub-channels to determine the information bit sequence; Step 2: Encode the data to be stored in the flash memory based on PC-CASCL, divide the original binary bit sequence into segments evenly, perform PC encoding and check bits on each sub-segment, merge the sub-segments, perform CRC encoding with a preset polynomial, and then perform polar code encoding on the result to generate a codeword to be written into the flash memory and store it in the flash memory; Step 3, after reading the encoded data from the flash memory, decode it through PC-CASCL, initialize the decoder, set the maximum number of paths and create a path list, determine and check each bit to see if it is a parity bit, and when all bits are decoded, use CRC code to check and select the optimal path as the output.

2. The polar code optimization method according to claim 1, characterized in that: In step 1, include: Step 1.1, determine the code length N and the number of information bits K of the polar code, and set the total number of Monte Carlo simulations; Step 1.2, performing a Monte Carlo simulation cycle; randomly generating a codeword with a code length of N, presetting all positions as frozen bits, and performing polar code encoding on the generated codeword; storing the encoding result in a flash memory chip, transmitting through a channel, and performing error statistics on each sub-channel after SC decoding after reading the data; Step 1.3, screening subchannels and determining bit sequence indexes: Through a large number of Monte Carlo simulations, the error frequency of each subchannel is calculated based on the accumulated number of errors and the total number of simulations, and this is used as an approximation of its error probability; all subchannels are sorted from small to large according to the error probability, and the first K subchannels with low error probability are used as information transmission channels, and the remaining NK subchannels are used as frozen channels, so as to determine the sequence index of the information bit; Step 1.4, based on the flash memory characteristics, optimize the information bit determination process by analyzing the number of P / E cycles: Analyze the impact of P / E cycle times: For different P / E cycle times, the information bit positions obtained using the Monte Carlo method are counted and analyzed.

3. The polar code optimization method according to claim 2, characterized in that: In step 1.2, the number of errors in each subchannel bit is accumulated during multiple simulations; In step 1.4, when the P / E number is low, there are fewer different information bits, and the polarization code information bit positions with similar structures are merged; when the P / E number is high, the polarization code information bit positions are selected separately.

4. The polar code optimization method according to claim 3, characterized in that: In step 2, include: Step 2.1, divide the original bit sequence into several sub-segments evenly. If the last part is not long enough, it is also regarded as a sub-segment. Step 2.2, PC encoding: perform parity encoding on each sub-segment and add a parity bit to each sub-segment; Step 2.3, sub-segment merging: merge the PC-encoded sub-segments in order to obtain a new bit sequence with a specific length; Step 2.4, CRC encoding: Use the generating polynomial to perform CRC encoding on the new bit sequence to obtain a bit sequence with a specific length; Step 2.5, polarization code encoding: polarization code encoding is performed on a bit sequence with a specific length to obtain a code word with a length of N to be written into the flash memory, thereby completing the encoding process.

5. The polar code optimization method according to claim 4, characterized in that: In step 3, Step 3.1, initialize the decoder, set the maximum number of paths, and create a path list; Step 3.2, perform bit judgment and check pruning: when judging each bit, determine whether the current bit is a parity check bit; retain the path that passes the parity check; Step 3.3, perform CRC check on all paths, and select the best path from the paths that pass the CRC check as the final decoding output; if no path passes the CRC check, select the path with the best path metric value as the final output.

6. The polar code optimization method according to claim 5, characterized in that: In step 3.2: If it is not a parity check bit, skip this step and do not perform parity check operation; If it is a parity check bit, a parity check is performed on the leading bits on each path. If the check result is the same as the judgment result of the position, it means that the parity check has passed and the path is retained; otherwise, the path is considered to be decoded incorrectly and is deleted from the path list.

7. The polar code optimization method according to claim 6, characterized in that: The polar code optimization method also includes a verification step: using a low-density parity check code widely used in current flash memories and a CASCL decoding algorithm commonly used in polar codes as comparisons, respectively verifying the performance of the polar code optimization method in terms of improved error correction success rate, reduced uncorrectable error code rate, and decoding delay compared to the comparison code.

8. A polar code optimization system for TLC flash memory, characterized by: The polar code optimization system includes a polar code construction module, a PC-CASCL encoding module, a PC-CASCL decoding module and a verification module; The polar code construction module constructs the polar code based on the Monte Carlo method, determines the polar code length, the number of information bits and the number of simulations; randomly generates a code word in each simulation, sets the frozen bit and then encodes it, transmits and reads data through the flash channel, uses SC decoding to count and accumulate the number of sub-channel errors, calculates the error probability, and sorts the sub-channels to determine the information bit sequence; The PC-CASCL encoding module encodes the data to be stored in the flash memory based on PC-CASCL, divides the original binary bit sequence into segments evenly, performs PC encoding and check bits on each sub-segment, combines the sub-segments, performs CRC encoding with a preset polynomial, and then performs polar code encoding on the result to generate a codeword to be written into the flash memory and store it in the flash memory; After the PC-CASCL decoding module reads the encoded data from the flash memory, it decodes it through PC-CASCL, initializes the decoder, sets the maximum number of paths and creates a path list, determines and checks whether it is a parity bit bit by bit, expands the retained path and updates the path list, and when all bits are decoded, uses CRC code to check and selects the optimal path as output. The verification module verifies the advantages of the polar code optimization system in error correction success rate, uncorrectable error code rate and decoding delay respectively through a comparison algorithm.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium for storing computer instructions, characterized in that: When the computer instructions are executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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