Semiconductor device with PN junction and preparation method thereof

Abstract

The invention provides a semiconductor device with a PN junction and a preparation method thereof, and belongs to the technical field of semiconductor devices. The semiconductor device comprises a silicon substrate, the surface of one side of the silicon substrate in the thickness direction is provided with an emitter region covering an emitter and an isolation region formed by removing the emitter, a PN junction is formed between the emitter and the silicon substrate, the isolation region is arranged at the edge of the silicon substrate, and at least one side wall of the silicon substrate in the length direction is provided with a cutting surface. An isolation region is arranged at least close to the edge of the cutting surface in the silicon substrate, the surface height of the isolation region is lower than that of the emitter region, the isolation region and the emitter region are connected through a buffer region of a slope structure, and passivation layers cover the surfaces of the emitter, the isolation region and the buffer region. According to the invention, the structure of the isolation region is optimized, a transmission channel of carriers from the emitter region to the cutting surface is effectively cut off, and uniform coverage of the passivation layer is ensured, so that the performance of the device is optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device with a PN junction and a preparation method thereof. Background Art

[0002] In the process of preparing semiconductor devices, separation operations are often performed, that is, the whole component is divided into multiple pieces. Taking crystalline silicon cells as an example, the production process usually uses laser cutting to cut the whole cell after preparation into half or multiple cells, and finally forms a battery assembly based on sliced ​​cells. The edge surface of the semiconductor device cut by laser has very significant carrier recombination, and as the perimeter area ratio of the small-sized device increases, the edge recombination becomes more and more serious. This is because the laser thermal ablation and mechanical damage caused by cutting will produce defects on the surface or edge of the device, causing carriers (electrons and holes) to recombine at the edge of these defects. The rate of edge recombination is usually higher than the rate of recombination in the body because the defect density in the damaged area is greater, which increases the probability of carrier recombination.

[0003] In order to deal with the performance degradation caused by slicing, the industry proposes to use atomic layer deposition (ALD) technology to deposit a certain thickness (about 30nm) of aluminum oxide (AlO) on the edge of the silicon substrate after semiconductor device slicing. x ) for edge passivation. However, this technology has the following shortcomings: aluminum oxide plating affects the appearance of the battery; deposition is time-consuming and gas-consuming, has low production capacity and high cost; the equipment is incompatible with existing production lines; the efficiency improvement effect is limited, and the cost-effectiveness of industrial applications is low. In response to the shortcomings of ALD technology, patent document CN202410971803.5 proposes an edge-isolated sliced ​​battery and a preparation method thereof, which uses a laser to etch the front side of the silicon substrate to form a PN junction-free isolation zone on both sides of the laser crack edge of the battery, so that the crack edge is located within the PN junction-free isolation zone. By introducing an isolation zone without a PN junction, the recombination effect of the crack edge can be effectively suppressed, the carrier recombination rate can be reduced, and the performance of the sliced ​​battery can be improved.

[0004] However, research has found that the existing edge isolation technology has the following problems: the laser etching depth is small, the PN junction isolation area is basically level with the surface of the emission area, and the carrier transmission channel cannot be completely cut off; if the etching depth is increased, a nearly vertical drop structure will appear at the edge of the isolation area, and gaps are likely to appear in the passivation layer during the process of covering the isolation area. These gaps will form new recombination centers, leading to intensified carrier recombination; in addition, after wet etching to remove the damage caused by the nanosecond laser, a planar structure or a large-sized velvet structure is formed on the surface of the isolation area, and the optical reflection loss is large. The above factors will have an adverse effect on device performance. Summary of the invention

[0005] In view of the deficiencies of the prior art, the technical problem to be solved by the present invention is how to optimize the surface structure of the semiconductor device, improve the isolation effect of the edge and the composite effect of the passivation layer, so as to improve the device performance.

[0006] To achieve the above-mentioned purpose, the first aspect of the present invention provides a semiconductor device with a PN junction, comprising a silicon substrate, wherein one side surface of the silicon substrate in the thickness direction has an emitter region covering an emitter and an isolation region formed by removing the emitter, a PN junction is formed between the emitter and the silicon substrate, the isolation region is arranged at the edge of the silicon substrate, at least one side wall in the length direction of the silicon substrate has a cutting surface, the isolation region is arranged at least at the edge close to the cutting surface in the silicon substrate, the surface height of the isolation region is lower than that of the emitter region, the isolation region and the emitter region are connected by a buffer zone with a slope structure, and the surfaces of the emitter, the isolation region and the buffer zone are covered with a passivation layer.

[0007] The present invention optimizes the isolation region structure, and its surface height is lower than that of the emission region, which effectively cuts off the transmission channel of carriers from the emission region to the cut surface, greatly reducing carrier recombination; the isolation region and the emission region are connected by a buffer zone with a slope structure, which helps to cover the passivation layer more evenly, reduce the probability of the occurrence of recombination centers, and further optimize device performance.

[0008] Furthermore, the slope angle of the buffer zone is 20° to 60°, and the vertical height of the buffer zone is 1 to 10 μm. The appropriate size range ensures the lamination effect of the passivation layer and avoids the occurrence of gaps, thereby effectively improving the surface passivation effect and enhancing device performance.

[0009] Furthermore, the width of the isolation region is 20-1000 μm. This width range not only ensures effective isolation between the cut surface and the emission region, suppresses the influence of minority carrier recombination dark current in the cut portion on the working area, but also can be flexibly adjusted according to different device designs and application scenarios, improving device performance while taking into account cost control.

[0010] Furthermore, the surface of the isolation area is a pyramid structure or a tower base structure, the surface of the emission area is a pyramid structure, and the size of the pyramid in the isolation area is smaller than that of the pyramid in the emission area. The small-sized pyramid or tower base structure on the surface of the isolation area can reduce optical reflection loss.

[0011] Furthermore, the surface of the isolation region is a pyramid structure, the pyramid is a quadrangular pyramid, the height is 0.2-2 μm, the length of the bottom side is 0.5-5 μm, and the distribution density of the pyramid is 3×10 5 ~1×10 6 Pieces / mm 2This surface structure greatly increases the light absorption area, improves light capture efficiency, and reduces light reflection loss; at the same time, it can increase the contact area between the passivation layer and the isolation region, further inhibit carrier recombination, and significantly improve device performance.

[0012] Furthermore, the surface of the isolation area is a tower base structure, which is a quadrangular pyramid with a height of less than 0.2 μm and a tower bottom side length of 10 to 50 μm. This surface structure can effectively reduce optical reflection loss, optimize the efficiency of light utilization of the device, and provide a good adhesion foundation for the passivation layer, which helps to improve device performance.

[0013] Furthermore, the passivation layer is a laminated film of aluminum oxide and silicon nitride. This composite passivation layer has a good passivation effect, can reduce surface carrier recombination, and improve device performance.

[0014] A second aspect of the present invention provides a method for preparing the semiconductor device having a PN junction, comprising the following steps: A. Providing a silicon substrate, forming an emitter on one side surface of the silicon substrate in the thickness direction, and forming a PN junction between the emitter and the silicon substrate; B. Perform picosecond laser surface treatment on the emitter, perform acid etching and alkali etching on the laser treated area, remove the emitter at the corresponding area, and change the surface structure of the silicon substrate to form an isolation area and a buffer zone; C. Depositing a passivation layer on the surface of the silicon substrate having the emitter; D. Perform laser non-destructive cutting, and the cutting line is located in the isolation area.

[0015] The present invention uses picosecond laser surface treatment, which has extremely short laser pulse width, concentrated energy, and high laser absorption rate. Compared with nanosecond laser, it can achieve more precise etching depth control. Combined with acid etching and alkaline etching processes, it can accurately remove the emitter at the corresponding part and shape the surface structure of the silicon substrate to form high-quality isolation areas and buffer zones.

[0016] Furthermore, in step B, the laser spot type is a Gaussian spot and / or a flat-top spot. The energy of the Gaussian spot is normally distributed. During laser surface treatment, the high energy in the center can ensure the etching depth, and the energy at the edge gradually decreases; the flat-top spot can make the laser energy more evenly distributed in the action area. The flat-top spot and the Gaussian spot can be used in combination. The main part of the isolation area adopts the flat-top spot to achieve a uniform etching effect, and the edge part adopts the Gaussian spot for etching to form a buffer zone with a natural transition.

[0017] Furthermore, in step B, when the laser spot type is a Gaussian spot, the laser frequency is 400-6000kHz, the power is 10-80W, and the speed is 1000-40000mm / s; when the laser spot type is a flat-top spot, the laser frequency is 3000-6000kHz, the power is 10-100W, and the speed is 2000-40000mm / s. By optimizing the laser process parameters, high-quality isolation areas and buffer zones can be formed, thereby improving the quality of the passivation layer and avoiding the occurrence of gaps.

[0018] Furthermore, in step B, an alkaline solution with a texturing auxiliary agent is used for alkaline etching to form a pyramid structure on the surface of the isolation area; or, in step B, an alkaline solution without a texturing auxiliary agent is used for alkaline etching to form a tower base structure on the surface of the isolation area. By adjusting the etching solution, the surface structure of the isolation area can be regulated, and the chemical etching process is matched with the laser process to obtain an edge isolation structure with excellent surface quality, thereby improving device performance.

[0019] The present invention starts from the two aspects of semiconductor device structure design and preparation process, effectively improves the isolation effect and passivation layer composite effect, reduces optical reflection loss, and improves the performance of semiconductor devices. The specific beneficial effects are as follows: (1) Improve isolation effect and eliminate edge recombination: An isolation zone is set at the edge of the cut surface to completely remove the emitter and is lower than the emitter area, cutting off the carrier transmission channel to the cut surface and inhibiting carrier recombination caused by cut surface defects. This structure can be applied to batteries to reduce dark current loss, increase open circuit voltage and fill factor, and improve photoelectric conversion efficiency.

[0020] (2) Optimize the coverage quality of the passivation layer and improve the surface passivation effect: The buffer zone slope provides a smooth transition basis for the deposition of the passivation layer to avoid covering gaps and defects; the pyramid structure or tower base structure on the surface of the isolation zone increases the contact area, fits the passivation layer tightly, reduces the interface recombination center, and improves the surface passivation effect and device performance.

[0021] (3) Reduce optical reflection loss: The surface of the isolation area is a pyramid structure or a tower base structure, which can increase the absorption and scattering of light, effectively reduce optical reflection loss, and improve the device's efficiency in utilizing light energy.

[0022] (4) Adaptation to multiple slicing modes and advanced semiconductor device technologies: The manufacturing process is compatible with existing production lines and can be flexibly adapted to slicing modes such as “everything is two” and “everything is three” to meet the design requirements of different components. It is also compatible with technical routes such as TOPCon and BC batteries. By adjusting parameters to adapt to different device structures, it promotes the large-scale application of high-performance semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural diagram of a cutting portion of a semiconductor device in a specific implementation manner.

[0024] Figure 2 It is a structural diagram of a cutting portion of a semiconductor device in another specific implementation manner.

[0025] Figure 3 A cross-sectional view of a solar cell structure according to a specific embodiment.

[0026] Figure 4 FIG. 4 is a cross-sectional view of a solar cell structure according to another specific embodiment.

[0027] Figure 5 This is the PL diagram of the sample of Example 1.

[0028] Figure 6 This is the surface morphology of the isolation area of ​​the sample in Example 2.

[0029] Figure 7 This is a side characteristic morphology image of the edge of the isolation zone of the sample of Example 2.

[0030] Figure 8 This is a front feature morphology image of the edge of the isolation zone of the sample of Example 3.

[0031] Fig. 9 This is a side characteristic morphology image of the edge of the isolation zone of the sample of Example 3.

[0032] Fig.10 This is the surface morphology of the isolation area of ​​the sample of Example 5.

[0033] Fig.11 This is a front feature morphology image of the edge of the isolation zone of the sample of Example 5.

[0034] Fig.12 This is a front feature morphology image of the edge of the isolation zone of the sample of Example 6.

[0035] Fig.13 This is a characteristic photograph of the edge of the isolation area of ​​the sample of comparative example 3.

[0036] Fig.14 This is a characteristic photograph of the edge of the isolation area of ​​the sample of Comparative Example 4.

[0037] Description of reference numerals: 1-silicon substrate, 2-cutting surface, 3-emitter region, 4-buffer region, 5-isolation region, 6-emitter, 7-first passivation layer, 8-first electrode, 9-tunneling oxide layer, 10-doped polysilicon layer, 11-second passivation layer, 12-second electrode. DETAILED DESCRIPTION

[0038] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. It should be noted that the following embodiments are only used to illustrate the implementation method and typical parameters of the present invention, and are not used to limit the parameter range described in the present invention. Reasonable changes derived therefrom are still within the scope of protection of the claims of the present invention.

[0039] It should be noted that the endpoints and any values ​​of the ranges disclosed in this article are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically disclosed in this article.

[0040] The specific embodiment of the present invention discloses a semiconductor device with a PN junction and a method for preparing the same. Figure 1 As shown, the semiconductor device includes a silicon substrate 1, and one side wall or both side walls of the silicon substrate 1 in the length direction have a cutting surface 2 generated by laser slicing. One side surface of the silicon substrate 1 in the thickness direction has an emitter region 3, an isolation region 5 and a buffer region 4. An emitter 6 is provided on the emitter region 3, and a PN junction is formed between the emitter 6 and the silicon substrate 1. The surface of the emitter region 3 is a pyramid structure. The isolation region 5 is arranged at the edge close to the cutting surface 2. The surface height of the isolation region 5 is lower than that of the emitter region 3. There is no emitter 6 on its surface. The surface of the isolation region 5 is a pyramid structure, and the size of the pyramid is smaller than that of the emitter region 3. The isolation region 5 can cut off the minority carrier transmission channel from the emitter region 3 to the cutting surface 2, reducing the influence of the cutting edge recombination on the emitter region 3; the surface of the isolation region 5 is a small-sized pyramid structure, which is conducive to reducing optical reflection loss. The buffer region 4 is arranged between the emitter region 3 and the isolation region 5, and is a slope structure to form a transition connection. A first passivation layer 7 is provided on the surface of the silicon substrate 1 having the emitter 6. The passivation layer covers the emitter 6, the isolation region 5 and the buffer region 4. The slope structure of the buffer region 4 helps the first passivation layer 7 to cover more evenly, avoid gaps, and improve the passivation layer composite effect.

[0041] In some specific embodiments, the size of the buffer zone 4 is optimized and designed, and the slope angle of the buffer zone 4 is controlled to be 20°~60°, and the vertical height is 1~10μm. By limiting the size of the buffer zone 4, the edge isolation effect is guaranteed, and there is enough transition space between the emission area 3 and the isolation area 5, ensuring the coverage effect of the first passivation layer 7 and avoiding the occurrence of gaps.

[0042] In some specific embodiments, the surface of the isolation region 5 is optimized to have a pyramid structure, the pyramid is a quadrangular pyramid with a height of 0.2-2 μm, a bottom side length of 0.5-5 μm, and a pyramid distribution density of 3×10 5 ~1×10 6 Pieces / mm 2 This surface structure greatly increases the light absorption area, improves light capture efficiency, and reduces light reflection loss; at the same time, it can increase the contact area between the passivation layer and the isolation region 5, further suppressing carrier recombination.

[0043] In some specific embodiments, the size of the isolation region 5 is optimized and designed, and the width of the isolation region 5 is controlled to be 20~1000μm. The sufficient width can effectively isolate the cut surface 2 and the emission region 3, and suppress the influence of the minority carrier recombination dark current in the cut part on the emission region 3.

[0044] In some specific embodiments, the structure of the first passivation layer 7 is optimized and designed to be a laminated film of aluminum oxide and silicon nitride. This composite passivation layer can reduce surface carrier recombination and improve device performance.

[0045] The method for preparing the semiconductor device with PN junction comprises the following steps: providing a silicon substrate 1, forming an emitter 6 on one side surface of the silicon substrate 1 in the thickness direction, and forming a PN junction between the emitter 6 and the silicon substrate 1. Performing picosecond laser surface treatment on the emitter 6, acid etching and alkaline etching on the laser-treated part, removing the emitter 6 at the corresponding part, and changing the surface structure of the silicon substrate 1 to form an isolation region 5 and a buffer region 4. Depositing a passivation layer on the side surface of the silicon substrate 1 having the emitter 6. Performing laser non-destructive cutting, and the cutting line is located in the isolation region 5.

[0046] In a specific embodiment, in order to form a high-quality isolation area 5 and a buffer area 4, the laser spot type is selected as a Gaussian spot or a flat-top spot, and the laser process parameters are adjusted according to the different spot types. Specifically, when the laser spot type is a Gaussian spot, the laser frequency is controlled to be 400-6000kHz, the power is 10-80W, and the speed is 1000-40000mm / s; when the laser spot type is a flat-top spot, the laser frequency is controlled to be 3000-6000kHz, the power is 10-100W, and the speed is 2000-40000mm / s.

[0047] In some embodiments, a flat-top spot and a Gaussian spot may be used in combination. A flat-top spot is used in the main part of the isolation region 5 to achieve a uniform etching effect, and a Gaussian spot is used for etching the edge to form a buffer zone 4 with a natural transition.

[0048] In a specific embodiment, in order to form a pyramid structure on the surface of the isolation region 5, an alkaline solution with a texturing auxiliary agent added thereto is used for alkaline etching, and the etching process is adjusted to obtain the isolation region 5 with an ideal surface structure.

[0049] Combination Figure 2 As shown, it is another implementation of a semiconductor device with a PN junction. The main difference from the above implementation is that the surface of the isolation region 5 is a tower base structure, which also has the effect of reducing light reflection loss relative to the planar structure.

[0050] In a specific embodiment, the tower base structure is optimized and designed to be a quadrangular pyramid with a height of less than 0.2 μm and a bottom side length of 10 to 50 μm, which can effectively reduce optical reflection loss, optimize the light utilization efficiency of the device, and provide a good adhesion foundation for the passivation layer.

[0051] In addition, the manufacturing process of semiconductor devices with tower base structure and pyramid structure on the surface of isolation area 5 is basically the same, the main difference is that alkaline solution without adding texturing auxiliary agent is used for alkaline etching. By matching chemical etching process with laser process, an edge isolation structure with excellent surface quality can be obtained.

[0052] The above-mentioned preparation technology is applicable to semiconductor devices of various structures. Taking high-efficiency photovoltaic cells as an example, it is suitable for TOPCon cells, BC cells, etc., and can be flexibly adapted to "one slice for two" and "one slice for three" segmentation modes. The isolation structure is located on the side of the device with the PN junction, which can isolate the recombination loss of the cutting edge to the greatest extent, thereby improving the performance of a single device and increasing the overall power of the component.

[0053] Combination Figure 3 As shown, taking a two-piece TOPCon cell as an example, the cell includes a silicon substrate 1, and an emitter 6 is provided on most of the front area of ​​the silicon substrate 1. The area covering the emitter 6 is the emitter region 3, and the surface of the emitter region 3 is a pyramid structure. The first passivation layer 7 is covered on the entire front surface of the silicon substrate 1, and the first electrode 8 passes through the first passivation layer 7 to contact the emitter 6. The back surface of the silicon substrate 1 is sequentially covered with a tunneling oxide layer 9, a doped polysilicon layer 10 and a second passivation layer 11, and the second electrode 12 passes through the second passivation layer 11 to contact the doped polysilicon layer 10. One side of the silicon substrate 1 is a cutting surface 2, and the front of the silicon substrate 1 has an isolation structure near the cutting surface 2. There is no emitter 6 on the surface of the isolation structure, including an isolation region 5 and a buffer region 4. The surface height of the isolation region 5 is lower than the emitter region 3, and the surface of the isolation region 5 is a small-sized pyramid structure. The isolation region 5 is transitionally connected to the emitter region 3 through the buffer region 4 with a slope structure.

[0054] In some embodiments, an isolation region 5 may also be provided on the edge of the silicon substrate 1 that is not close to the cutting surface 2. Still taking the two-piece TOPCon battery as an example, in combination with Figure 4 As shown, an isolation region 5 is provided on the edge of the silicon substrate 1 close to the cutting surface 2, and isolation regions 5 are also provided on other edges, so that carrier recombination at the non-cutting edge of the battery can be reduced, and the battery efficiency is further improved. The surrounding isolation regions 5 are connected to the corresponding buffer regions 4, and the entire front surface of the silicon substrate 1 is evenly covered with a first passivation layer 7.

[0055] The technical solutions and effects of the present invention are illustrated below through specific embodiments.

[0056] Example 1

[0057] Prepare an n-type silicon substrate, perform front texturing, and perform standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter. Slot the middle area on the front of the passivation film, remove the corresponding part of the emitter, and form an isolation area. The edge of the isolation area is a nearly vertical structure with a vertical height of 3~5μm. Aluminum oxide film and silicon nitride film are deposited on the front of the passivation film to form a front passivation layer, and sample (A) is obtained.

[0058] Prepare an n-type silicon substrate, perform front texturing, and perform standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter. Slot the middle area on the front of the passivation film, remove the corresponding part of the emitter, and form an isolation area. The edge of the isolation area is a buffer area with a slope structure. The slope angle of the buffer area is controlled to be 65°~75°, and the vertical height is 3~5μm. Aluminum oxide film and silicon nitride film are deposited on the front of the passivation film to form a front passivation layer to obtain sample (B).

[0059] Prepare an n-type silicon substrate, perform front texturing, and perform standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter. Slot the middle area on the front of the passivation film, remove the corresponding part of the emitter, and form an isolation area. The edge of the isolation area is a buffer area with a slope structure. The slope angle of the buffer area is controlled to be 20°~30° and the vertical height is 3~5μm. Aluminum oxide film and silicon nitride film are deposited on the front of the passivation film to form a front passivation layer to obtain sample (C).

[0060] Prepare an n-type silicon substrate, perform front texturing, and perform standard RCA cleaning. Diffusion of boron on the front of the silicon substrate forms a boron emitter. Slot the middle area on the front of the passivation film, remove the corresponding part of the emitter, and form an isolation area. The edge of the isolation area is a buffer area with a slope structure. The slope angle of the buffer area is controlled to be 50°~60° and the vertical height is 3~5μm. Aluminum oxide film and silicon nitride film are deposited on the front of the passivation film to form a front passivation layer to obtain sample (D).

[0061] The four samples prepared were subjected to PL testing, and the results are as follows: Figure 5As shown, it can be seen that setting a slope buffer zone at the edge of the isolation zone is beneficial to improving the coverage quality of the passivation layer and reducing the interface recombination center. The best effect is achieved when the slope angle of the buffer zone is 50°~60°.

[0062] Example 2

[0063] Prepare an n-type silicon substrate, perform front texturing, back polishing, and standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter. Etch the back to remove the borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are deposited on the back in sequence, and annealed at 900°C for 30 minutes to obtain a TOPCon structure passivation film. Perform picosecond laser surface treatment on an area with a certain width corresponding to the reserved cutting line of the passivation film. The laser spot type is a flat-top spot, the laser frequency is 3000kHz, the power is 30W, and the speed is 10000mm / s to remove the emitter at the corresponding position. Acid etching and alkali etching are performed on the laser-treated area in turn to form an isolation area with a width of about 200μm. The surface structure of the isolation area is as follows Figure 6 As shown in the figure, the tower base is a quadrangular pyramid with a height of less than 0.1 μm and a bottom side length of about 20 μm. The edges of the isolation zone on both sides are buffer zones with slope structures, and their side morphology is as follows: Figure 7 As shown, the vertical height of the buffer zone is about 3.2μm and the slope angle is about 30°. Aluminum oxide film is prepared on the front of the passivation sheet, and silicon nitride film is deposited on both sides. The passivation sheet is metallized on both sides. Laser cutting is performed along the reserved cutting line to obtain two sliced ​​batteries.

[0064] 2000 sliced ​​cells were prepared by the above method, and the performance of the sliced ​​cells was tested by Suns-Voc. The average performance test results of the samples are as follows: open circuit voltage ( V oc ) = 737.2mV, short-circuit current density ( J sc )=41.13mA / cm 2 , fill factor ( FF ) = 86.15%, efficiency ( Eff )=26.42%.

[0065] The sliced ​​cells prepared in Example 2 were selected to make 10 108 half-cell battery assemblies, each with a size of 9.1 cm × 18.2 cm. After testing, the average power of the assembly was 445.9W.

[0066] Example 3

[0067] Prepare an n-type silicon substrate, perform front texturing, back polishing, and standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter. Picosecond laser surface treatment is performed on the area with a certain width corresponding to the reserved cutting line of the passivation sheet. The laser spot type is Gaussian spot, the laser frequency is 3000kHz, the power is 30W, and the rate is 10000mm / s to remove the emitter at the corresponding position. Etch the back to remove the borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are deposited on the back in sequence, and annealing treatment is performed at 900℃ for 30 minutes to obtain a TOPCon structure passivation sheet. Acid etching and alkaline etching are performed on the laser-treated parts in turn to form an isolation area with a width of about 200μm. The surface of the isolation area is a tower base structure with a height of less than 0.1μm and a tower bottom side length of about 20μm. The edges on both sides of the isolation area are buffer zones with a slope structure, and its front morphology is as follows. Figure 8 As shown in the figure, the edges of the buffer zone and the isolation zone are smooth. Fig. 9 As shown, the vertical height of the buffer zone is about 3.6μm and the slope angle is about 55°. Aluminum oxide film is prepared on the front of the passivation sheet, and silicon nitride film is deposited on both sides. The passivation sheet is metallized on both sides. Laser cutting is performed along the reserved cutting line to obtain two sliced ​​cells.

[0068] 2000 sliced ​​cells were prepared by the above method, and the performance of the sliced ​​cells was tested by Suns-Voc. The average performance test results of the samples are as follows: open circuit voltage ( V oc ) = 738.0mV, short-circuit current density ( J sc )=41.10mA / cm 2 , fill factor ( FF ) = 86.64%, efficiency ( Eff )=26.46%.

[0069] The sliced ​​cells prepared in Example 3 were selected to make 10 108 half-cell battery assemblies, each with a size of 9.1 cm × 18.2 cm. After testing, the average power of the assembly was 446.7W.

[0070] Example 4

[0071] Prepare an n-type silicon substrate, perform front texturing, back polishing, and standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter. Etch the back to remove the borosilicate glass. Nano silicon oxide and phosphorus-doped amorphous silicon are deposited on the back in sequence, and annealed at 900°C for 30 minutes to obtain a TOPCon structure passivation sheet. Picosecond laser surface treatment is performed on the area with a certain width corresponding to the reserved cutting line of the passivation sheet. The laser spot type is Gaussian spot, the laser frequency is 2000kHz, the power is 35W, and the rate is 5000mm / s to remove the emitter at the corresponding position. Acid etching and alkaline etching are performed on the laser-treated parts in sequence to form an isolation area with a width of about 100μm. The surface of the isolation area is a tower base structure with a height of less than 0.2μm and a tower bottom side length of about 10μm. The edges on both sides of the isolation area are buffer zones with a slope structure. The vertical height of the buffer zone is about 5.0μm and the slope angle is about 60°. Aluminum oxide film is prepared on the front of the passivation sheet, and then silicon nitride film is deposited on both sides. The passivation sheet is metallized on both sides. Laser cutting is performed along the reserved cutting line to obtain two sliced ​​batteries.

[0072] 2000 sliced ​​cells were prepared by the above method, and the performance of the sliced ​​cells was tested by Suns-Voc. The average performance test results of the samples are as follows: open circuit voltage ( V oc ) = 737.8mV, short-circuit current density ( J sc )=41.12mA / cm 2 , fill factor ( FF ) = 86.53%, efficiency ( Eff )=26.45%.

[0073] Example 5

[0074] Prepare an n-type silicon substrate, perform front texturing, back polishing, and standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter. Etch the back to remove the borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are deposited on the back in sequence, and annealed at 900°C for 30 minutes to obtain a TOPCon structure passivation sheet. Perform picosecond laser surface treatment on an area with a certain width corresponding to the reserved cutting line of the passivation sheet. The laser spot type is a flat-top spot, the laser frequency is 4000kHz, the power is 40W, and the speed is 20000mm / s to remove the emitter at the corresponding position. Acid etching and alkaline etching are performed on the laser-treated parts in turn, and a texturing auxiliary agent is added to the alkaline solution to form an isolation area with a width of about 200μm. The surface of the isolation area is a pyramid structure, such as Fig.10 and Fig.11 As shown, the pyramid is a four-sided pyramid with a height of about 1 μm, a base length of about 2 μm, and a distribution density of about 6×10 5 Pieces / mm 2The edges of the isolation area on both sides are buffer zones with a slope structure. The vertical height of the buffer zone is about 4μm and the slope angle is about 25°. An aluminum oxide film is prepared on the front of the passivation sheet, and then a silicon nitride film is deposited on both sides. The passivation sheet is metallized on both sides. Laser cutting is performed on the reserved cutting line to obtain two sliced ​​batteries.

[0075] 2000 sliced ​​cells were prepared by the above method, and the performance of the sliced ​​cells was tested by Suns-Voc. The average performance test results of the samples are as follows: open circuit voltage ( V oc ) = 737.5mV, short-circuit current density ( J sc )=41.11mA / cm 2 , fill factor ( FF ) = 86.37%, efficiency ( Eff )=26.43%.

[0076] The sliced ​​cells prepared in Example 5 were selected to make 10 108 half-cell battery assemblies, each with a size of 9.1 cm × 18.2 cm. After testing, the average power of the assembly was 446.2W.

[0077] Example 6

[0078] Prepare an n-type silicon substrate, perform front texturing, back polishing, and standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter. Etch the back to remove the borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are deposited on the back in sequence, and annealed at 900°C for 30 minutes to obtain a TOPCon structure passivation wafer. Picosecond laser surface treatment is performed on an area with a certain width corresponding to the reserved cutting line of the passivation wafer. The laser spot type is Gaussian spot, the laser frequency is 3000kHz, the power is 30W, and the speed is 10000mm / s to remove the emitter at the corresponding position. Acid etching and alkaline etching are performed on the laser-treated parts in turn, and a texturing auxiliary agent is added to the alkaline solution to form an isolation area with a width of about 100μm. The surface of the isolation area is a pyramid structure, such as Fig.12 As shown, the pyramid is a four-sided pyramid with a height of about 1 μm, a base length of about 2 μm, and a distribution density of about 6×10 5 Pieces / mm 2 The edges of the isolation area on both sides are buffer zones with a slope structure. The vertical height of the buffer zone is about 4μm and the slope angle is about 55°. An aluminum oxide film is prepared on the front of the passivation sheet, and then a silicon nitride film is deposited on both sides. The passivation sheet is metallized on both sides. Laser cutting is performed on the reserved cutting line to obtain two sliced ​​batteries.

[0079] 2000 sliced ​​cells were prepared by the above method, and the performance of the sliced ​​cells was tested by Suns-Voc. The average performance test results of the samples are as follows: open circuit voltage ( Voc ) = 738.3mV, short-circuit current density ( J sc )=41.06mA / cm 2 , fill factor ( FF ) = 87.02%, efficiency ( Eff )=26.51%.

[0080] The sliced ​​cells prepared in Example 6 were selected to make 10 108 half-cell battery assemblies, each with a size of 9.1 cm × 18.2 cm. After testing, the average power of the assembly was 447.0W.

[0081] Example 7

[0082] Prepare an n-type silicon substrate, perform front texturing, back polishing, and standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter. Etch the back to remove the borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are deposited on the back in sequence, and annealed at 900°C for 30 minutes to obtain a TOPCon structure passivation sheet. Picosecond laser surface treatment is performed on the area with a certain width corresponding to the reserved cutting line of the passivation sheet. The laser spot type is Gaussian spot, the laser frequency is 3000kHz, the power is 45W, and the rate is 20000mm / s to remove the emitter at the corresponding position. Acid etching and alkaline etching are performed on the laser-treated parts in turn, and a texturing auxiliary agent is added to the alkaline solution to form an isolation area with a width of about 200μm. The surface of the isolation area is a pyramid structure with a height of about 2μm, a bottom side length of about 4μm, and a distribution density of about 2×10 5 Pieces / mm 2 The edges of both sides of the isolation area are buffer zones with a slope structure. The vertical height of the buffer zone is about 5μm and the slope angle is about 45°. An aluminum oxide film is prepared on the front of the passivation sheet, and then a silicon nitride film is deposited on both sides. The passivation sheet is metallized on both sides. Laser cutting is performed on the reserved cutting line to obtain two sliced ​​batteries.

[0083] 2000 sliced ​​cells were prepared by the above method, and the performance of the sliced ​​cells was tested by Suns-Voc. The average performance test results of the samples are as follows: open circuit voltage ( V oc ) = 738.1mV, short-circuit current density ( J sc )=41.08mA / cm 2 , fill factor ( FF ) = 86.81%, efficiency ( Eff )=26.48%.

[0084] Comparative Example 1 Prepare an n-type silicon substrate, perform front texturing, back polishing, and standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter; the back is etched to remove the borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back, and annealed at 900°C for 30 minutes to obtain a TOPCon structure passivation film. Prepare an aluminum oxide film on the front of the passivation film, and then deposit a silicon nitride film on both sides. Metallize the passivation film on both sides. Laser cutting is performed on the reserved cutting line to obtain two sliced ​​batteries. Aluminum oxide with a thickness of 30nm is deposited on the cut surface using ALD.

[0085] 2000 solar cells were prepared by the above method, and the performance of solar cells was tested by Suns-Voc. The average performance test results of the samples are as follows: open circuit voltage ( V oc ) = 732.1mV, short-circuit current density ( J sc )=41.80mA / cm 2 , fill factor ( FF ) = 85.26%, efficiency ( Eff )=25.71%.

[0086] The sliced ​​cells prepared in Comparative Example 1 were selected to make 10 108 half-cell battery modules, each with a size of 9.1 cm × 18.2 cm. After testing, the average power of the module was 439.7W.

[0087] Comparative Example 2 Prepare an n-type silicon substrate, perform front texturing, back polishing, and standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter; the back is etched to remove the borosilicate glass. Nano silicon oxide and phosphorus-doped amorphous silicon are deposited on the back in sequence, and annealed at 900°C for 30 minutes to obtain a TOPCon structure passivation sheet. Nanosecond laser surface treatment is performed on the area with a certain width corresponding to the reserved cutting line of the passivation sheet. The laser spot type is a flat-top spot, the laser frequency is 3000kHz, the power is 30W, and the rate is 10000mm / s to remove the emitter at the corresponding position. Acid etching and alkaline etching are performed on the laser-treated parts in sequence to form an isolation area with a width of about 200μm, and the surface of the isolation area is a planar structure. The edges on both sides of the isolation area are nearly vertical structures with a vertical height of less than 1μm. Aluminum oxide film is prepared on the front of the passivation sheet, and then silicon nitride film is deposited on both sides. The passivation sheet is metallized on both sides. Laser cutting is performed on the reserved cutting line to obtain two sliced ​​batteries.

[0088] 2000 solar cells were prepared by the above method, and the performance of solar cells was tested by Suns-Voc. The average performance test results of the samples are as follows: open circuit voltage ( V oc) = 734.6mV, short-circuit current density ( J sc )=41.58mA / cm 2 , fill factor ( FF ) = 85.66%, efficiency ( Eff )=25.88%.

[0089] The sliced ​​cells prepared in Comparative Example 1 were selected to make 10 108 half-cell battery modules, each with a size of 9.1 cm × 18.2 cm. After testing, the average power of the module was 441.5W.

[0090] Comparative Example 3 Prepare an n-type silicon substrate, perform front texturing, back polishing, and standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter; the back is etched to remove the borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are deposited on the back in sequence, and annealed at 900°C for 30 minutes to obtain a TOPCon structure passivation sheet. Picosecond laser surface treatment is performed on an area with a certain width corresponding to the reserved cutting line of the passivation sheet. The laser spot type is a flat-top spot, the laser frequency is 6000kHz, the power is 150W, and the rate is 40000mm / s to remove the emitter at the corresponding position. Acid etching and alkaline etching are performed on the laser-treated parts in turn to form an isolation area with a width of about 100μm. The surface of the isolation area is a tower base structure. The tower base is a quadrangular pyramid with a height of less than 0.1μm and a tower bottom side length of about 20μm. The edges on both sides of the isolation area are nearly vertical structures, and their side morphology is as follows Fig.13 As shown, the vertical height is about 5μm. Aluminum oxide film is prepared on the front of the passivation sheet, and silicon nitride film is deposited on both sides. The passivation sheet is metallized on both sides. Laser cutting is performed along the reserved cutting line to obtain two sliced ​​batteries.

[0091] 2000 sliced ​​cells were prepared by the above method, and the performance of the sliced ​​cells was tested by Suns-Voc. The average performance test results of the samples are as follows: open circuit voltage ( V oc ) = 735.4mV, short-circuit current density ( J sc )=41.37mA / cm 2 , fill factor ( FF ) = 85.95%, efficiency ( Eff )=26.14%.

[0092] The sliced ​​cells prepared in Comparative Example 3 were selected to make 10 108 half-cell battery modules, each with a size of 9.1 cm × 18.2 cm. After testing, the average power of the module was 442.6W.

[0093] Comparative Example 4 Prepare an n-type silicon substrate, perform front texturing, back polishing, and standard RCA cleaning. Boron is diffused on the front of the silicon substrate to form a boron emitter; the back is etched to remove the borosilicate glass. Picosecond laser surface treatment is performed on the area with a certain width corresponding to the reserved cutting line of the passivation sheet. The laser spot type is Gaussian spot, the laser frequency is 5000kHz, the power is 100W, and the rate is 20000mm / s to remove the emitter at the corresponding position. Etch the back to remove the borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are deposited on the back in sequence, and annealing treatment is performed at 900℃ for 30 minutes to obtain a TOPCon structure passivation sheet. Acid etching and alkaline etching are performed on the laser-treated parts in turn to form an isolation area with a width of about 200μm. The surface of the isolation area is a tower base structure with a height of less than 0.1μm and a tower bottom side length of about 20μm. The edges on both sides of the isolation area are buffer zones with a slope structure, and its front morphology is as follows. Fig.14 As shown, the edges of the buffer zone and the isolation zone are not flat, and a broken line structure appears. The vertical height of the buffer zone is about 4μm, and the slope angle is about 60°. An aluminum oxide film is prepared on the front of the passivation sheet, and then a silicon nitride film is deposited on both sides. The passivation sheet is metallized on both sides. Laser cutting is performed on the reserved cutting line to obtain two sliced ​​batteries.

[0094] 2000 sliced ​​cells were prepared by the above method, and the performance of the sliced ​​cells was tested by Suns-Voc. The average performance test results of the samples are as follows: open circuit voltage ( V oc ) = 736.7mV, short-circuit current density ( J sc )=41.26mA / cm 2 , fill factor ( FF ) = 86.05%, efficiency ( Eff )=26.28%.

[0095] Table 1 Comparison of battery performance between examples and comparative examples

[0096] The device performances of Examples 2-7 and Comparative Examples 1-4 are shown in Table 1. The test results show that applying the technology of the present invention to batteries can effectively improve the performance of sliced ​​batteries, significantly reduce the battery efficiency loss caused by the slicing process, and increase the power of photovoltaic modules.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor device having a PN junction, characterized in that: The invention comprises a silicon substrate, wherein one side surface of the silicon substrate in the thickness direction has an emitter region covering an emitter and an isolation region formed by removing the emitter, a PN junction is formed between the emitter and the silicon substrate, the isolation region is arranged at the edge of the silicon substrate, at least one side wall in the length direction of the silicon substrate has a cutting surface, the isolation region is arranged at least at the edge close to the cutting surface in the silicon substrate, the surface height of the isolation region is lower than that of the emitter region, the isolation region and the emitter region are connected by a buffer region with a slope structure, and the surfaces of the emitter, the isolation region and the buffer region are covered with a passivation layer.

2. The semiconductor device having a PN junction according to claim 1, characterized in that: The slope angle of the buffer zone is 20° to 60°, and the vertical height of the buffer zone is 1 to 10 μm.

3. The semiconductor device having a PN junction according to claim 1, characterized in that: The width of the isolation region is 20-1000 μm.

4. The semiconductor device with a PN junction according to any one of claims 1 to 3, characterized in that: The surface of the isolation area is a pyramid structure or a tower base structure, the surface of the emission area is a pyramid structure, and the pyramid size of the isolation area is smaller than the pyramid size of the emission area.

5. The semiconductor device having a PN junction according to claim 4, characterized in that: The surface of the isolation area is a pyramid structure, the pyramid is a quadrangular pyramid, the height is 0.2-2 μm, the length of the bottom side is 0.5-5 μm, and the distribution density of the pyramid is 3×10 5 ~1×10 6 Pieces / mm 2 .

6. The semiconductor device having a PN junction according to claim 4, characterized in that: The surface of the isolation zone is a tower base structure, the tower base is a quadrangular pyramid with a height less than 0.2 μm and a tower base side length of 10 to 50 μm.

7. The semiconductor device having a PN junction according to claim 1, characterized in that: The passivation layer is a laminated film of aluminum oxide and silicon nitride.

8. A method for preparing a semiconductor device having a PN junction as claimed in any one of claims 1 to 7, characterized in that: The following steps are involved: A. Providing a silicon substrate, forming an emitter on one side surface of the silicon substrate in the thickness direction, and forming a PN junction between the emitter and the silicon substrate; B. Perform picosecond laser surface treatment on the emitter, perform acid etching and alkali etching on the laser treated area, remove the emitter at the corresponding area, and change the surface structure of the silicon substrate to form an isolation area and a buffer zone; C. Depositing a passivation layer on the surface of the silicon substrate having the emitter; D. Perform laser non-destructive cutting, and the cutting line is located in the isolation area.

9. The preparation method according to claim 8, characterized in that: In the step B, the spot type of the laser is a Gaussian spot and / or a flat-top spot.

10. The preparation method according to claim 9, characterized in that: In the step B, when the laser spot type is a Gaussian spot, the laser frequency is 400-6000kHz, the power is 10-80W, and the speed is 1000-40000mm / s; when the laser spot type is a flat-top spot, the laser frequency is 300-6000kHz, the power is 10-100W, and the speed is 2000-40000mm / s.

11. The preparation method according to claim 8, characterized in that: In the step B, alkaline etching is performed using an alkaline solution to which a texturing auxiliary agent is added, so that a pyramid structure is formed on the surface of the isolation area; Alternatively, in the step B, alkaline etching is performed using an alkaline solution without adding a texturing auxiliary agent, so that a tower base structure is formed on the surface of the isolation area.

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