JTAG standard pin test system
By designing a JTAG standard pin testing system including a board to be tested, a riser card, a test card, a TAP controller and a test data generation device, the problem that the test machine in the prior art can only be used for multiple slots to be tested on the same board to be tested is solved, and the testing support for multiple slots to be tested on different boards to be tested is realized.
Patent Information
- Application Number
- CN202311675216.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-07
- Publication Date
- 2025-06-10
AI Technical Summary
In the prior art, the test machine can only be used for multiple slots to be tested on the same board to be tested for JTAG standard pin testing, and cannot be used for multiple slots to be tested for different boards to be tested.
A JTAG standard pin testing system is designed, including the board to be tested, multiple adapter cards, multiple test cards, TAP controller and test data generation device. By forming electrical connections between the slots to be tested, it is a series link between different series links to be tested, or the electrical connections between the adapter cards form a series link. The TAP controller provides a JTAG format test signal, so that the test card can be tested on JTAG standard pins.
It is realized that the test machine can be used to multiple slots to be tested on different boards to be tested for JTAG standard pin testing, solving the problem of limited application scope of test machines in the prior art.
Smart Images
Figure CN120121967A_ABST
Abstract
Description
Technical Field
[0001] A test system, in particular, refers to a JTAG standard pin test system. Background Art
[0002] Conventionally, a plurality of slots to be tested on a board to be tested is tested by inserting a corresponding test card into each slot to be tested, and then connecting the test cards in series to perform a JTAG standard pin test.
[0003] However, the existing testing method is only suitable for testing multiple test slots of the same test board. That is, different test boards have differences in the number of test slots, configuration positions, etc., and the number of test cards used and the way in which the test cards are connected in series are also different. Therefore, it is impossible to use the same test machine to test multiple test slots of different test boards.
[0004] In summary, it can be seen that the prior art has long had the problem that the test machine can only provide multiple test slots on the same test board for JTAG standard pin testing, so it is necessary to propose an improved technical means to solve this problem. Summary of the invention
[0005] In view of the problem in the prior art that a test machine can only provide multiple test slots on the same test board for JTAG standard pin testing, the present invention discloses a JTAG standard pin testing system, wherein:
[0006] The first embodiment of the present invention discloses a JTAG standard pin test system, which includes: a board to be tested, a plurality of adapter cards, a plurality of test cards, a test access port (TAP) controller and a test data generating device.
[0007] The board to be tested has a plurality of slots to be tested, and the slots to be tested are electrically connected to each other to form different serial chains to be tested.
[0008] Each adapter card has an adapter card plugging interface, an adapter card gold finger interface, a first JTAG input interface, a first JTAG output interface, a second JTAG input interface, and a second JTAG output interface. The test data input (TDI) pins of the adapter card plugging interface, the adapter card gold finger interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface, and the second JTAG output interface are electrically connected to each other. The test data output (TDO) pins are electrically connected to each other. The test clock (TCK) pins are electrically connected to each other. The test mode select (TMS) pins are electrically connected to each other. And the test reset (TRST) pins are electrically connected to each other.
[0009] The gold finger interface of each adapter card is plugged into the corresponding slot to be tested, so that the TDI pins of the corresponding plugged-in gold finger interface of the adapter card and the slot to be tested are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other.
[0010] Each test card has a boundary scan element, a JTAG input interface, a JTAG output interface, and a gold finger interface. The TDI pins of the boundary scan element, the JTAG input interface, the JTAG output interface, and the gold finger interface are electrically connected to each other. The TDO pins are electrically connected to each other. The TCK pins are electrically connected to each other. The TMS pins are electrically connected to each other. And the TRST pins are electrically connected to each other.
[0011] The gold finger interface of each test card is plugged into the plugging interface of the corresponding adapter card, so that the TDI pins of the corresponding plugged-in gold finger interface and the plugging interface of the adapter card are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other. And the test card tests the JTAG standard pins with the JTAG format test signals provided by the corresponding plugged-in slot to be tested and feeds back the JTAG format test result signals.
[0012] The TAP controller is electrically connected to different chains to be tested in series, converts different test data into corresponding JTAG format test signals to be provided to the corresponding chains to be tested in series, receives the JTAG format test result signals from the chains to be tested in series, and converts them into response data.
[0013] The test data generation device is electrically connected to the TAP controller, provides test data to the TAP controller, and receives response data corresponding to the slot to be tested from the TAP controller.
[0014] The JTAG standard pin test system disclosed in the second embodiment of the present invention includes: a board to be tested, a plurality of adapter cards, a plurality of test cards, a TAP controller, and a test data generation device.
[0015] The board to be tested has a plurality of slots to be tested.
[0016] Each adapter card has an adapter card plugging interface, an adapter card gold finger interface, a first JTAG input interface, a first JTAG output interface, a second JTAG input interface, and a second JTAG output interface. The TDI pins of the adapter card plugging interface, the adapter card gold finger interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface, and the second JTAG output interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other.
[0017] The adapter card gold finger interface of each adapter card is correspondingly plugged into each slot to be tested, so that the TDI pins of the correspondingly plugged adapter card gold finger interface and the slot to be tested are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; and the adapter cards are electrically connected to each other through their respective first JTAG input interfaces and first JTAG output interfaces or second JTAG input interfaces and second JTAG output interfaces to form a series connection chain for different adapter cards.
[0018] Each test card has a boundary scan element, a JTAG input interface, a JTAG output interface, and a gold finger interface. The TDI pins of the boundary scan element, the JTAG input interface, the JTAG output interface, and the gold finger interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other.
[0019] The gold finger interface of each test card is plugged into the adapter card plugging interface of each adapter card correspondingly, so that the TDI pins of the correspondingly plugged gold finger interface and adapter card plugging interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; and the test card performs tests on the JTAG standard pins based on the JTAG format test signals provided by the correspondingly plugged adapter card and feeds back the JTAG format test result signals.
[0020] The TAP controller is electrically connected in series with different adapter cards to form a chain, converts different test data into corresponding JTAG format test signals to provide to the corresponding adapter card series chain, receives the JTAG format test result signals from the adapter card series chain and converts them into response data.
[0021] The test data generation device is electrically connected to the TAP controller, provides test data to the TAP controller, and receives the response data corresponding to the slot to be tested from the TAP controller.
[0022] The system disclosed by the present invention is as above. The slots to be tested are electrically connected to each other to form different series chains to be tested, or the adapter cards are electrically connected to each other through their respective first JTAG input interfaces and first JTAG output interfaces or second JTAG input interfaces and second JTAG output interfaces to form different adapter card series chains. The TAP controller provides corresponding JTAG format test signals to the series chain to be tested or the adapter card series chain so that the test card performs tests on the JTAG standard pins.
[0023] Through the above technical means, the present invention can achieve the technical effect of the testing machine performing JTAG standard pin tests on multiple slots to be tested on different circuit boards to be tested. Description of the Drawings
[0024] Figure 1 It is a system block diagram showing the first embodiment of the JTAG standard pin test of the present invention.
[0025] Figure 2 It is a block diagram of the adapter card showing the first embodiment of the JTAG standard pin test of the present invention.
[0026] Figure 3 It is a block diagram of the test card showing the first embodiment of the JTAG standard pin test of the present invention.
[0027] Figure 4 It is a system block diagram showing the second embodiment of the JTAG standard pin test of the present invention.
[0028] Figure 5It is a block diagram of an adapter card showing the second embodiment of the JTAG standard pin test of the present invention.
[0029] Figure 6 It is a block diagram of a test card showing the second embodiment of the JTAG standard pin test of the present invention.
[0030] Figure 7 It is a test architecture diagram showing the second embodiment of the JTAG standard pin test of the present invention.
[0031] The description of the reference numerals is as follows:
[0032] 10: Printed circuit board to be tested
[0033] 11: Slot to be tested
[0034] 111: First slot to be tested
[0035] 112: Second slot to be tested
[0036] 113: Third slot to be tested
[0037] 114: Fourth slot to be tested
[0038] 115: Fifth slot to be tested
[0039] 116: Sixth slot to be tested
[0040] 117: Seventh slot to be tested
[0041] 118: Eighth slot to be tested
[0042] 20: Adapter card
[0043] 201: First adapter card
[0044] 202: Second adapter card
[0045] 203: Third adapter card
[0046] 204: Fourth adapter card
[0047] 205: Fifth adapter card
[0048] 206: Sixth adapter card
[0049] 207: Seventh adapter card
[0050] 208: Eighth adapter card
[0051] 21: Adapter card plug-in interface
[0052] 22: Adapter card gold finger interface
[0053] 23: First JTAG input interface
[0054] 24: First JTAG output interface
[0055] 25: Second JTAG input interface
[0056] 26: Second JTAG output interface
[0057] 30: Test card
[0058] 301: First test card
[0059] 302: Second test card
[0060] 303: Third test card
[0061] 304: Fourth test card
[0062] 305: Fifth test card
[0063] 306: Sixth test card
[0064] 307: Seventh test card
[0065] 308: Eighth test card
[0066] 31: Boundary scan element
[0067] 32: JTAG input interface
[0068] 33: JTAG output interface
[0069] 34: Gold finger interface
[0070] 40: TAP controller
[0071] 50: Test data generation device
[0072] 61: TDI pin
[0073] 62: TDO pin
[0074] 63: TCK pin
[0075] 64: TMS pin
[0076] 65: TRST pin Detailed implementation mode
[0077] The following will describe in detail the implementation mode of the present invention in conjunction with the drawings and embodiments, so as to fully understand how the present invention uses technical means to solve technical problems and achieve the realization process of technical effects and implement accordingly.
[0078] The following describes the JTAG standard pin test system of the first implementation aspect disclosed by the present invention, and please refer to Figure 1 as shownFigure 1 FIG. 4 is a system block diagram of a first embodiment of a JTAG standard pin test according to the present invention.
[0079] The first embodiment of the present invention discloses a JTAG standard pin test system, which includes: a board to be tested 10 , a plurality of adapter cards 20 , a plurality of test cards 30 , a test access port (TAP) controller 40 and a test data generating device 50 .
[0080] The tested board 10 has a plurality of tested slots 11, and the tested slots 11 are electrically connected to each other to form different tested serial chains. Specifically, assuming that the tested board 10 has a first tested slot, a second tested slot, a third tested slot and a fourth tested slot, the first tested slot and the second tested slot are electrically connected to each other to form a first tested serial chain, and the third tested slot and the fourth tested slot are electrically connected to each other to form a second tested serial chain; the first tested slot and the third tested slot are electrically connected to each other to form a first tested serial chain, and the second tested slot and the fourth tested slot are electrically connected to each other to form a second tested serial chain; this is only for illustration and does not limit the scope of application of the present invention.
[0081] Please refer to Figure 2 As shown, Figure 2 The block diagram of the adapter card of the first embodiment of the JTAG standard pin test of the present invention is shown. Each adapter card 20 has an adapter card plug-in interface 21, an adapter card gold finger interface 22, a first JTAG input interface 23, a first JTAG output interface 24, a second JTAG input interface 25 and a second JTAG output interface 26. The test data input (Test Data Input, TDI) pins 61 of the adapter card plug-in interface 21, the adapter card gold finger interface 22, the first JTAG input interface 23, the first JTAG output interface 24, the second JTAG input interface 25 and the second JTAG output interface 26 are electrically connected to each other, the test data output (Test Data Output, TDO) pins 62 are electrically connected to each other, the test clock (TestClock, TCK) pins 63 are electrically connected to each other, the test mode select (Test Mode Select, TMS) pins 64 are electrically connected to each other, and the test initialization (Test Initialization) pins 65 are electrically connected to each other. Reset, TRST) pins 65 are electrically connected to each other.
[0082] The adapter card gold finger interface 22 of each adapter card 20 is correspondingly plugged into each slot to be tested 11, so that the correspondingly plugged adapter card gold finger interface 22 and the TDI pins 61 of the slot to be tested 11 are electrically connected to each other, the TDO pins 62 are electrically connected to each other, the TCK pins 63 are electrically connected to each other, the TMS pins 64 are electrically connected to each other, and the TRST pins 65 are electrically connected to each other.
[0083] Based on the above example, the first adapter card is correspondingly plugged into the first slot to be tested, the second adapter card is correspondingly plugged into the second slot to be tested, the third adapter card is correspondingly plugged into the third slot to be tested, and the fourth adapter card is correspondingly plugged into the fourth slot to be tested, that is, the adapter card gold finger interface of the first adapter card and the TDI pins of the first slot to be tested are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other, the adapter card gold finger interface of the second adapter card and the TDI pins of the second slot to be tested are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other, and the rest are similar and so on, which will not be repeated here.
[0084] Please refer to Figure 3 As shown, Figure 3 The block diagram of the test card of the first embodiment of the JTAG standard pin test of the present invention is shown. Each test card 30 has a boundary scan element 31, a JTAG input interface 32, a JTAG output interface 33 and a gold finger interface 34. The TDI pins 61 of the boundary scan element 31, the JTAG input interface 32, the JTAG output interface 33 and the gold finger interface 34 are electrically connected to each other, the TDO pins 62 are electrically connected to each other, the TCK pins 63 are electrically connected to each other, the TMS pins 64 are electrically connected to each other, and the TRST pins 65 are electrically connected to each other.
[0085] The gold finger interface 34 of each test card 30 is correspondingly connected to the adapter card plug-in interface 21 of each adapter card 20, so that the TDI pins 61 of the correspondingly connected gold finger interface 34 and the adapter card plug-in interface 21 are electrically connected to each other, the TDO pins 62 are electrically connected to each other, the TCK pins 63 are electrically connected to each other, the TMS pins 64 are electrically connected to each other, and the TRST pins 65 are electrically connected to each other.
[0086] Based on the above example, the first test card is correspondingly plugged into the first adapter card, the second test card is correspondingly plugged into the second adapter card, the third test card is correspondingly plugged into the third adapter card, and the fourth test card is correspondingly plugged into the fourth adapter card, that is, the TDI pins of the gold finger interface of the first test card and the adapter card plug-in interface of the first adapter card are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other, the TDI pins of the gold finger interface of the second test card and the adapter card plug-in interface of the second adapter card are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other, and the rest are similar and so on, which will not be repeated here.
[0087] The test data generating device 50 is electrically connected to the TAP controller 40, and provides test data to the TAP controller 40. The TAP controller 40 is electrically connected to different serial chains to be tested, and converts different test data into corresponding test signals in JTAG format to provide to the corresponding serial chains to be tested.
[0088] The test card 30 can perform a JTAG standard pin test based on the JTAG format test signal provided by the corresponding plugged-in slot 11 to be tested and feed back a JTAG format test result signal, so that the TAP controller 40 receives the JTAG format test result signal from the serial link to be tested and converts it into response data. The test data generating device 50 receives the response data corresponding to the slot to be tested from the TAP controller 40, thereby completing the entire test process.
[0089] It is worth noting that in the actual test state, if the first slot to be tested and the third slot to be tested are electrically connected to each other to form a first series chain to be tested, and the second slot to be tested and the fourth slot to be tested are electrically connected to each other to form a second series chain to be tested, only the first adapter card can be correspondingly plugged into the first slot to be tested and the third adapter card can be correspondingly plugged into the third slot to be tested, and the first test card can be correspondingly plugged into the first adapter card and the third test card can be correspondingly plugged into the third adapter card.
[0090] The test data generating device 50 can only provide the test data corresponding to the first serial chain to be tested to the TAP controller 40. The TAP controller 40 converts the test data into a test signal in the JTAG format corresponding to the first serial chain to be tested, and then provides it to the first serial chain to be tested, so that the first test card and the third test card perform a JTAG standard pin test and feed back a test result signal in the JTAG format. This is only an example and is not intended to limit the scope of application of the present invention.
[0091] It is also possible to allow only the second adapter card to be correspondingly plugged into the second slot to be tested and the fourth adapter card to be correspondingly plugged into the fourth slot to be tested, and the second test card to be correspondingly plugged into the second adapter card and the fourth test card to be correspondingly plugged into the fourth adapter card. The test data generating device 50 can only provide the test data corresponding to the second serial chain to be tested to the TAP controller 40, and the TAP controller 40 will provide the test data as a test signal in the JTAG format corresponding to the second serial chain to be tested to the second serial chain to be tested, so that the second test card and the fourth test card perform a JTAG standard pin test and feed back a test result signal in the JTAG format. This is only an example and is not intended to limit the scope of application of the present invention.
[0092] The first adapter card may be correspondingly plugged into the first slot to be tested, the second adapter card may be correspondingly plugged into the second slot to be tested, the third adapter card may be correspondingly plugged into the third slot to be tested, and the fourth adapter card may be correspondingly plugged into the fourth slot to be tested, and the first test card may be correspondingly plugged into the first adapter card, the second test card may be correspondingly plugged into the second adapter card, the third test card may be correspondingly plugged into the third adapter card, and the fourth test card may be correspondingly plugged into the fourth adapter card. The test data generating device 50 may only provide the test data corresponding to the first serial chain to be tested or the second serial chain to be tested to the TAP controller 40, and the TAP controller 40 converts the test data into a test signal in the JTAG format corresponding to the first serial chain to be tested or the second serial chain to be tested, and then provides the test data to the first serial chain to be tested or the second serial chain to be tested, so that the first test card and the third test card or the second test card and the fourth test card perform a test on the JTAG standard pin and feed back a test result signal in the JTAG format. This is only an example and does not limit the scope of application of the present invention.
[0093] The following describes a JTAG standard pin test system according to a second embodiment of the present invention. Figure 4 As shown, Figure 4 FIG. 4 is a system block diagram of a second embodiment of the JTAG standard pin test of the present invention.
[0094] The second embodiment of the present invention discloses a JTAG standard pin test system, which comprises: a test board 10, a plurality of adapter cards 20, a plurality of test cards 30, a TAP controller 40 and a test data generating device 50, wherein the test board 10 has a plurality of test sockets 11.
[0095] Please refer to Figure 5 As shown, Figure 5The block diagram of the adapter card of the second embodiment of the JTAG standard pin test of the present invention is shown. Each adapter card 20 has an adapter card plug-in interface 21, an adapter card gold finger interface 22, a first JTAG input interface 23, a first JTAG output interface 24, a second JTAG input interface 25 and a second JTAG output interface 26. The TDI pins 61 of the adapter card plug-in interface 21, the adapter card gold finger interface 22, the first JTAG input interface 23, the first JTAG output interface 24, the second JTAG input interface 25 and the second JTAG output interface 26 are electrically connected to each other, the TDO pins 62 are electrically connected to each other, the TCK pins 63 are electrically connected to each other, the TMS pins 64 are electrically connected to each other, and the TRST pins 65 are electrically connected to each other.
[0096] The adapter card gold finger interface 22 of each adapter card 20 is correspondingly plugged into each slot to be tested 11, so that the correspondingly plugged adapter card gold finger interface 22 and the TDI pins 61 of the slot to be tested 11 are electrically connected to each other, the TDO pins 62 are electrically connected to each other, the TCK pins 63 are electrically connected to each other, the TMS pins 64 are electrically connected to each other, and the TRST pins 65 are electrically connected to each other; and the adapter cards 20 are electrically connected to each other through their respective first JTAG input interface 23 and first JTAG output interface 24 or second JTAG input interface 25 and second JTAG output interface 26 to form different adapter card serial chains.
[0097] The first adapter card is correspondingly plugged into the first slot to be tested, the second adapter card is correspondingly plugged into the second slot to be tested, the third adapter card is correspondingly plugged into the third slot to be tested, and the fourth adapter card is correspondingly plugged into the fourth slot to be tested, that is, the adapter card gold finger interface of the first adapter card and the TDI pins of the first slot to be tested are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other, the adapter card gold finger interface of the second adapter card and the TDI pins of the second slot to be tested are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other, and the rest are similar and so on, which will not be repeated here.
[0098] The first JTAG output interface of the first adapter card and the first JTAG input interface of the second adapter card are electrically connected to form a first adapter card serial chain, and the first JTAG output interface of the third adapter card and the first JTAG input interface of the fourth adapter card are electrically connected to form a second adapter card serial chain; the first JTAG output interface of the first adapter card and the first JTAG input interface of the second adapter card are electrically connected to form a first adapter card serial chain, and the second JTAG output interface of the third adapter card and the second JTAG input interface of the fourth adapter card are electrically connected to form a second adapter card serial chain; the first JTAG output interface of the first adapter card and the first JTAG input interface of the third adapter card are electrically connected to form a second adapter card serial chain. The first JTAG output interface of the first adapter card and the first JTAG input interface of the fourth adapter card form an electrical connection to form a first adapter card serial chain, the first JTAG output interface of the second adapter card and the first JTAG input interface of the fourth adapter card form an electrical connection to form a second adapter card serial chain; the first JTAG output interface of the first adapter card and the first JTAG input interface of the third adapter card form an electrical connection to form a first adapter card serial chain, and the second JTAG output interface of the second adapter card and the second JTAG input interface of the fourth adapter card form an electrical connection to form a second adapter card serial chain; the adapter card serial chain described above is only for illustration, and the remaining combinations to form the adapter card serial chain can be deduced accordingly, which will not be repeated here and the application scope of the present invention is not limited thereto.
[0099] Please refer to Figure 6 As shown, Figure 6 The block diagram of the test card of the second embodiment of the JTAG standard pin test of the present invention is shown. Each test card 30 has a boundary scan element 31, a JTAG input interface 32, a JTAG output interface 33 and a gold finger interface 34. The TDI pins 61 of the boundary scan element 31, the JTAG input interface 32, the JTAG output interface 33 and the gold finger interface 34 are electrically connected to each other, the TDO pins 62 are electrically connected to each other, the TCK pins 63 are electrically connected to each other, the TMS pins 64 are electrically connected to each other, and the TRST pins 65 are electrically connected to each other.
[0100] The gold finger interface 34 of each test card 30 is correspondingly plugged into the adapter card plug-in interface 21 of each adapter card 20, so that the TDI pins 61 of the correspondingly plugged gold finger interface 34 and the adapter card plug-in interface 21 are electrically connected to each other, the TDO pins 62 are electrically connected to each other, the TCK pins 63 are electrically connected to each other, the TMS pins 64 are electrically connected to each other, and the TRST pins 65 are electrically connected to each other; and the test card 30 performs a JTAG standard pin test based on the JTAG format test signal provided by the correspondingly plugged adapter card 20 and feeds back a JTAG format test result signal.
[0101] Based on the above example, the first test card is correspondingly plugged into the first adapter card, the second test card is correspondingly plugged into the second adapter card, the third test card is correspondingly plugged into the third adapter card, and the fourth test card is correspondingly plugged into the fourth adapter card, that is, the TDI pins of the gold finger interface of the first test card and the adapter card plug-in interface of the first adapter card are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other, the TDI pins of the gold finger interface of the second test card and the adapter card plug-in interface of the second adapter card are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other, and the rest are similar and so on, which will not be repeated here.
[0102] The test data generating device 50 is electrically connected to the TAP controller 40, and the test data generating device 50 provides test data to the TAP controller 40. The TAP controller 40 is electrically connected to different adapter card serial chains respectively, and converts different test data into corresponding JTAG format test signals to provide to the corresponding adapter card serial chains.
[0103] The test card 30 can perform a JTAG standard pin test based on the JTAG format test signal provided by the corresponding plug-in adapter card 20 and feed back a JTAG format test result signal, so that the TAP controller 40 receives the JTAG format test result signal from the adapter card serial link and converts it into response data. The test data generating device 50 receives the response data corresponding to the slot to be tested from the TAP controller 40, thereby completing the entire test process.
[0104] Please refer to Figure 7 As shown, Figure 7 The diagram shows a test architecture diagram of a second embodiment of the JTAG standard pin test of the present invention, wherein the first JTAG output interface of the first adapter card 201 is electrically connected to the first JTAG input interface of the third adapter card 203, the first JTAG output interface of the third adapter card 203 is electrically connected to the first JTAG input interface of the fifth adapter card 205, and the first JTAG output interface of the fifth adapter card 205 is electrically connected to the first JTAG input interface of the seventh adapter card 207 to form a first adapter card serial chain, the second JTAG output interface of the second adapter card 202 is electrically connected to the second JTAG input interface of the fourth adapter card 204, the second JTAG output interface of the fourth adapter card 204 is electrically connected to the second JTAG input interface of the sixth adapter card 204, and the second JTAG output interface of the sixth adapter card 206 is electrically connected to the second JTAG input interface of the eighth adapter card 208 to form a second adapter card serial chain.
[0105] The first test card 301 is electrically connected to the first riser card 201, the second test card 302 is electrically connected to the second riser card 202, the third test card 303 is electrically connected to the third riser card 203, the fourth test card 304 is electrically connected to the fourth riser card 204, the fifth test card 305 is electrically connected to the fifth riser card 205, the sixth test card 306 is electrically connected to the sixth riser card 206, the seventh test card 307 is electrically connected to the seventh riser card 207, and the eighth test card 308 is electrically connected to the eighth riser card 208.
[0106] In the actual detection process, only the first riser card 201 can be plugged into the first slot to be tested 111, the third riser card 203 can be plugged into the third slot to be tested 113, the fifth riser card 205 can be plugged into the fifth slot to be tested 115, and the seventh riser card 207 can be plugged into the seventh slot to be tested 117.
[0107] The test data generating device 50 provides the test data corresponding to the first adapter card serial chain to the TAP controller 40. The TAP controller 40 converts the test data into a test signal in the JTAG format corresponding to the first adapter card serial chain, and then provides it to the first adapter card serial chain, so that the first test card 201, the third test card 203, the fifth test card 205 and the seventh test card 207 perform the JTAG standard pin test and feed back the test result signal in the JTAG format.
[0108] In the actual detection process, only the second riser card 202 may be plugged into the second slot to be tested 112 , the fourth riser card 204 may be plugged into the fourth slot to be tested 114 , the sixth riser card 206 may be plugged into the sixth slot to be tested 116 , and the eighth riser card 208 may be plugged into the eighth slot to be tested 118 .
[0109] The test data generating device 50 provides the test data corresponding to the second riser card serial chain to the TAP controller 40. The TAP controller 40 converts the test data into a test signal in the JTAG format corresponding to the second riser card serial chain, and then provides it to the second riser card serial chain, so that the second test card 202, the fourth test card 204, the sixth test card 206 and the eighth test card 208 perform the JTAG standard pin test and feed back the test result signal in the JTAG format.
[0110] In the actual detection process, the first adapter card 201 can also be plugged into the first slot to be tested 111, the second adapter card 202 can be plugged into the second slot to be tested 112, the third adapter card 203 can be plugged into the third slot to be tested 113, the fourth adapter card 204 can be plugged into the fourth slot to be tested 114, the fifth adapter card 205 can be plugged into the fifth slot to be tested 115, the sixth adapter card 206 can be plugged into the sixth slot to be tested 116, the seventh adapter card 207 can be plugged into the seventh slot to be tested 117, and the eighth adapter card 208 can be plugged into the eighth slot to be tested 118.
[0111] The test data generating device 50 can only provide the test data corresponding to the first riser card serial chain or the second riser card serial chain to the TAP controller 40. The TAP controller 40 converts the test data into a test signal in the JTAG format corresponding to the first riser card serial chain or the second riser card serial chain, and then provides it to the first riser card serial chain or the second riser card serial chain, so that the first test card 201, the third test card 203, the fifth test card 205 and the seventh test card 207 or the second test card 202, the fourth test card 204, the sixth test card 206 and the eighth test card 208 perform the JTAG standard pin test and feed back the test result signal in the JTAG format.
[0112] The test data generating device 50 can simultaneously provide the test data corresponding to the first riser card serial chain and the second riser card serial chain to the TAP controller 40. The TAP controller 40 converts the test data into test signals in the JTAG format corresponding to the first riser card serial chain and the second riser card serial chain, and then provides them to the first riser card serial chain and the second riser card serial chain respectively, so that the first test card 201, the second test card 202, the third test card 203, the fourth test card 204, the fifth test card 205, the sixth test card 206, the seventh test card 207 and the eighth test card 208 simultaneously perform the JTAG standard pin test and feed back the test result signal in the JTAG format.
[0113] The above detection processes are only for illustration purposes, and the present invention is not limited thereto. A person skilled in the art can implement different combinations of adapter card cascade chains based on the above detection processes, which will not be described in detail herein.
[0114] In summary, the sockets to be tested are electrically connected to each other to form different serial chains to be tested, or the adapter cards are electrically connected to each other through their respective first JTAG input interface and first JTAG output interface or second JTAG input interface and second JTAG output interface to form different adapter card serial chains. The TAP controller provides corresponding JTAG format test signals to the serial chain to be tested or the adapter card serial chain so that the test card can perform JTAG standard pin testing.
[0115] This technical means can solve the problem in the prior art that the test machine can only provide multiple test slots on the same test board for JTAG standard pin testing, thereby achieving the technical effect of the test machine providing multiple test slots on different test boards for JTAG standard pin testing.
[0116] Although the embodiments disclosed in the present invention are as above, the contents described are not intended to directly limit the scope of patent protection of the present invention. Any person skilled in the art may make some modifications in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention. The scope of patent protection of the present invention shall still be subject to the scope defined in the attached claims.
Claims
1. A JTAG standard pin test system, comprising: A board under test, having a plurality of slots to be tested, and the slots to be tested are electrically connected to each other to form different serial chains to be tested; A plurality of adapter cards, each adapter card having an adapter card plugging interface, an adapter card gold finger interface, a first JTAG input interface, a first JTAG output interface, a second JTAG input interface, and a second JTAG output interface. The test data input pins of the adapter card plugging interface, the adapter card gold finger interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface, and the second JTAG output interface are electrically connected to each other, the test data output pins are electrically connected to each other, the test clock pins are electrically connected to each other, the test mode selection pins are electrically connected to each other, and the test initialization pins are electrically connected to each other; Wherein, The gold finger interface of each adapter card is plugged into the corresponding slot to be tested, so that the TDI pins of the corresponding plugged gold finger interface and the slot to be tested are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; A plurality of test cards, each test card having a boundary scan element, a JTAG input interface, a JTAG output interface, and a gold finger interface. The TDI pins of the boundary scan element, the JTAG input interface, the JTAG output interface, and the gold finger interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; Wherein, the gold finger interface of each test card is plugged into the corresponding adapter card plugging interface of each adapter card, so that the TDI pins of the corresponding plugged gold finger interface and the adapter card plugging interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; and The test card tests the JTAG standard pins with the JTAG format test signal provided by the corresponding slot to be tested and feeds back the JTAG format test result signal; A test access port controller, electrically connected to different serial chains to be tested respectively, converting different test data into the corresponding JTAG format test signal to be provided to the corresponding serial chain to be tested, receiving the JTAG format test result signal from the serial chain to be tested and converting it into response data; and A test data generation device, electrically connected to the test access port controller, providing the test data to the test access port controller, and receiving the response data corresponding to the slot to be tested from the test access port controller.
2. The JTAG standard pin test system as claimed in claim 1, wherein the test data generating device provides test data of a single serial chain to be tested to the test access port controller, and the test access port controller converts the test data into the corresponding test signals in JTAG format to provide to the single serial chain to be tested.
3. The JTAG standard pin test system as claimed in claim 1, wherein the adapter card and the test card are plugged into each other according to a single serial chain to be tested, the test data generating device provides test data of a single serial chain to be tested to the test access port controller, and the test access port controller converts the test data into the corresponding test signals in JTAG format to provide to the single serial chain to be tested.
4. A JTAG standard pin test system, comprising: A motherboard to be tested, having a plurality of slots to be tested; A plurality of adapter cards, each adapter card having an adapter card plugging interface, an adapter card gold finger interface, a first JTAG input interface, a first JTAG output interface, a second JTAG input interface, and a second JTAG output interface. The TDI pins of the adapter card plugging interface, the adapter card gold finger interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface, and the second JTAG output interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; Wherein, The adapter card gold finger interface of each adapter card is plugged into corresponding one of the slots to be tested, so that the TDI pins of the corresponding plugged adapter card gold finger interface and the slots to be tested are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; And The adapter cards are electrically connected to each other through their respective first JTAG input interfaces and first JTAG output interfaces or second JTAG input interfaces and second JTAG output interfaces to form different adapter card serial chains; A plurality of test cards, each test card having a boundary scan element, a JTAG input interface, a JTAG output interface, and a gold finger interface. The TDI pins of the boundary scan element, the JTAG input interface, the JTAG output interface, and the gold finger interface are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; Wherein, the gold finger interface of each test card is correspondingly plugged into the plug-in interface of each adapter card, so that the TDI pins of the correspondingly plugged gold finger interface and the plug-in interface of the adapter card are electrically connected to each other, the TDO pins are electrically connected to each other, the TCK pins are electrically connected to each other, the TMS pins are electrically connected to each other, and the TRST pins are electrically connected to each other; and The test card performs tests on the JTAG standard pins based on the JTAG format test signals provided by the correspondingly plugged adapter card and feeds back the test result signals in the JTAG format; A test access port controller is electrically connected in series with different adapter card chains respectively, converts different test data into the corresponding JTAG format test signals to be provided to the corresponding adapter card chain, receives the JTAG format test result signals from the adapter card chain and converts them into response data; and A test data generation device is electrically connected to the test access port controller, provides the test data to the test access port controller, and receives the response data corresponding to the slot to be tested from the test access port controller.
5. The JTAG standard pin test system according to claim 4, wherein the test data generation device provides the test data of a single adapter card chain to the test access port controller, and the test access port controller converts the test data into the corresponding JTAG format test signals to be provided to the single adapter card chain.
6. The JTAG standard pin test system according to claim 4, wherein the adapter card and the test card are plugged into each other according to a single adapter card chain, the test data generation device provides the test data of a single adapter card chain to the test access port controller, and the test access port controller converts the test data into the corresponding JTAG format test signals to be provided to the single adapter card chain.
7. The JTAG standard pin test system according to claim 4, wherein the adapter card only uses the first JTAG input interface and the first JTAG output interface to electrically connect to each other to form different adapter card chains.
8. The JTAG standard pin test system according to claim 4, wherein the adapter card only uses the second JTAG input interface and the second JTAG output interface to electrically connect to each other to form different adapter card chains.
9. The JTAG standard pin test system according to claim 4, wherein the adapter card respectively uses the second JTAG input interface and the second JTAG output interface to electrically connect to the second JTAG input interface and the second JTAG output interface to form different adapter card chains.