Method and equipment for processing misalignment abnormity of fetch addresses

Abstract

The invention discloses an instruction fetch address misalignment exception processing method and device, and the method comprises the steps: dividing an unconditional jump instruction into a first operation for calculating a link address and writing a result into a destination register and a second operation for calculating a branch target address and completing jump, and executing the first operation and the second operation in an integer calculation part and a branch part respectively; the conditional branch instruction only comprises that a first operation for calculating a branch target address and judging whether to jump is executed on the branch component, the branch component only realizes one calculation module and does not set a result write bus, a completion field and an unaligned field are set in the ROB, and the two fields are updated when the operation is dispatched and executed. And after the operation is executed, the first operation checks the misalignment field of the corresponding item in the ROB to determine whether to report the misalignment abnormity of the fetch address. The invention aims to provide the processing method for the misalignment exception of the fetch address, which is small in area overhead, for the out-of-order superscale processor of the RISC-V architecture.

Description

Technical Field

[0001] The present invention relates to the out-of-order superscalar processor design technology in the field of processor design, and specifically relates to a method and device for processing the instruction fetch address misalignment exception. Background Art

[0002] In the open instruction set architecture RISC-V, the instruction length has two types: 32 bits and 16 bits. If the processor does not implement the compressed instruction extension (i.e., C extension), then the instruction length is fixed at 32 bits, occupying 4 bytes, and the instruction fetch address must be 4-byte aligned. Otherwise, an instruction fetch address misalignment exception will occur. The RISC-V architecture stipulates that the instruction fetch address misalignment exception is reported at the instruction that causes the instruction fetch address misalignment, and this instruction that causes the instruction fetch address misalignment cannot modify the architectural state of the processor.

[0003] The control transfer instructions in the RISC-V instruction set are divided into two categories: unconditional jumps and conditional branches, both of which may cause the instruction fetch address to be misaligned. The unconditional jump instruction has the meaning of jump and link, which will save the link address (i.e., the address of the next instruction after the unconditional jump instruction) in the destination register, and then modify the instruction fetch address to the target address. Therefore, the unconditional jump instruction needs to calculate both the link address and the target address; the conditional branch instruction will compare whether the values of two source registers meet a certain condition, such as being equal. If the condition is met, the instruction fetch address is modified to the target address, otherwise, instructions are fetched sequentially. The conditional branch instruction only needs to calculate the target address and has no destination register.

[0004] When designing a processor with the RISC-V architecture, the existing technology usually implements a branch component for executing control transfer instructions. When executing an unconditional jump instruction, this instruction is sent as an operation to the branch component, and the branch component simultaneously completes the two functions of link address update and branch jump. If the target address is misaligned, this instruction will neither update the destination register with the link address nor perform a jump. This method requires the branch component to implement two calculation modules, one for calculating the link address and one for calculating the branch target address, and also needs to set a result write bus to write back the link address, resulting in an increase in the write port of the integer register file and an additional bypass source in the integer data bypass network, both of which will increase the area overhead of the processor. And only the unconditional jump instruction among the control transfer instructions executed by the branch component has the link function. The conditional branch instruction does not need to calculate the link address and write it into the destination register, and the additional calculation module and the set result write bus in the branch component will not be used by the conditional branch instruction. The existing branch component design is not conducive to the area optimization of the processor. Summary of the Invention

[0005] Technical problems to be solved by the present invention: Aiming at the above problems of the prior art, a method and device for processing the instruction fetch address misalignment exception are provided. The present invention aims to provide a method for processing the instruction fetch address misalignment exception with small area overhead for out-of-order superscalar processors based on the RISC-V architecture.

[0006] To solve the above technical problems, the technical solution adopted by the present invention is as follows: A method for processing the instruction fetch address misalignment exception, comprising the following steps: 1) Fetch the control transfer instruction; 2) If the control transfer instruction is an unconditional jump instruction, split the unconditional jump instruction into a first operation of calculating the linked address and writing the result into the destination register and a second operation of calculating the branch target address and completing the jump; if the control transfer instruction is a conditional branch instruction, regard the conditional branch instruction as the first operation; 3) Decode and rename the operations of the control transfer instruction; 4) Dispatch the operations of the control transfer instruction to the functional units and allocate entries in the reorder buffer: If the control transfer instruction is an unconditional jump instruction, dispatch the first operation to the integer calculation unit and the second operation to the branch unit, and allocate two consecutive entries in the reorder buffer for the first operation and the second operation, each entry is set with an unaligned field and a completion field, where the unaligned field is used to record whether the instruction fetch address is misaligned, and the completion field is used to record whether the operation is completed; if the control transfer instruction is a conditional branch instruction, dispatch the conditional branch instruction to the branch unit, and allocate one entry in the reorder buffer for the first operation, and this entry is also set with an unaligned field for recording whether the instruction fetch address is misaligned and a completion field for recording whether the operation is completed; update the entry allocated in the reorder buffer when the operation of the control transfer instruction is executed; finally, after the operation is executed, the first operation checks the value of the unaligned field in the reorder buffer to determine whether to report the instruction fetch address misalignment exception.

[0007] Optionally, the value of the unaligned field is 1 or 0, 1 indicates that the instruction fetch address is misaligned, 0 indicates that the instruction fetch address is aligned, and the initial value when allocated is 0; the value of the completion field is 1 or 0, 1 indicates that the operation has been executed, 0 indicates that the operation has not been executed, and the initial value when allocated is 0.

[0008] Optionally, updating the item allocated in the reorder buffer when the operation of the control transfer instruction is executed includes: when the control transfer instruction is an unconditional jump instruction, calculating the link address during the execution of the first operation of the unconditional jump instruction executed by the integer calculation component, and writing the result into the intermediate result register. The architectural state is not updated immediately after the first operation is completed. After the first operation is completed, the completion field in the item allocated for it in the reorder buffer is set to 1, indicating that the operation has been completed, and the misalignment field remains unchanged.

[0009] Optionally, updating the item allocated in the reorder buffer when the operation of the control transfer instruction is executed includes: when the control transfer instruction is an unconditional jump instruction, calculating the target address during the execution of the second operation of the unconditional jump instruction executed by the branch component, determining whether the target address is 4-byte aligned, and updating the information of the corresponding item and the previous item in the reorder buffer according to whether the target address is 4-byte aligned: setting the completion field of the corresponding item in the reorder buffer for the second operation to 1, indicating that the operation has been completed, and updating the misalignment field of the previous item in the reorder buffer for the second operation: if the target address is not 4-byte aligned, then setting the misalignment field to 1, otherwise setting it to 0, and keeping the misalignment field of the corresponding item in the reorder buffer for the second operation unchanged.

[0010] Optionally, updating the item allocated in the reorder buffer when the operation of the control transfer instruction is executed includes: when the control transfer instruction is a conditional branch instruction, calculating the target address during the execution of the first operation of the conditional branch instruction executed by the branch component, and combining the jump direction to determine whether the subsequent fetch address is 4-byte aligned. If it is not 4-byte aligned, then setting the misalignment field of the corresponding item in the reorder buffer to 1, otherwise setting it to 0. At the same time, the completion field of the corresponding item in the reorder buffer for this operation is set to 1, indicating that the operation has been completed.

[0011] Optionally, the first operation checks the value of the misalignment field in the reorder buffer to determine whether to report a fetch address misalignment exception, including: the first operation checks the value of the misalignment field of the corresponding item in the reorder buffer to determine whether to report a fetch address misalignment exception. If the value of the misalignment field is 1, indicating that the control transfer instruction has caused a fetch address misalignment, then a fetch address misalignment exception is reported at this operation, and all subsequent operations starting from this operation will not be committed, thus ensuring that the control transfer instruction that causes the fetch address misalignment exception will not modify the architectural state; if the value of the misalignment field is 0, then the operations corresponding to the control transfer instruction can be committed normally. If the control transfer instruction is a conditional branch instruction, then sequential fetching or jumping to the target address is performed. If the control transfer instruction is an unconditional jump instruction, then the value of the destination register is updated and the jump to the target address is performed.

[0012] Optionally, the control transfer instruction refers to the control transfer instruction in the RISC-V instruction set.

[0013] In addition, the present invention further provides an electronic device, including a processor and a memory connected to each other, and the processor is programmed or configured to execute the method for handling the instruction fetch address misalignment exception.

[0014] In addition, the present invention further provides a computer-readable storage medium, in which a computer program or instruction is stored, and the computer program or instruction is programmed or configured to execute the method for handling the instruction fetch address misalignment exception through a processor.

[0015] In addition, the present invention further provides a computer program product, including a computer program or instruction, and the computer program or instruction is programmed or configured to execute the method for handling the instruction fetch address misalignment exception through a processor.

[0016] Compared with the prior art, the present invention can mainly achieve the following beneficial effects: The present invention splits an unconditional jump instruction into a first operation of calculating a link address and writing the result into a destination register and a second operation of calculating a branch target address and completing the jump. The first operation is executed in an integer calculation component, and the second operation is executed in a branch component. The conditional branch instruction only includes a first operation of calculating a branch target address and determining whether to jump, and this operation is executed in the branch component. A completion field for recording whether the operation is completed and an unaligned field for whether the instruction fetch address is misaligned are set in the reorder buffer, and these two fields are updated when the operation is dispatched and executed. After the operation is completed, the first operation checks the unaligned field of its corresponding item in the reorder buffer to determine whether to report an instruction fetch address misalignment exception. The operation of calculating the link address of the unconditional jump instruction and writing the result into the destination register is completed by means of an integer calculation component, without the need to additionally increase calculation and write-back logic. The branch component only needs to implement a calculation module and does not need to set a result write bus, so the area overhead is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the basic flow of the method according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0019] As Figure 1 shown, the method for handling the instruction fetch address misalignment exception in this embodiment includes the following steps: 1) Fetch the control transfer instruction; 2) If the control transfer instruction is an unconditional jump instruction, split the unconditional jump instruction into a first operation of calculating the link address and writing the result to the destination register and a second operation of calculating the branch target address and completing the jump; if the control transfer instruction is a conditional branch instruction, regard the conditional branch instruction as the first operation; 3) Decode and rename the operations of the control transfer instruction; 4) Dispatch the operations of the control transfer instruction to the functional units and allocate entries in the ReOrder Buffer (ROB, a structure used to implement instruction sequential submission in an out-of-order superscalar processor): If the control transfer instruction is an unconditional jump instruction, dispatch the first operation to the integer calculation unit and the second operation to the branch unit, and allocate two consecutive entries in the ReOrder Buffer for the first operation and the second operation, each entry setting an unaligned field and a completion field, where the unaligned field is used to record whether the fetch address is unaligned, and the completion field is used to record whether the operation is completed; if the control transfer instruction is a conditional branch instruction, dispatch the conditional branch instruction to the branch unit, and allocate one entry in the ReOrder Buffer for the first operation, and this entry also sets an unaligned field for recording whether the fetch address is unaligned and a completion field for recording whether the operation is completed; update the entry allocated for it in the ReOrder Buffer when the operation of the control transfer instruction is executed; finally, after the operation is executed, the first operation checks the value of the unaligned field in its allocated entry in the ReOrder Buffer to determine whether to report a fetch address unaligned exception.

[0020] To handle the fetch address unaligned exception, two types of fields are set in the ReOrder Buffer in this embodiment: one field indicates whether the operation has been executed, named the completion field, and the other field indicates whether the fetch address is unaligned when the operation is executed, named the unaligned field. In this embodiment, the value of the unaligned field is 1 or 0, 1 means the fetch address is unaligned, 0 means the fetch address is aligned, and the initial value when allocated is 0; the value of the completion field is 1 or 0, 1 means the operation has been executed, 0 means the operation has not been executed, and the initial value when allocated is 0. When the operation of the control transfer instruction is dispatched into the ReOrder Buffer, the completion field and the unaligned field of the corresponding entry are both set to 0. There are also other fields set in the ReOrder Buffer, which are not described because they are not relevant to the present invention.

[0021] The execution unit executes the operations of the control transfer instruction and updates the completion field and the unaligned field of the corresponding entry in the ReOrder Buffer according to the execution situation. Updating the entry allocated for it in the ReOrder Buffer when the operation of the control transfer instruction is executed includes: When the control transfer instruction is an unconditional jump instruction, the link address is calculated during the execution of the first operation of the unconditional jump instruction executed by the integer calculation component, and the result is written into the intermediate result register. Since it is not yet determined whether a fetch address misalignment exception will occur for the unconditional jump instruction corresponding to this operation at this time, the architectural state is not updated immediately after the execution of the first operation. After the execution of the first operation is completed, the completion field in the item allocated for it in the reorder buffer is set to 1, indicating that the operation has been executed, and the misalignment field remains unchanged.

[0022] When the control transfer instruction is an unconditional jump instruction, the target address is calculated during the execution of the second operation of the unconditional jump instruction executed by the branch component, and it is judged whether the target address is 4-byte aligned. Since an unconditional jump instruction will definitely cause a jump, it is directly judged whether the target address is 4-byte aligned; then, according to the result of whether the target address is 4-byte aligned, the information of the corresponding item and the previous item of this second operation in the reorder buffer is updated: the completion field of the corresponding item of this second operation in the reorder buffer is set to 1, indicating that the operation has been executed, and the misalignment field of the previous item of this second operation in the reorder buffer is updated: if the target address is not 4-byte aligned, then the misalignment field is set to 1, otherwise it is set to 0, and the misalignment field of the corresponding item of this second operation in the reorder buffer remains unchanged. Even if the target address is not 4-byte aligned, it is not necessary to update the misalignment field of the corresponding item of this second operation in the reorder buffer. In fact, this field is not used.

[0023] When the control transfer instruction is a conditional branch instruction, the target address is calculated during the execution of the first operation of the conditional branch instruction executed by the branch component, and it is judged whether the subsequent fetch address is 4-byte aligned in combination with the jump direction. If it is not 4-byte aligned, the misalignment field of the corresponding item in the reorder buffer is set to 1, otherwise it is set to 0. At the same time, the completion field of the corresponding item of this operation in the reorder buffer is also set to 1, indicating that the operation has been executed.

[0024] After all the operations corresponding to the control transfer instruction are completed, the first operation checks the value of the misalignment field of the corresponding entry in the reorder buffer to determine whether to report a fetch address misalignment exception. Specifically, in this embodiment, the first operation checks the value of its misalignment field in the reorder buffer to determine whether to report a fetch address misalignment exception, including: the first operation checks the value of the misalignment field of the corresponding entry in the reorder buffer to determine whether to report a fetch address misalignment exception. If the value of the misalignment field is 1, it indicates that the control transfer instruction has caused a fetch address misalignment. Then, a fetch address misalignment exception is reported at this operation, and all subsequent operations starting from this operation will not be committed, thus ensuring that the control transfer instruction that causes a fetch address misalignment exception will not modify the architecture state. If the value of the misalignment field is 0, then all the operations corresponding to the control transfer instruction can be normally committed. If the control transfer instruction is a conditional branch instruction, sequential fetching or jumping to the target address is performed. If the control transfer instruction is an unconditional jump instruction, the value of the destination register is updated and the jump to the target address is performed.

[0025] The method of this embodiment can be applied to various out-of-order superscalar processors. As an alternative embodiment, in this embodiment, the target is a RISC-V processor, and the control transfer instruction refers to the control transfer instruction in the RISC-V instruction set.

[0026] In summary, the method for handling the fetch address misalignment exception in this embodiment splits the unconditional jump instruction into a first operation of calculating the linked address and writing the result to the destination register and a second operation of calculating the branch target address and completing the jump. The first operation is executed in the integer calculation component without adding additional calculation and write-back logic. The second operation is executed in the branch component. The conditional branch instruction only includes a first operation of calculating the branch target address and determining whether to jump, and this operation is executed in the branch component. The branch component only implements one calculation module and does not set a result write bus. In the reorder buffer, a completion field for recording whether the operation is completed and a misalignment field for recording whether the fetch address is misaligned are set, and these two fields are updated when the operation is dispatched and executed. After the operation is completed, the first operation checks the misalignment field of its corresponding entry in the reorder buffer to determine whether to report a fetch address misalignment exception. Since the operation of calculating the linked address and writing the result to the destination register of the unconditional jump instruction is completed by the integer calculation component without the need to add additional calculation and write-back logic, and the branch component only needs to implement one calculation module and does not need to set a result write bus, the method of this embodiment can reduce the area overhead of the processor.

[0027] In addition, this embodiment also provides an electronic device, including a processor and a memory connected to each other, and the processor is programmed or configured to execute the method for handling the fetch address misalignment exception.

[0028] In addition, this embodiment also provides a computer-readable storage medium storing a computer program or instruction, which is programmed or configured to execute the method for processing the instruction fetch address misalignment exception through a processor.

[0029] In addition, this embodiment also provides a computer program product including a computer program or instruction, which is programmed or configured to execute the method for processing the instruction fetch address misalignment exception through a processor.

[0030] Those skilled in the art should understand that the technical solution provided by the present invention can be in the form of a method, a system, or a computer program product. Therefore, the present invention can be implemented in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can be implemented in the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes. The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, and the combination of processes and / or blocks in the flowcharts and / or block diagrams, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks. These computer program instructions can also be stored in a computer-readable memory capable of guiding the computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device realizes the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks. These computer program instructions can also be loaded onto the computer or other programmable data processing devices, so that a series of operation steps are executed on the computer or other programmable devices to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable devices provide steps for realizing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0031] The above are only the preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should also be regarded as within the protection scope of the present invention.

Claims

1. A method for processing an instruction fetch address misalignment exception, characterized in that: The steps include: 1) Take out the control transfer instruction; 2) If the control transfer instruction is an unconditional jump instruction, the unconditional jump instruction is split into a first operation of calculating the link address and writing the result into the destination register and a second operation of calculating the branch target address and completing the jump; if the control transfer instruction is a conditional branch instruction, the conditional branch instruction is regarded as the first operation; 3) Decode and rename the operations of control transfer instructions; 4) Dispatching the operation of the control transfer instruction to the functional unit and allocating items in the reorder buffer: If the control transfer instruction is an unconditional jump instruction, the first operation is dispatched to the integer calculation unit, the second operation is dispatched to the branch unit, and two consecutive items are allocated to the first operation and the second operation in the reorder buffer, each item is set with an unaligned field and a completed field, wherein the unaligned field is used to record whether the instruction fetch address is unaligned, and the completed field is used to record whether the operation is completed; if the control transfer instruction is a conditional branch instruction, the conditional branch instruction is dispatched to the branch unit, and an item is allocated to the first operation in the reorder buffer, and the item also sets an unaligned field for recording whether the instruction fetch address is unaligned and a completed field for recording whether the operation is completed; when the operation of the control transfer instruction is executed, its allocated item in the reorder buffer is updated; finally, after the operation is executed, the first operation checks the value of its unaligned field in the reorder buffer to decide whether to report an instruction fetch address misalignment exception.

2. The method for processing instruction fetch address misalignment exception according to claim 1, characterized in that: The value of the unaligned field is 1 or 0, 1 indicates that the instruction fetch address is not aligned, 0 indicates that the instruction fetch address is aligned, and the initial value when it is assigned is 0; the value of the completion field is 1 or 0, 1 indicates that the operation has been completed, 0 indicates that the operation has not been completed, and the initial value when it is assigned is 0.

3. The method for processing instruction fetch address misalignment exception according to claim 1, characterized in that: The updating of the item allocated in the reorder buffer when the operation of the control transfer instruction is executed includes: when the control transfer instruction is an unconditional jump instruction, when the first operation of the unconditional jump instruction executed by the integer calculation unit is executed, the link address is calculated, and the result is written into the intermediate result register, and the architecture state is not updated immediately after the first operation is executed. After the first operation is executed, the completion field in the item allocated in the reorder buffer is set to 1, indicating that the operation has been executed, and the misalignment field remains unchanged.

4. The method for processing instruction fetch address misalignment exception according to claim 1, characterized in that: The updating of the items allocated in the reorder buffer when the operation of the control transfer instruction is executed includes: when the control transfer instruction is an unconditional jump instruction, calculating the target address when the second operation of the unconditional jump instruction executed by the branch component is executed, judging whether the target address is 4-byte aligned, and updating the information of the corresponding item of the second operation in the reorder buffer and its previous item according to the result of whether the target address is 4-byte aligned: setting the completion field of the corresponding item of the second operation in the reorder buffer to 1, indicating that the operation is completed, and updating the misalignment field of the previous item of the second operation in the reorder buffer: if the target address is not 4-byte aligned, then setting the misalignment field to 1, otherwise setting it to 0, and keeping the misalignment field of the corresponding item of the second operation in the reorder buffer unchanged.

5. The method for processing instruction fetch address misalignment exception according to claim 1, characterized in that: The updating of the items allocated in the reorder buffer when the operation of the control transfer instruction is executed includes: when the control transfer instruction is a conditional branch instruction, calculating the target address when the first operation of the conditional branch instruction executed by the branch component is executed, and judging whether the subsequent instruction fetch address is 4-byte aligned in combination with the jump direction, if it is not 4-byte aligned, setting the unaligned field of the corresponding item in the reorder buffer to 1, otherwise setting it to 0, and at the same time setting the completion field of the corresponding item in the reorder buffer to 1, indicating that the operation has been completed.

6. The method for processing instruction fetch address misalignment exception according to claim 1, characterized in that: The first operation checks the value of the misaligned field in the reorder buffer to determine whether to report an instruction fetch address misalignment exception, including: the first operation checks the value of the misaligned field of the corresponding item in the reorder buffer to determine whether to report an instruction fetch address misalignment exception. If the value of the misaligned field is 1, it means that the control transfer instruction causes the instruction fetch address misalignment, then the instruction fetch address misalignment exception is reported at the operation, and all subsequent operations starting from the operation will not be submitted, thereby ensuring that the control transfer instruction that causes the instruction fetch address misalignment exception will not modify the architecture state; if the value of the misaligned field is 0, then the operations corresponding to the control transfer instruction can be submitted normally, if the control transfer instruction is a conditional branch instruction, the instructions are sequentially fetched or jumped to the target address, if the control transfer instruction is an unconditional jump instruction, the value of the destination register is updated and the jump is to the target address.

7. The method for processing instruction fetch address misalignment exception according to claim 1, characterized in that: The control transfer instruction refers to the control transfer instruction in the RISC-V instruction set.

8. An electronic device comprising a processor and a memory connected to each other, characterized in that: The processor is programmed or configured to execute the method for processing instruction fetch address misalignment exception described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the method for processing instruction fetch address misalignment exception described in any one of claims 1 to 7 through a processor.

10. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the method for processing instruction fetch address misalignment exception described in any one of claims 1 to 7 through a processor.

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