Charge pump switch tube dynamic substrate bias current leakage prevention method and device

Abstract

The invention discloses a charge pump switching tube dynamic substrate bias current leakage prevention method and device, and relates to the technical field of charge pumps, the charge pump switching tube dynamic substrate bias current leakage prevention device comprises an MOS switching tube SW1, an MOS switching tube SW2, an MOS switching tube SW3, an MOS switching tube SW4, an energy storage capacitor Cs1 and a two-time positive voltage charge pump circuit of a non-overlapping clock signal CLKP / CLKN, and the source end or the drain end of the charge pump circuit is periodically switched on or off according to the clock signal. By providing a dynamic bias technology of the substrate of the mos switch, the parasitic pnp / npn triode in the mos switch is ensured not to be positively conducted no matter whether the charge pump is provided with a heavy load or a light load, so that the internal node of the charge pump is prevented from leaking large current to the psub / dnw, the driving capability of the charge pump is enhanced, and the reliability of the charge pump is improved. Moreover, the current consumption of the charge pump is reduced, and the efficiency of the charge pump is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of charge pumps, and particularly relates to a method and device for preventing current leakage in a dynamic substrate bias of a charge pump switching transistor. Background Art

[0002] In an actual circuit, a charge pump uses MOS transistors as switches. When the charge pump drives a heavy load, due to the limited over-current capacity of the MOS transistors acting as charge pump switches, the drain-bulk or source-bulk of the MOS transistors may conduct forward, causing the parasitic triodes in the MOS transistors to conduct. As a result, a large current flows from the emitter to the collector of the parasitic triode, which also means that a large leakage current occurs from the source / drain terminal of the MOS switch of the charge pump to the DNW or PSUB. Eventually, the driving ability of the charge pump decreases, and the current consumption of the charge pump itself increases, thereby reducing the efficiency of the charge pump. The present invention proposes a dynamic substrate biasing method for MOS switches in a charge pump, which can avoid the situation where the drain-bulk or source-bulk of the MOS switch of the charge pump conducts forward when the charge pump drives a heavy load and causes a large current to flow through the MOS switch, thereby avoiding the large current flowing from the internal nodes of the charge pump to the DNW or PSUB caused by the conduction of the parasitic triode of the MOS transistor. Eventually, the driving ability of the charge pump is improved, the current consumption of the charge pump itself is reduced, and the efficiency of the charge pump is increased. Summary of the Invention

[0003] To solve the above technical problems, the present invention is realized through the following technical solutions:

[0004] The present invention provides a method for preventing current leakage in a dynamic substrate bias of a charge pump switching transistor, including a 2X positive voltage charge pump circuit with MOS switches SW1, SW2, SW3, SW4, a storage capacitor Cs1, and non-overlapping clock signals CLKP / CLKN, whose source or drain terminals are periodically turned on or off according to the clock signals.

[0005] According to the type of switching transistor, PMOS, NMOS, or hybrid type, the substrate terminals of each switching transistor are dynamically connected to specific potential nodes Vin, Vout, VA, VB, or GND to ensure that the substrate and the source / drain terminals are reverse-biased in the initial state;

[0006] During the charging phase, CLKP is high and CLKN is low. Switches SW1 and SW4 are turned on, and switches SW2 and SW3 are turned off. The substrate potential of SW1 and SW4 is dynamically adjusted to ensure that the substrate potential is always higher than or equal to the source / drain potential;

[0007] During the pump charge phase, CLKP is low and CLKN is high. Switches SW2 and SW3 are turned on, and switches SW1 and SW4 are turned off. The substrate potential of SW2 and SW3 is dynamically adjusted to ensure that the substrate potential is always higher than or equal to the source / drain potential.

[0008] The substrate connection is switched according to the clock signal, the node voltage is monitored in real time, and the substrate is dynamically connected to the highest potential node corresponding to the current working phase to ensure that the reverse bias condition is always satisfied between the source / drain and the substrate.

[0009] An independent dynamic substrate bias circuit is configured for each of the PMOS switch transistors. This circuit consists of a voltage monitoring module and a potential switching module:

[0010] The voltage monitoring module is used to detect the voltage values of the source end, drain end, and intermediate node of the switch transistor in real time.

[0011] The potential switching module is used to dynamically select the substrate to be connected to the input voltage Vin, the output voltage Vout, or the intermediate node potential VA / VB according to the monitoring results and the current working phase, determined by the CLKP / CLKN state.

[0012] The working phase of the charge pump adjusts the substrate potential:

[0013] During the charging phase, CLKP is high and CLKN is low:

[0014] SW1 and SW4 are turned on, and SW2 and SW3 are turned off;

[0015] The substrate of SW1 is connected to Vin, the source end is connected to VA. If the load increases and causes VA < Vin, the substrate potential Vin is still higher than the source end voltage, maintaining the reverse bias;

[0016] The substrate of SW4 is connected to the VB intermediate node, the source end is grounded. If the load increases and causes VB > 0, the dynamic bias circuit transfers the VB potential to the SW4 substrate to satisfy VB ≥ 0;

[0017] The substrates of the turned-off SW2 and SW3 are respectively connected to Vin and Vout, and the drain end voltages VB and VA are always lower than the substrate potential;

[0018] During the pump power stage, CLKP is low and CLKN is high:

[0019] SW2 and SW3 are turned on, and SW1 and SW4 are turned off;

[0020] The substrate of SW2 is connected to Vin, the drain end is connected to VB. If the load increases and causes VB < Vin, the substrate potential Vin is still higher than the drain end voltage, maintaining the reverse bias;

[0021] The substrate of SW3 is connected to VA, and the source terminal is connected to Vout. If the load increases and causes VA > Vout, the dynamic bias circuit will transfer the VA potential to the substrate of SW3 to make VA ≥ Vout;

[0022] The substrates of the turned-off SW1 and SW4 are respectively connected to VA and V.

[0023] For NMOS switches, hybrid switches, and multi - voltage charge pumps with different charge - pump topologies, the dynamic substrate bias circuit can be adjusted:

[0024] The NMOS switch tube is used to connect the substrate to the lowest potential node monitored dynamically, so that the source / drain voltage ≤ the substrate potential;

[0025] For the hybrid switch, independent dynamic bias circuits are designed for PMOS and NMOS respectively;

[0026] Multi - voltage charge pump: According to the number of intermediate nodes, a potential switching module is added to ensure that the substrate potential of all switch tubes is adapted in real time.

[0027] Extended to other charge - pump architectures, including NMOS switch tubes, hybrid switch tubes, and multi - voltage charge pumps, the substrate connections are dynamically adjusted according to the rules respectively to ensure that the base - emitter of the parasitic triode of all switch tubes is reverse - biased. Through simulation and actual tests, it is verified that under dynamic substrate bias, the base - emitter of the parasitic PNP triode of the PMOS tube is always in the reverse - biased state.

[0028] Verify the working state of the charge pump under light load and heavy load through simulation and actual measurement, and optimize the dynamic bias logic to cover extreme load conditions.

[0029] The power - electronic device of the present invention for a method of preventing current leakage by dynamic substrate bias of charge - pump switch tubes includes: one or more processors, a memory, and one or more programs, where the one or more programs are stored in the memory and are configured to be executed by the one or more processors. The programs include instructions for executing the method of preventing current leakage by dynamic substrate bias as described in any one of claims 1 to 7. The power - electronic device dynamically adjusts the substrate connection of the charge - pump switch tube to a specific potential node, monitors the voltage values of the source terminal, drain terminal, and intermediate nodes in real time, and switches the substrate connection according to the clock signals CLKP / CLKN to ensure that the reverse - bias condition is always satisfied between the source / drain and the substrate, thereby avoiding current leakage caused by the conduction of parasitic PNP / NPN triodes and improving the driving ability and efficiency of the charge pump.

[0030] The present invention has the following beneficial effects:

[0031] 1. By proposing the dynamic biasing technology for the substrate of the MOS switch, the present invention ensures that whether the charge pump is under heavy load or light load, the parasitic PNP / NPN transistors in the MOS switch will not conduct forward, thus avoiding large current leakage from the internal nodes of the charge pump to the Psub / DNW. This not only enhances the driving ability of the charge pump, but also reduces the current consumption of the charge pump itself and improves the efficiency of the charge pump.

[0032] 2. The solution of the present invention is simple, easy to implement, and has a small power consumption / area cost.

[0033] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0035] Figure 1 Schematic diagram of the technology for preventing switch substrate current leakage of a charge pump with PMOS as the switching transistor;

[0036] Figure 2 Schematic diagram of the working state of the switching transistor of a charge pump with PMOS as the switching transistor during the charge pumping stage;

[0037] Figure 3 Schematic diagram of the working state of the switching transistor of a charge pump with PMOS as the switching transistor during the charge transfer stage;

[0038] Figure 4 For the switching transistor nmos Schematic diagram of the technology for preventing switch substrate current leakage of a 2x positive voltage charge pump with PMOS as the switching transistor;

[0039] Figure 5 Schematic diagram of the technology for preventing switch substrate current leakage of a 2x positive voltage charge pump with NMOS / PMOS as the switching transistor;

[0040] Figure 6 Schematic diagram of the technology for preventing switch substrate current leakage of a 1x negative voltage charge pump with PMOS as the switching transistor;

[0041] Figure 7 Schematic diagram of the technology for preventing switch substrate current leakage of a 1x negative voltage charge pump with NMOS / PMOS as the switching transistor;

[0042] Figure 8Schematic diagram of the technology for preventing switch substrate current leakage in a 3x positive voltage charge pump for nmos / pmos switch transistors;

[0043] Figure 9 Schematic diagram of the technology for preventing switch substrate current leakage in a 2x negative voltage charge pump for nmos / pmos switch transistors. Specific implementation manners

[0044] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0045] Please refer to Figures 1-9 As shown, the present invention is a method for preventing current leakage in a dynamic substrate bias of a charge pump switch transistor, including a 2x positive voltage charge pump circuit of MOS switch transistors SW1, SW2, SW3, SW4, energy storage capacitor Cs1, and non-overlapping clock signals CLKP / CLKN, whose source or drain is periodically turned on or off according to the clock signal.

[0046] According to the switch transistor type PMOS, NMOS or hybrid type, dynamically connect the substrate terminals of each switch transistor to specific potential nodes Vin, Vout, VA, VB or GND to ensure that the substrate and the source / drain terminals are reverse-biased in the initial state;

[0047] In the charging stage, CLKP is high and CLKN is low, turn on switches SW1 and SW4, turn off switches SW2 and SW3, and dynamically adjust the substrate potential of SW1 and SW4 to ensure that the substrate potential is always higher than or equal to the source / drain potential;

[0048] In the charge pumping stage, CLKP is low and CLKN is high, turn on switches SW2 and SW3, turn off switches SW1 and SW4, and dynamically adjust the substrate potential of SW2 and SW3 to ensure that the substrate potential is always higher than or equal to the source / drain potential;

[0049] Switch the substrate connection according to the clock signal, monitor the node voltage in real time, and dynamically adjust the substrate connection to the highest potential node corresponding to the current working stage to ensure that the reverse bias condition is always satisfied between the source / drain and the substrate.

[0050] Configure an independent dynamic substrate bias circuit for each PMOS switch transistor, which consists of a voltage monitoring module and a potential switching module:

[0051] The voltage monitoring module is used to detect the voltage values of the source terminal, drain terminal and intermediate node of the switch transistor in real time;

[0052] The potential switching module is used to dynamically select to connect the substrate to the input voltage Vin, the output voltage Vout, or the intermediate node potential VA / VB according to the monitoring result and the current working stage, and determine by the CLKP / CLKN state.

[0053] The working stage of the charge pump adjusts the substrate potential:

[0054] During the charging stage, CLKP is high and CLKN is low:

[0055] SW1 and SW4 are turned on, and SW2 and SW3 are turned off;

[0056] The substrate of SW1 is connected to Vin, and the source terminal is connected to VA. If the load increases and causes VA < Vin, the substrate potential Vin is still higher than the source terminal voltage, maintaining reverse bias;

[0057] The substrate of SW4 is connected to the VB intermediate node, and the source terminal is grounded. If the load increases and causes VB > 0, the dynamic biasing circuit transmits the VB potential to the SW4 substrate to satisfy VB ≥ 0;

[0058] The substrates of the turned-off SW2 and SW3 are respectively connected to Vin and Vout, and the drain terminal voltages VB and VA are always lower than the substrate potential;

[0059] During the pumping stage, CLKP is low and CLKN is high:

[0060] SW2 and SW3 are turned on, and SW1 and SW4 are turned off;

[0061] The substrate of SW2 is connected to Vin, and the drain terminal is connected to VB. If the load increases and causes VB < Vin, the substrate potential Vin is still higher than the drain terminal voltage, maintaining reverse bias;

[0062] The substrate of SW3 is connected to VA, and the source terminal is connected to Vout. If the load increases and causes VA > Vout, the dynamic biasing circuit transmits the VA potential to the SW3 substrate to make VA ≥ Vout;

[0063] The substrates of the turned-off SW1 and SW4 are respectively connected to VA and V.

[0064] For different charge pump topologies, NMOS switches, hybrid switches, and multi - voltage - multiplier charge pumps, the dynamic substrate biasing circuit can be adjusted:

[0065] The NMOS switching tube is used to connect the substrate to the lowest potential node monitored dynamically, so that the source / drain terminal voltage ≤ the substrate potential;

[0066] The hybrid switch designs independent dynamic biasing circuits for PMOS and NMOS respectively;

[0067] Multi - voltage charge pump: Add a potential switching module according to the number of intermediate nodes to ensure that the substrate potential of all switching transistors is adapted in real time.

[0068] Extend to other charge pump architectures, including NMOS switching transistors, hybrid switching transistors, and multi - voltage charge pumps. Dynamically adjust the substrate connection according to the rules respectively to ensure that the base - emitter of the parasitic triode of all switching transistors is reverse - biased. Through simulation and actual testing, it is verified that under dynamic substrate biasing, the base - emitter of the parasitic PNP triode of the PMOS transistor is always in the reverse - biased state.

[0069] Verify the operating state of the charge pump under light load and heavy load through simulation and actual measurement, and optimize the dynamic biasing logic to cover extreme load conditions.

[0070] The power electronic device of a method for preventing current leakage in a charge pump switching transistor with dynamic substrate biasing according to the present invention includes: one or more processors, a memory, and one or more programs. Wherein one or more programs are stored in the memory and are configured to be executed by one or more processors. The programs include instructions for executing the method for preventing current leakage in a dynamic substrate biasing as described in any one of claims 1 to 7. The power electronic device dynamically adjusts the substrate connection of the charge pump switching transistor to a specific potential node, monitors the voltage values of the source terminal, drain terminal, and intermediate nodes in real time, and switches the substrate connection according to the clock signals CLKP / CLKN to ensure that the reverse - bias condition is always satisfied between the source / drain and the substrate, thereby avoiding current leakage caused by the conduction of the parasitic PNP / NPN triode and improving the driving ability and efficiency of the charge pump.

[0071] A specific application of this embodiment is:

[0072] Figure One Taking a 2 - times positive - voltage charge pump with PMOS switching transistors as an example to illustrate the core idea of the patent, that is, the substrate end of the PMOS switching transistor adopts dynamic biasing technology to ensure that the substrate of the PMOS switching transistor is in the reverse - biased state whether the charge pump is under heavy load or light load, thereby avoiding the internal nodes of the charge pump from leaking current to the PSUB through the parasitic PNP triode in the PMOS switching transistor, reducing the self - current consumption of the charge pump, improving the efficiency of the charge pump, and enhancing the driving ability of the charge pump. In fact, the switching of the 2 - times charge pump can be implemented using PMOS, NMOS, or a combination of PMOS / NMOS switching transistors. At this time, the substrate of the PMOS or NMOS switch can also adopt the dynamic biasing method to avoid the forward biasing of the substrate of the MOS switch when the charge pump is under heavy load; in addition, a similar idea can be used for the substrate biasing method of the MOS transistor switch in a multi - times negative - voltage or multi - times positive - voltage charge pump;

[0073] Embodiment 1:Figure 4 Technical schematic diagram for preventing switch substrate current leakage applied to a 2x positive charge pump (NMOS is used for the switch tube);

[0074] Two-phase clocks (CLKP / CLKN) are used to control the NMOS switches to achieve voltage multiplication;

[0075] Charging stage: When CLKP is high, SW1 conducts, and capacitor C1 is charged to Vin; when CLKN is low, SW3 is off;

[0076] Transfer stage: When CLKN is high, SW3 conducts, and the voltage of capacitor C1 is superimposed on Vin, and Vout = 2Vin is output through SW3;

[0077] Substrate leakage prevention: The substrates (B) of the NMOS are all grounded (0 / Volt) to ensure that the parasitic diodes are reverse-biased and prevent substrate current leakage;

[0078] Example 2: Figure 5 Technical schematic diagram for preventing switch substrate current leakage applied to a 2x positive charge pump (NMOS / PMOS is used for the switch tube);

[0079] Complementary switches (NMOS + PMOS) are introduced to optimize the substrate connection;

[0080] NMOS (SW1 / SW3): The substrate is grounded and is controlled to conduct by CLKP / CLKN;

[0081] PMOS (SW2): The substrate is connected to Vout (the highest potential) to avoid the conduction of the parasitic diode;

[0082] Capacitor charge and discharge: CLKP / CLKN drive alternately, and the voltages of capacitors C1 and C2 are superimposed in series, and finally Vout = 2Vin;

[0083] Example 3: Figure 6 Technical schematic diagram for preventing switch substrate current leakage applied to a 1x negative charge pump (PMOS is used for the switch tube);

[0084] Generate Vout = -Vin;

[0085] Charging stage: When CLKP is high, SW1 conducts, and capacitor C1 is charged to Vin;

[0086] Inversion stage: When CLKP is low, SW3 conducts, the negative electrode of capacitor C1 is grounded, and the positive electrode outputs Vout = -Vin;

[0087] Substrate leakage prevention: The substrate (B) of the PMOS is connected to the highest potential (Vin) to prevent parasitic leakage;

[0088] Embodiment 4: Figure 7 A schematic diagram of the technology for preventing switch substrate current leakage applied to a 1x negative voltage charge pump (NMOS / PMOS for the switch tube);

[0089] MMOS special structure: hybrid MOS (may be depletion type or special process device);

[0090] Capacitor charging and discharging path: CLKP / CLKN drive switches to be turned on alternately, and capacitors Cs1 and Cp form a charging and discharging loop;

[0091] Substrate control: The substrate of the MMOS is dynamically biased (e.g. connected to CLKN or GND) to ensure that the parasitic diode is always reverse biased during the switching process;

[0092] Embodiment five: Figure 8 A schematic diagram of the technology for preventing switch substrate current leakage applied to a 3x positive charge pump (NMOS / PMOS for the switch tube);

[0093] Connecting multiple capacitors in series can achieve a 3-fold voltage boost;

[0094] Multi-stage charging and discharging: The charging and discharging of three-stage capacitors are controlled by CLKP / CLKN in a time-sharing manner, and the voltage is superimposed step by step.

[0095] Substrate connection: The substrate of MMOS / PMOS is connected to the lowest (GND) and highest (Vout) potentials respectively to prevent leakage;

[0096] Embodiment six: Figure 9 A schematic diagram of the technology for preventing switch substrate current leakage applied to a 2x positive charge pump (NMOS / PMOS for the switch tube);

[0097] Generate Vout = -2Vi n;

[0098] Two-phase charging and discharging: CLK drives multiple sets of switches (sv1-sv6), and the capacitors Csl and CLKF are charged and discharged alternately;

[0099] Voltage superposition: Through capacitor series connection and ground potential inversion, output Vout = -2Vi n;

[0100] Substrate isolation: The NMOS substrate is grounded and the PMOS substrate is connected to Vout to ensure that the parasitic diode is reverse biased.

[0101] It is worth noting that in the above system embodiment, the various units included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention.

[0102] In addition, those of ordinary skill in the art can understand that all or part of the steps in the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the corresponding program can be stored in a computer-readable storage medium.

[0103] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for preventing current leakage by dynamic substrate bias of a charge pump switch tube, characterized in that: A charge pump circuit with a 2x positive voltage that includes MOS switches SW1, MOS switches SW2, MOS switches SW3, MOS switches SW4, a storage capacitor Cs1, and non-overlapping clock signals CLKP / CLKN. Its source or drain is periodically turned on or off according to the clock signal.

2. A method for preventing current leakage by dynamic substrate bias of a charge pump switch tube, characterized in that: According to the switch type PMOS, NMOS, or hybrid type, dynamically connect the substrate terminals of each switch to specific potential nodes Vin, Vout, VA, VB, or GND to ensure that the substrate and the source / drain terminals are reverse-biased in the initial state. During the charging stage, CLKP is high and CLKN is low. Turn on switches SW1 and SW4, and turn off switches SW2 and SW3. Dynamically adjust the substrate potential of SW1 and SW4 to ensure that the substrate potential is always higher than or equal to the source / drain potential. During the charge pumping stage, CLKP is low and CLKN is high. Turn on switches SW2 and SW3, and turn off switches SW1 and SW4. Dynamically adjust the substrate potential of SW2 and SW3 to ensure that the substrate potential is always higher than or equal to the source / drain potential. Switch the substrate connection according to the clock signal, monitor the node voltage in real time, and dynamically adjust the substrate connection to the highest potential node corresponding to the current working stage to ensure that the reverse bias condition is always satisfied between the source / drain and the substrate.

3. The method for preventing current leakage of a charge pump switch tube by dynamic substrate bias according to claim 1, characterized in that: Configure an independent dynamic substrate bias circuit for each of the PMOS switches. This circuit consists of a voltage monitoring module and a potential switching module: The voltage monitoring module is used to detect the voltage values of the source terminal, drain terminal, and intermediate nodes of the switch in real time. The potential switching module is used to dynamically select the substrate connection to the input voltage Vin, output voltage Vout, or the intermediate node potential VA / VB according to the monitoring results and the current working stage, determined by the CLKP / CLKN state.

4. The method for preventing current leakage of a charge pump switch tube by dynamic substrate bias according to claim 1, characterized in that: The working stage of the charge pump adjusts the substrate potential: During the charging stage, CLKP is high and CLKN is low: SW1 and SW4 are turned on, and SW2 and SW3 are turned off; The substrate of SW1 is connected to Vin, the source terminal is connected to VA. If the load increases and VA < Vin, the substrate potential Vin is still higher than the source terminal voltage, maintaining the reverse bias; The substrate of SW4 is connected to the intermediate node VB, the source terminal is grounded. If the load increases and VB > 0, the dynamic bias circuit transfers the VB potential to the substrate of SW4 to satisfy VB ≥ 0; The substrates of the turned-off SW2 and SW3 are connected to Vin and Vout respectively, and the drain terminal voltages VB and VA are always lower than the substrate potential; During the charge pumping stage, CLKP is low and CLKN is high: SW2 and SW3 are turned on, and SW1 and SW4 are turned off; The substrate of SW2 is connected to Vin, the drain terminal is connected to VB. If the load increases and VB < Vin, the substrate potential Vin is still higher than the drain terminal voltage, maintaining the reverse bias; The substrate of SW3 is connected to VA, the source terminal is connected to Vout. If the load increases and VA > Vout, the dynamic bias circuit transfers the VA potential to the substrate of SW3 to make VA ≥ Vout; The substrates of the turned-off SW1 and SW4 are connected to VA and V respectively.

5. The method for preventing current leakage of a charge pump switch tube by dynamic substrate bias according to claim 1, characterized in that: For different charge pump topologies, NMOS switches, hybrid switches, and multi-stage charge pumps, the dynamic substrate bias circuit can be adjusted: The NMOS switch tube is used to connect the substrate to the lowest potential node of dynamic monitoring, so that the source / drain voltage is less than or equal to the substrate potential; The hybrid switch is designed with independent dynamic bias circuits for PMOS and NMOS respectively; Multi-voltage charge pump: Add potential switching modules according to the number of intermediate nodes to ensure real-time adaptation of the substrate potential of all switching tubes.

6. A method for preventing current leakage of a charge pump switch tube by dynamic substrate bias according to claim 1, characterized in that: Expanded to other charge pump architectures, including NMOS switch tubes, hybrid switch tubes and multi-voltage charge pumps, the substrate connection is dynamically adjusted according to the rules to ensure that the parasitic transistor base-emitter of all switch tubes is reverse biased. Through simulation and actual test verification, it is found that under dynamic substrate bias, the parasitic PNP transistor base-emitter of the PMOS tube is always in a reverse biased state.

7. A method for preventing current leakage of a charge pump switch tube by dynamic substrate bias according to claim 6, characterized in that: The working state of the charge pump under light load and heavy load is verified through simulation and actual measurement, and the dynamic bias logic is optimized to cover extreme load conditions.

8. The power electronic device of the charge pump switch tube dynamic substrate bias current leakage prevention method according to claim 1 comprises: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, the programs include instructions for executing the dynamic substrate bias current leakage prevention method as described in any one of claims 1 to 7, the power electronic device dynamically adjusts the substrate of the charge pump switch tube to connect to a specific potential node, monitors the voltage values ​​of the source end, the drain end and the intermediate node in real time, and switches the substrate connection according to the clock signal CLKP / CLKN, to ensure that the reverse bias condition is always satisfied between the source / drain and the substrate.

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