Current trimming circuit and chip

Abstract

The invention provides a current trimming circuit and a chip, which are suitable for the field of high-precision PWM (Pulse Width Modulation) power supply management and motor driving chips. According to the invention, the problem of oscillator frequency error caused by process deviation is solved. The circuit comprises a trimming fuse switch module, a trimming current source driving module, a trimming current source module and a proportional current sampling module. Through a fuse trimming mode, an external trimming digital code is received, a corresponding trimming current source is driven, and an accurate charging current is provided for an external slope capacitor, so that the working frequency of the relaxation oscillator is calibrated. In addition, due to the design of the fuse switch module, normal overturning of a logic signal when the fuse is not completely burnt out is ensured, and the trimming robustness is improved. The proportional current sampling module reduces the noise and temperature influence through the operational amplifier feedback and mirror current technology, and improves the stability and matching precision of the current source. According to the technical scheme, the frequency accuracy of the oscillator is effectively improved, and the requirement for the driving capacity of the fuse switch is lowered.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a current trimming circuit and a chip. Background Art

[0002] Pulse-width modulation control technology (PWM) plays a key role in the design of integrated circuits such as power management chips and motor drive chips. A reliable PWM design requires a stable oscillation frequency as a support. In the industry, in most cases, the PWM operating frequency is generated by an internal oscillator circuit, and the relaxation oscillator occupies a large market share due to its simple structure, stability, and reliability.

[0003] The relaxation oscillator relies on an accurate current source to charge the ramp capacitor, and the stability of the current source directly determines the accuracy of the output frequency. During the manufacturing process of integrated circuits, process inevitably introduces random errors, resulting in deviations in device parameters (such as resistors, bias currents of current sources, etc.), causing current source mismatch. This mismatch will ultimately lead to inaccurate charging current, causing the operating frequency output by the oscillator to deviate from the designed value and affecting the performance of PWM.

[0004] In addition to the above problems, the fuse trimming scheme is also a potential trimming method. However, the problems it has are as follows:

[0005] 1. The robustness of fuse trimming is relatively low. Traditional designs have high requirements for the output driving ability of the trimming fuse switch, which easily leads to problems where the trimming circuit cannot work properly. If the fuse is not completely blown, it may cause the logic signal to fail to flip correctly, thereby affecting the normal operation of the trimming circuit.

[0006] 2. When the traditional current sampling module generates the proportional current, it is restricted by environmental temperature, noise, and process deviation, resulting in unstable current or insufficient matching accuracy. The reduction of current sampling accuracy will directly affect the trimming accuracy of the oscillator frequency, especially in high-precision application scenarios, the problem is particularly prominent. Summary of the Invention

[0007] The present invention provides a high-side NMOS driving circuit and a chip. To achieve the above object, the present invention adopts the following technical solutions:

[0008] A current trimming circuit includes a trimming fuse switch module, a trimming current source driving module, a trimming current source module, and a proportional current sampling module;

[0009] The input end of the trimming fuse switch module is used to receive the externally input trimming digital code. The output end of the trimming fuse switch module is connected to the input end of the trimming current source driving module, and is used to select the turning on or off of the trimming current source driving module. The output end of the trimming current source driving module is connected to the control end of the trimming current source module, and is used to stabilize the working voltage of the subsequent circuit. The output end of the proportional current sampling module is connected to the input end of the trimming current source module, and is used to externally connect a reference voltage source and output an image reference current. The output end of the trimming current source module is used to charge an external ramp capacitor to generate a trimmed ramp voltage.

[0010] Further, the trimming fuse switch module includes a bias circuit and a fuse switch circuit;

[0011] The bias circuit includes PMOS transistor MP1, PMOS transistor MP2, NMOS transistor MN1, NMOS transistor MN2, resistor R1, and resistor R2;

[0012] The gates of PMOS transistor MP1 and PMOS transistor MP2 are commonly connected and receive a reference power supply signal. The sources of PMOS transistor MP1 and PMOS transistor MP2 are connected to the power supply voltage. The drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN1. The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN2. The gate of NMOS transistor MN1 is connected to its drain. The gates of NMOS transistor MN1 and NMOS transistor MN2 are commonly connected. The source of NMOS transistor MN1 is connected to one end of resistor R1, and the other end of resistor R1 is grounded. The source of NMOS transistor MN2 is connected to one end of resistor R2, and the other end of resistor R2 is grounded;

[0013] The trimming digital code is a three-bit trimming signal. The fuse switch circuit includes three groups of parallel single-bit trimming fuse switch branches. The structure of each group of branches is the same and is used for the input of one trimming signal in the three-bit trimming digital code. One of the single-bit trimming fuse switch branches includes PMOS transistor MP3, NMOS transistor MN3, resistor R3, and trimming fuse resistor FUSE1;

[0014] The source of PMOS transistor MP3 is connected to the power supply voltage. The gate of PMOS transistor MP3 receives a reference power supply signal. The drain of PMOS transistor MP3 is connected to the drain of NMOS transistor MN3 and the input end of inverter INV1. The output end of inverter INV1 is used to output a trimming signal. The gate of NMOS transistor MN3 is connected to the gate of NMOS transistor MN1 in the bias circuit. The source of NMOS transistor MN3 is connected to one end of resistor R3. The other end of resistor R3 is connected to one end of fuse resistor FUSE1 and is used for inputting a trimming signal. The other end of fuse resistor FUSE1 is grounded.

[0015] Further, the trimming current source driving module includes three groups of single-bit trimming current source driving branches arranged in parallel, and the structures of each group of branches are the same; one of the single-bit trimming current source driving branches includes PMOS transistor MP6, PMOS transistor MP7, BJT transistor Q1, BJT transistor Q2, resistor R6, resistor R7, and NMOS transistor MN6;

[0016] The source of the PMOS transistor MP6 is connected to the power supply voltage, the gate receives the reference power supply signal, and the drain is connected to the collector of the BJT transistor Q1; the source of the PMOS transistor MP7 is connected to the power supply voltage, the gate receives the reference power supply signal, and the drain is connected to the collector of the BJT transistor Q2 and outputs the working voltage signal; the base of the BJT transistor Q1 is connected to its collector and the base of the BJT transistor Q2, the emitter of the BJT transistor Q1 is connected to one end of the resistor R6; the emitter of the BJT transistor Q2 is connected to one end of the resistor R7, and the other end of the resistor R7 is grounded; the other end of the resistor R6 is connected to the drain of the NMOS transistor MN6, and the gate of the NMOS transistor MN6 is used to input the trimming signal; the source of the NMOS transistor MN6 is grounded.

[0017] Further, the proportional current sampling module includes PMOS transistor MP12, PMOS transistor MP13, PMOS transistor MP14, NMOS transistor MN9, NMOS transistor MN10, frequency-selective resistor RT, and operational amplifier OPA;

[0018] The positive input terminal of the operational amplifier OPA is externally connected to the reference voltage source, the negative input terminal of the operational amplifier is connected to one end of the frequency-selective resistor RT, the source of the NMOS transistor MN9, and the source of the NMOS transistor MN10, and the output terminal of the operational amplifier is connected to the gates of the NMOS transistor MN9 and the NMOS transistor MN10; the other end of the frequency-selective resistor RT is grounded; the drain of the NMOS transistor MN9 is connected to the drain of the PMOS transistor MP12; the drain of the NMOS transistor MN10 is connected to the drain of the PMOS transistor MP13; the gate and drain of the PMOS transistor MP12 are connected, and the source of the PMOS transistor MP12 is connected to the power supply voltage; the gate and drain of the PMOS transistor MP13 are connected, and the source of the PMOS transistor MP13 is connected to the power supply voltage; the source of the PMOS transistor MP14 is connected to the power supply voltage, the gate of the PMOS transistor MP14 is connected to the gate of the PMOS transistor MP13, and the source of the PMOS transistor MP14 is used to output the mirror reference current.

[0019] Further, the trimming current source module includes PMOS transistors MP15, MP16, MP17, MP18, MP19, MP20, MP21, MP22, MP23, NMOS transistors MN11, MN12, MN13, and MN14;

[0020] The drain of the NMOS transistor MN11 inputs the mirror reference current. The gate and drain of the NMOS transistor MN11 are connected and connected to the gate of the NMOS transistor MN12. The source of the NMOS transistor MN11 is grounded. The source of the NMOS transistor MN12 is grounded, and the drain of the NMOS transistor MN12 is connected to the drain of the PMOS transistor MP15. The source of the PMOS transistor MP15 is connected to the power supply voltage, and the gate and drain of the PMOS transistor MP15 are connected. The gates of the PMOS transistors MP16, MP17, and MP18 are connected to the gate of the PMOS transistor MP15. The sources of the PMOS transistors MP16, MP17, and MP18 are connected to the power supply voltage. The drains of the PMOS transistors MP16, MP17, and MP18 are respectively connected to the sources of the PMOS transistors MP20, MP21, and MP22. The gates of the PMOS transistors MP20, MP21, and MP22 respectively receive the working voltage signals output by the trimming current source driving module. The drains of the PMOS transistors MP20, MP21, and MP22 are connected to the drain of the NMOS transistor MN13. The gate and drain of the NMOS transistor MN13 are connected, and the source of the NMOS transistor MN13 is grounded. The sources of the PMOS transistors MP19 and MP23 are connected to the power supply voltage. The gate and drain of the PMOS transistor MP19 are connected, and the drain of the PMOS transistor MP19 is connected to the drain of the NMOS transistor MN14. The gate of the NMOS transistor MN14 is connected to the gate of the NMOS transistor MN13, and the source of the NMOS transistor MN14 is grounded. The gate of the PMOS transistor MP23 is connected to the gate of the PMOS transistor MP19, and the drain of the PMOS transistor MP19 is used to charge an external ramp capacitor.

[0021] The present invention also provides a chip integrating the current trimming circuit described above.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] 1. The oscillator frequency error caused by process deviation is effectively solved through fuse trimming. When the measured oscillator frequency cannot meet the rated frequency, according to the pre-designed trimming bits, the digital code of the trimming fuse switch is set to drive the corresponding trimming current source, thereby calibrating the oscillator frequency error.

[0024] 2. The trimming fuse switch module realizes the normal flip of the trimming logic when the fuse is not completely blown, improving the robustness of fuse trimming.

[0025] 3. The proportional current sampling module achieves a higher matching degree of the sampling current source, reduces the influence of the proportional current by environmental noise, and improves the accuracy of the trimmed sampling current; the trimming drive module reduces the requirement for the output drive ability of the trimming fuse switch, improving the reliability of trimming. Description of the Drawings

[0026] Figure 1 It is the current trimming circuit structure diagram of the embodiment of the present invention;

[0027] Figure 2 It is the circuit diagram of the trimming fuse switch module of the embodiment of the present invention;

[0028] Figure 3 It is the circuit diagram of the current source drive module of the embodiment of the present invention;

[0029] Figure 4 It is the circuit diagram of the proportional current sampling module of the embodiment of the present invention;

[0030] Figure 5 It is the circuit diagram of the trimming current source module of the embodiment of the present invention.

[0031] In the above-mentioned drawings: 1. Current trimming circuit; 2. Trimming fuse switch module; 3. Trimming current source drive module; 4. Trimming current source module; 5. Proportional current sampling module; 6. Bias circuit; 7. Fuse switch circuit. Detailed Embodiment

[0032] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the accompanying drawings. The exemplary embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein. On the contrary, these embodiments are provided so that the present invention will be more comprehensive and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "mounted", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] The circuit structure diagram of the current trimming circuit in this embodiment is as Figure 1 shown. The current trimming circuit 1 includes a trimming fuse switch module 2, a trimming current source driving module 3, a trimming current source module 4, and a proportional current sampling module 5.

[0034] In this embodiment, the trimming digital code used is a three-bit trimming signal DATA<2:0>. The external three-bit trimming signal DATA<2:0> is input in parallel to the input terminal SI<2:0> of the trimming fuse switch module 2. The output terminal SO<2:0> of the trimming fuse switch module 2 is connected to the input terminal OSC<2:0> of the trimming current source driving module 3, which is used to select the on or off of the trimming current source driving module 3. The output terminal QO<2:0> of the trimming current source driving module 3 is connected to the control terminal QB<2:0> of the trimming current source module 4, which is used to stabilize the working voltage of the subsequent circuit. The output terminal RO of the proportional current sampling module 5 is connected to the input terminal IN of the trimming current source module 4, which is used to externally connect a reference voltage source V REF , and output an image reference current; the output terminal IO of the trimming current source module 4 is used to charge an external ramp capacitor C RAMP to generate a trimmed ramp voltage V RAMP .

[0035] The circuit diagram of the trimming fuse switch module in this embodiment is as Figure 2 shown. The trimming fuse switch module 2 includes a bias circuit 6 and a fuse switch circuit 7.

[0036] Among them, the bias circuit 6 includes PMOS transistor MP1, PMOS transistor MP2, NMOS transistor MN1, NMOS transistor MN2, resistor R1 and resistor R2. The gates of the PMOS transistor MP1 and the PMOS transistor MP2 are commonly connected and receive a reference power supply signal BIAS_TRIM with a voltage of 3.7V. The sources of the PMOS transistor MP1 and the PMOS transistor MP2 are connected to the power supply voltage VCC. The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1. The drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2. The gate of the NMOS transistor MN1 is connected to its drain. The gates of the NMOS transistor MN1 and the NMOS transistor MN2 are commonly connected. The source of the NMOS transistor MN1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded. The source of the NMOS transistor MN2 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded.

[0037] The resistors R1 and R2 are used as bias resistors, and their resistance values are both 14.85 kΩ. Assuming that all MOS transistors are in the saturation region, the drain current of the PMOS transistor MP1 is:

[0038]

[0039] In the formula, I D1 is the drain current of the PMOS transistor MP1, μ P is the hole mobility, V GS is 1.3V, (W / L) MP1 is the width-to-length ratio of the PMOS transistor MP1, C OX is the capacitance per unit area of the oxide layer, V THP is the threshold voltage of the PMOS transistor.

[0040] In this embodiment, the fuse switch circuit 7 includes three groups of parallel single-bit trimming fuse switch branches. The structure of each group of branches is the same and is used for the input of one trimming signal in the three-bit trimming signal DATA<2:0>. One of the single-bit trimming fuse switch branches includes a PMOS transistor MP3, an NMOS transistor MN3, a resistor R3 and a trimming fuse resistor FUSE1.

[0041] The source of the PMOS transistor MP3 is connected to the power supply voltage VCC. The gate of the PMOS transistor MP3 receives a reference power supply signal BIAS_TRIM with a voltage of 3.7V. The drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN3 and the input terminal of the inverter INV1. The output terminal of the inverter INV1 is SO<0>, which is used to output the trimming signal. The gate of the NMOS transistor MN3 is connected to the gate of the NMOS transistor MN1 in the bias circuit 6. The source of the NMOS transistor MN3 is connected to one end of the resistor R3. The other end of the resistor R3 is connected to one end of the fuse resistor FUSE1 and serves as the input terminal SI<0> for inputting the trimming signal. The other end of the fuse resistor FUSE1 is grounded.

[0042] Taking a single-bit trimming fuse switch branch as an example, the resistance of the fuse resistor FUSE1 is ≤100Ω. When a high-level pulse is input from the port SI<0> to the trimming signal, the fuse resistor FUSE1 can be blown when the current passing through it is higher than 50mA. The blown fuse resistor FUSE1 is regarded as having an infinite impedance, and the drain voltage of the PMOS transistor MP3 is raised from V Z to nearly VCC - V OV3 , where V OV3 is the overdrive voltage of the PMOS transistor MP3. Then, under the condition of self-bias, the size of the NMOS transistor MN3 is set so that the voltage V Z can "escape from the range of noise margin". The noise margin refers to the input voltage range within which the inverter INV1 can correctly flip. When the voltage of V Z is raised, the output terminal SO<0> outputs a low level, completing the trimming of this bit of the fuse switch.

[0043] The R3 resistor is set to 14.85kΩ to limit the current magnitude of this branch. The current of this branch is provided by the PMOS transistor MP3. The gate voltage V Y of the NMOS transistor MN3 is set near the logic noise margin of the inverter INV1 to ensure that after trimming this bit of the fuse switch, the voltage change of V Z can cause the inverter INV1 to flip normally. The ratio of the size of the PMOS transistor MP3 to the size of the PMOS transistor MP1 is set to (3:7.5) to ensure that before trimming, the voltage of V Z is lower than the voltage of V Y . This can increase the working range of V Z , avoid mis-triggering logic flips, and ensure the normal operation of the circuit.

[0044] Among them, the expression of V Y is:

[0045]

[0046] Wherein, V THN is the threshold voltage of the NMOS transistor, μ N is the electron mobility, (W / L) MN1 is the width-to-length ratio of the MN1 transistor.

[0047] Further, in the trimming fuse switch module 2, the NMOS transistors MN1 - MN5 are all set as "inverse ratio transistors". Taking a single-bit trimming fuse switch branch as an example, an "inverse ratio transistor" means that the NMOS transistor MN3 has a smaller driving ability compared to the PMOS transistor MP3 that provides the branch current. This usually means that the width-to-length ratio (W / L) of the NMOS transistor MN3 is smaller, making its conduction ability weaker. Therefore, even when the source voltage of the NMOS transistor MN3 slightly increases, resulting in a slight decrease in the branch current (for example, when the fuse resistance FUSE1 is not completely blown), the V Z voltage can still be quickly pulled up by the PMOS transistor MP3 with strong driving ability. This high-sensitivity design ensures that even if the fuse resistance FUSE1 is not completely open, the inverter INV1 can still detect the V Z voltage change, thereby achieving the correct flip of the logic state.

[0048] Further, compared with the PMOS transistor MP1, setting the PMOS transistor MP3 to a smaller width-to-length ratio means that the conduction ability of the PMOS transistor MP3 is weaker. This design makes it so that when the circuit is powered on and initialized, the V Z voltage will not be erroneously higher than V Y , increasing the safe operating voltage range of the circuit and avoiding logic misflipping; the parameter design of the PMOS transistor MN3 can effectively prevent external current backflow caused by too high a voltage of the input signal SI<0>, improving the robustness of the circuit.

[0049] The circuit diagram of the current source driving module in this embodiment is as shown in Figure 3 The figure. The trimming current source driving module 3 includes three groups of parallel single-bit trimming current source driving branches. The structure of each group of branches is the same and is used for the input of one signal in the three-bit trimming signal SO<2:0>. One trimming current source driving branch includes the PMOS transistor MP6, the PMOS transistor MP7, the BJT transistor Q1, the BJT transistor Q2, the resistor R6, the resistor R7, and the NMOS transistor MN6.

[0050] The source of the PMOS transistor MP6 is connected to the power supply voltage VCC, the gate receives the reference voltage source signal BIAS_TRIM of 3.7V, and the drain is connected to the collector of the BJT transistor Q1. The source of the PMOS transistor MP7 is connected to the power supply voltage VCC, the gate receives the reference voltage source signal BIAS_TRIM of 3.7V, and the drain is connected to the collector of the BJT transistor Q2 and outputs the working voltage signal QO<0>. The base of the BJT transistor Q1 is connected to its collector and the base of the BJT transistor Q2. The emitter of the BJT transistor Q1 is connected to one end of the resistor R6. The emitter of the BJT transistor Q2 is connected to one end of the resistor R7, and the other end of the resistor R7 is grounded. The other end of the resistor R6 is connected to the drain of the NMOS transistor MN6. The gate of the NMOS transistor MN6 is used as the input terminal OSC<0> for inputting the trimming signal. The source of the NMOS transistor MN6 is grounded.

[0051] The circuit diagram of the proportional current sampling module in this embodiment is as Figure 4 shown. The proportional current sampling module 5 includes a PMOS transistor MP12, a PMOS transistor MP13, a PMOS transistor MP14, an NMOS transistor MN9, an NMOS transistor MN10, a frequency-selective resistor RT, and an operational amplifier OPA.

[0052] The positive input terminal RI of the operational amplifier OPA is externally connected to the 2V reference voltage source V REF , the negative input terminal of the operational amplifier is connected to one end of the frequency-selective resistor RT, the source of the NMOS transistor MN9, and the source of the NMOS transistor MN10. The output terminal of the operational amplifier is connected to the gates of the NMOS transistor MN9 and the NMOS transistor MN10. The other end of the frequency-selective resistor RT is grounded. The drain of the NMOS transistor MN9 is connected to the drain of the PMOS transistor MP12. The drain of the NMOS transistor MN10 is connected to the drain of the PMOS transistor MP13. The gate and the drain of the PMOS transistor MP12 are connected, and the source of the PMOS transistor MP12 is connected to the power supply voltage. The gate and the drain of the PMOS transistor MP13 are connected, and the source of the PMOS transistor MP13 is connected to the power supply voltage. The source of the PMOS transistor MP14 is connected to the power supply voltage. The gate of the PMOS transistor MP14 is connected to the gate of the PMOS transistor MP13. The source of the PMOS transistor MP14 is used as the output terminal RO for outputting the mirror reference current.

[0053] The operational amplifier OPA, PMOS transistor MP12, PMOS transistor MP13, NMOS transistor MN9, NMOS transistor MN10, and frequency-selective resistor RT form a linear voltage regulator structure. Among them, PMOS transistors MP12 and MP13 provide current for its branches, NMOS transistors MN9 and MN10 are used as power transistors to stabilize the voltage, the branches of PMOS transistor MP13 and NMOS transistor MN10 are proportional current branches, and PMOS transistor MP14 is a proportional current mirror PMOS transistor.

[0054] The positive input terminal of the operational amplifier OPA is externally connected to a reference voltage V of 2V. REF , the input impedance of the operational amplifier OPA is infinite, and V X is equal to 2V at the same time. Compared with the main current path (PMOS transistor MP12 and NMOS transistor MN9), the proportional current branch formed by PMOS transistor MP13 and NMOS transistor MN10 has a smaller number of transistors in PMOS transistor MP13 and NMOS transistor MN10 than the main path. The ratio of the number of transistors of PMOS transistor MP12 to that of PMOS transistor MP13 is designed to be 4:1, and the ratio of the number of transistors of MN9 to that of NMOS transistor MN10 is 4:1. This makes the current flowing through the proportional current branch (PMOS transistor MP13 and NMOS transistor MN10) be 1 / 4 of the main current. The expression of the reference current I X is as follows:

[0055]

[0056] PMOS transistor MP13 further mirrors the current in the proportional current branch to the output terminal RO. The ratio of the number of transistors of PMOS transistor MP13 to that of PMOS transistor MP14 is 4:1. Therefore, the output current is scaled proportionally again. The proportional relationship between the output current I O and the reference current I X is as follows:

[0057]

[0058] This proportional current sampling module 5 designs a proportional current branch to isolate the environment of V Z (the drain of PMOS transistor MP13) from the V Y (the drain of PMOS transistor MP12) of the main power path, and through reasonable layout and branch design of the layout, reduces the influence of the external environmental noise on the V Z point, thereby improving the accuracy of the output current I O .

[0059] The trimming current source module of this embodiment is as Figure 5As shown, the trimming current source module 4 includes PMOS transistors MP15, MP16, MP17, MP18, MP19, MP20, MP21, MP22, MP23, NMOS transistors MN11, MN12, MN13, and MN14.

[0060] The drain of the NMOS transistor MN11 serves as the input terminal IN, and the input mirror reference current I O , the gate and drain of the NMOS transistor MN11 are connected and connected to the gate of the NMOS transistor MN12, and the source of the NMOS transistor MN11 is grounded; the source of the NMOS transistor MN12 is grounded, and the drain of the NMOS transistor MN12 is connected to the drain of the PMOS transistor MP15; the source of the PMOS transistor MP15 is connected to the power supply voltage, and the gate and drain of the PMOS transistor MP15 are connected; the gates of the PMOS transistors MP16, MP17, and MP18 are connected to the gate of the PMOS transistor MP15, the sources of the PMOS transistors MP16, MP17, and MP18 are connected to the power supply voltage, and the drains of the PMOS transistors MP16, MP17, and MP18 are respectively connected to the sources of the PMOS transistors MP20, MP21, and MP22; the gates of the PMOS transistors MP20, MP21, and MP22 sequentially serve as the control terminals QB<0:2> to receive the working voltage signals SO<0:2> output by the trimming current source driving module 3, and the drains of the PMOS transistors MP20, MP21, and MP22 are connected to the drain of the NMOS transistor MN13; the gate and drain of the NMOS transistor MN13 are connected, and the source of the NMOS transistor MN13 is grounded; the sources of the PMOS transistors MP19 and MP23 are connected to the power supply voltage, the gate and drain of the PMOS transistor MP19 are connected, and the drain of the PMOS transistor MP19 is connected to the drain of the NMOS transistor MN14; the gate of the NMOS transistor MN14 is connected to the gate of the NMOS transistor MN13, and the source of the NMOS transistor MN14 is grounded; the gate of the PMOS transistor MP23 is connected to the gate of the PMOS transistor MP19, and the drain of the PMOS transistor MP19 serves as the output terminal IO and charges the external ramp capacitor C RAMP for charging.

[0061] Among them, the transistor number ratio of NMOS transistors MN11, MN12, MN13, and MN14 is 4:1:2:4, the transistor number ratio of MN13 and MN14 is 1:2, and the transistor number ratio of MP19 and MP23 is 1:4. Let the algebraic signals accessed by QB<0:2> be (the input high level is 1 and the input low level is 0), then the expression of the IO output current I Y is:

[0062] I Y = 2I X ·(a + 2b + 4c)

[0063] By changing the magnitude of the trimming current I Y through the entire trimming scheme, the slew rate of charging the external ramp capacitor C RAMP can be changed, thereby trimming the frequency of the relaxation oscillator.

[0064] This embodiment further includes a chip, which integrates a trimming fuse switch module 2, a trimming current source driving module 3, a trimming current source module 4, and a proportional current sampling module 5 included in the current trimming circuit 1.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not restrictive. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A current trimming circuit, characterized in that: It includes a trimming fuse switch module, a trimming current source drive module, a trimming current source module and a proportional current sampling module; The input end of the trimming fuse switch module is used to receive the trimming digital code input from the outside, and the output end of the trimming fuse switch module is connected to the input end of the trimming current source drive module to select whether to turn on or off the trimming current source drive module; The output end of the trimming current source driving module is connected to the control end of the trimming current source module, and is used to stabilize the working voltage of the subsequent circuit; The output end of the proportional current sampling module is connected to the input end of the trimming current source module, and is used to externally connect a reference voltage source and output a mirror reference current; The output end of the trimmed current source module is used to charge the external ramp capacitor to generate a trimmed ramp voltage.

2. A current trimming circuit according to claim 1, characterized in that: The trimming fuse switch module includes a bias circuit and a fuse switch circuit; The bias circuit includes a PMOS tube MP1, a PMOS tube MP2, an NMOS tube MN1, an NMOS tube MN2, a resistor R1 and a resistor R2; The gates of the PMOS tube MP1 and the PMOS tube MP2 are connected in common and receive a reference power supply signal, the sources of the PMOS tube MP1 and the PMOS tube MP2 are connected to a power supply voltage, the drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN1, and the drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN2; The gate of the NMOS transistor MN1 is connected to its drain, the gates of the NMOS transistor MN1 and the NMOS transistor MN2 are connected in common, the source of the NMOS transistor MN1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded; The source of the NMOS tube MN2 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded; The trimming digital code is a three-bit trimming signal, and the fuse switch circuit includes three groups of single-bit trimming fuse switch branches connected in parallel, each group of branches has the same structure and is used for inputting a one-bit trimming signal in the three-bit trimming digital code; One of the single-bit trimming fuse switch branches includes a PMOS transistor MP3, an NMOS transistor MN3, a resistor R3 and a trimming fuse resistor FUSE1; The source of the PMOS tube MP3 is connected to the power supply voltage, the gate of the PMOS tube MP3 receives the reference power supply signal, and the drain of the PMOS tube MP3 is connected to the drain of the NMOS tube MN3 and the input end of the inverter INV1; The output end of the inverter INV1 is used to output a trimming signal; The gate of the NMOS transistor MN3 is connected to the gate of the NMOS transistor MN1 in the bias circuit, and the source of the NMOS transistor MN3 is connected to one end of the resistor R3; The other end of the resistor R3 is connected to one end of the fuse resistor FUSE1 and is used to input a trimming signal. The other end of the fuse resistor FUSE1 is grounded.

3. The current trimming circuit according to claim 1, characterized in that: The trimmed current source driving module includes three groups of single-bit trimmed current source driving branches arranged in parallel, and the structure of each group of branches is the same; One of the single-bit trimmed current source driving branches includes a PMOS transistor MP6, a PMOS transistor MP7, a BJT transistor Q1, a BJT transistor Q2, a resistor R6, a resistor R7 and an NMOS transistor MN6; The source of the PMOS tube MP6 is connected to the power supply voltage, the gate receives the reference power supply signal, and the drain is connected to the collector of the BJT tube Q1; The source of the PMOS tube MP7 is connected to the power supply voltage, the gate receives the reference power supply signal, the drain is connected to the collector of the BJT tube Q2, and outputs the working voltage signal; The base of the BJT tube Q1 is connected to its collector and the base of the BJT tube Q2, and the emitter of the BJT tube Q1 is connected to one end of the resistor R6; The emitter of the BJT tube Q2 is connected to one end of the resistor R7, and the other end of the resistor R7 is grounded; The other end of the resistor R6 is connected to the drain of the NMOS transistor MN6, and the gate of the NMOS transistor MN6 is used to input the adjustment signal; The source of the NMOS tube MN6 is grounded.

4. The current trimming circuit according to claim 1, characterized in that: The proportional current sampling module includes a PMOS tube MP12, a PMOS tube MP13, a PMOS tube MP14, an NMOS tube MN9, an NMOS tube MN10, a frequency selection resistor R T and operational amplifier OPA; The positive input terminal of the operational amplifier OPA is connected to an external reference voltage source, and the negative input terminal of the operational amplifier is connected to a frequency selection resistor R T One end of the operational amplifier, the source of the NMOS tube MN9 and the source of the NMOS tube MN10, the output end of the operational amplifier is connected to the gate of the NMOS tube MN9 and the NMOS tube MN10; The frequency selection resistor R T The other end is grounded; The drain of the NMOS tube MN9 is connected to the drain of the PMOS tube MP12; The drain of the NMOS tube MN10 is connected to the drain of the PMOS tube MP13; The gate and drain of the PMOS tube MP12 are connected, and the source of the PMOS tube MP12 is connected to the power supply voltage; The gate and drain of the PMOS tube MP13 are connected, and the source of the PMOS tube MP13 is connected to the power supply voltage; The source of the PMOS tube MP14 is connected to the power supply voltage, the gate of the PMOS tube MP14 is connected to the gate of the PMOS tube MP13, and the source of the PMOS tube MP14 is used to output a mirror reference current.

5. The current trimming circuit according to claim 1, characterized in that: The trimming current source module includes PMOS tube MP15, PMOS tube MP16, PMOS tube MP17, PMOS tube MP18, PMOS tube MP19, PMOS tube MP20, PMOS tube MP21, PMOS tube MP22, PMOS tube MP23, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13 and NMOS tube MN14; The drain of the NMOS tube MN11 inputs a mirror reference current, the gate and drain of the NMOS tube MN11 are connected, and are connected to the gate of the NMOS tube MN12, and the source of the NMOS tube MN11 is grounded; The source of the NMOS tube MN12 is grounded, and the drain of the NMOS tube MN12 is connected to the drain of the PMOS tube MP15; The source of the PMOS tube MP15 is connected to the power supply voltage, and the gate and drain of the PMOS tube MP15 are connected; The gates of the PMOS tubes MP16, MP17 and MP18 are connected to the gate of the PMOS tube MP15, the sources of the PMOS tubes MP16, MP17 and MP18 are connected to the power supply voltage, and the drains of the PMOS tubes MP16, MP17 and MP18 are connected to the sources of the PMOS tubes MP20, MP21 and MP22 respectively; The gates of the PMOS tube MP20, the PMOS tube MP21 and the PMOS tube MP22 respectively receive the working voltage signal output by the trimming current source driving module, and the drains of the PMOS tube MP20, the PMOS tube MP21 and the PMOS tube MP22 are connected to the drain of the NMOS tube MN13; The gate and drain of the NMOS tube MN13 are connected, and the source of the NMOS tube MN13 is grounded; The source of the PMOS tube MP19 and the PMOS tube MP23 are connected to the power supply voltage, the gate and drain of the PMOS tube MP19 are connected, and the drain of the PMOS tube MP19 is connected to the drain of the NMOS tube MN14; The gate of the NMOS tube MN14 is connected to the gate of the NMOS tube MN13, and the source of the NMOS tube MN14 is grounded; The gate of the PMOS transistor MP23 is connected to the gate of the PMOS transistor MP19 , and the drain of the PMOS transistor MP19 is used to charge the external ramp capacitor.

6. A chip, characterized in that: A current trimming circuit as described in any one of claims 1 to 5 is integrated.

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