Clock phase detection circuit and method, delay-locked loop, chip and electronic equipment

Abstract

The invention relates to a clock phase detection circuit and method, a delay phase-locked loop, a chip and electronic equipment, and the circuit comprises a frequency division module which is used for carrying out the frequency division processing of a reference clock signal selected from a plurality of input clock signals with the same frequency and different phases, and generating a frequency division clock signal; the clock driving module is used for grouping a plurality of input clock signals with the same frequency and different phases to generate at least two groups of input clock signals; the detection module is used for generating a detection signal according to a time interval between the reference clock signal and the feedback clock signal based on the frequency division clock signal and the at least two groups of input clock signals; wherein the feedback clock signal is an input clock signal of the previous phase of the reference clock signal. According to the invention, on the premise of not introducing an additional clock source, the detection of the clock phase can be quickly realized by using a plurality of input clock signals with the same frequency and different phases.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and in particular, to a clock phase detection circuit, method, delay-locked loop, chip, and electronic device. Background Art

[0002] In digital circuit design, the phase detection of clock signals is a key link, especially in DLL (Delay-Locked Loop) applications. The phase detection of clock signals is mainly used to ensure the synchronization and stability of clock signals, which is crucial for the normal operation of digital circuits. However, the clock phase detection technologies in related arts often face the problem of slow detection speed.

[0003] Therefore, how to quickly implement the detection of clock phase is an urgent problem to be solved currently. Summary of the Invention

[0004] This application provides a clock phase detection circuit, chip, electronic device, and clock phase detection method. The technical solutions of this application are as follows:

[0005] A first aspect embodiment of this application proposes a clock phase detection circuit, including:

[0006] A frequency division module, configured to perform frequency division processing on a reference clock signal selected from multiple input clock signals with the same frequency but different phases to generate a divided clock signal;

[0007] A clock driving module, configured to perform grouping processing on the multiple input clock signals with the same frequency but different phases to generate at least two groups of input clock signals;

[0008] A detection module, the detection module is respectively connected to the frequency division module and the clock driving module, and the detection module is configured to generate a detection signal based on the divided clock signal and the at least two groups of input clock signals according to the time interval between the reference clock signal and the feedback clock signal; wherein, the feedback clock signal is the input clock signal of the previous phase of the reference clock signal.

[0009] A second aspect embodiment of this application proposes a delay-locked loop, including: the clock phase detection circuit as described above.

[0010] A third aspect embodiment of this application proposes a chip, including: the clock phase detection circuit as described above.

[0011] A fourth aspect embodiment of this application proposes a clock phase detection method, including:

[0012] Performing frequency division processing on a reference clock signal selected from multiple input clock signals with the same frequency but different phases to generate a divided clock signal;

[0013] Group the multiple input clock signals with the same frequency but different phases to generate at least two groups of input clock signals;

[0014] Based on the divided clock signal and the at least two groups of input clock signals, generate a detection signal according to the time interval between the reference clock signal and the feedback clock signal; wherein, the feedback clock signal is the input clock signal of the previous phase of the reference clock signal.

[0015] An embodiment of the fifth aspect of the present application provides an electronic device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the above clock phase detection method is implemented.

[0016] An embodiment of the sixth aspect of the present application provides a non-transitory computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the steps of the above clock phase detection method are implemented.

[0017] An embodiment of the seventh aspect of the present application provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the above clock phase detection method are implemented.

[0018] The technical solutions provided by the embodiments of the present application at least bring the following beneficial effects:

[0019] In the clock phase detection circuit, method, delay locked loop, chip and electronic device of the embodiments of the present application, the reference clock signal selected from multiple input clock signals with the same frequency but different phases is divided by a frequency division module to generate a divided clock signal, and the multiple input clock signals with the same frequency but different phases are grouped by a clock driving module to generate at least two groups of input clock signals. A detection signal is generated by a detection module based on the divided clock signal and the at least two groups of input clock signals according to the time interval between the reference clock signal and the feedback clock signal; wherein, the feedback clock signal is the input clock signal of the previous phase of the reference clock signal. Thus, the present application can quickly detect the clock phase by using multiple input clock signals with the same frequency but different phases without introducing an additional clock source.

[0020] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application and do not constitute an improper limitation to the present application.

[0022] Figure 1 is a schematic diagram of a clock phase detection circuit according to an embodiment of the present application;

[0023] Figure 2 is a schematic diagram of a clock phase detection circuit according to another embodiment of the present application;

[0024] Figure 3 is a schematic diagram of a low-frequency under-delay detection subunit according to an embodiment of the present application;

[0025] Figure 4 is a schematic diagram of a high-frequency under-delay detection subunit according to an embodiment of the present application;

[0026] Figure 5 is a schematic diagram of an over-delay detection unit according to an embodiment of the present application;

[0027] Figure 6 is a schematic diagram of a delay locked loop DLL according to an embodiment of the present application;

[0028] Figure 7 is a flowchart of a clock phase detection method according to an embodiment of the present application;

[0029] Figure 8 is a schematic diagram of an electronic device according to an embodiment of the present application. Detailed implementation manners

[0030] In order to enable those of ordinary skill in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0032] The clock phase detection circuit, method, delay locked loop, chip and electronic device of the embodiments of the present application will be described below with reference to the drawings.

[0033] Figure 1 is a schematic diagram of a clock phase detection circuit according to an embodiment of the present application.

[0034] As Figure 1As shown in the figure, the clock phase detection circuit 100 of the embodiment of the present application includes: a detection module 101, a frequency division module 102, and a clock driving module 103.

[0035] Among them, the frequency division module 102 is used to perform frequency division processing on the reference clock signal refclk_buf selected from multiple input clock signals clk[n:0] with the same frequency but different phases, and generate a frequency-divided clock signal refclk_div. The clock driving module 103 is used to group multiple input clock signals clk[n:0] with the same frequency but different phases, and generate at least two groups of input clock signals. The detection module 101 is respectively connected to the frequency division module 102 and the clock driving module 103. The detection module 101 is used to generate a detection signal based on the frequency-divided clock signal refclk_div and at least two groups of input clock signals according to the time interval between the reference clock signal refclk_buf and the feedback clock signal; wherein, the feedback clock signal is the input clock signal of the previous phase of the reference clock signal.

[0036] In this embodiment, the frequency division module 102 may be a three-frequency division module. Then, the three-frequency division module is used to perform three-frequency division processing on the reference clock signal refclk_buf, and generate a three-frequency divided clock signal refclk_div3.

[0037] In the following, multiple input clock signals clk[n:0] with the same frequency but different phases are exemplified by 10 input clock signals clk[9:0] with the same frequency but different phases.

[0038] The clock driving module 103 can group 10 input clock signals clk[9:0] with the same frequency but different phases, and generate a first group of input clock signals and a second group of input clock signals. Among them, the first group of input clock signals includes j input clock signals, such as the third-phase input clock signal dllclk[2], the sixth-phase input clock signal dllclk[5], and the ninth-phase input clock signal dllclk[8]; the second group of input clock signals includes k input clock signals, such as the third-phase input clock signal dllclk[2], the fifth-phase input clock signal dllclk[4], the seventh-phase input clock signal dllclk[6], and the ninth-phase input clock signal dllclk[8].

[0039] The detection module 101 is used for:

[0040] Based on the divided-frequency clock signal refclk_div and the first set of input clock signals, when it is detected that the time interval between the reference clock signal refclk_buf and the feedback clock signal is greater than N (such as 1.5) reference clock signal periods, it indicates that the feedback clock signal arrives with a delay relative to the reference clock signal refclk_buf, and there may be over-delay (i.e., the signal propagation speed is too slow), which may also cause logic timing violations. At this time, the generated detection signal is the voltage boost indication signal over;

[0041] Based on the first set of input clock signals and the second set of input clock signals, when it is detected that the time interval between the reference clock signal refclk_buf and the feedback clock signal is less than M (0.5) reference clock signal periods, it indicates that the feedback clock signal arrives earlier relative to the reference clock signal refclk_buf, and there may be under-delay (i.e., the signal propagation speed is too fast), which may cause logic timing violations. At this time, the generated detection signal is the voltage reduction indication signal under;

[0042] When it is detected that the time interval between the reference clock signal refclk_buf and the feedback clock signal is less than or equal to N (such as 1.5) reference clock signal periods and greater than or equal to M (0.5) reference clock signal periods, it indicates that there is no under-delay and over-delay. At this time, the generated detection signal is the voltage hold indication signal.

[0043] Assume that the frequency of the reference clock signal refclk_buf is 100 MHz (period is 10 ns), then:

[0044] The time interval less than 0.5 clock cycles: that is, less than 5 ns.

[0045] The time interval greater than 1.5 clock cycles: that is, greater than 15 ns.

[0046] In this case, if the feedback clock signal is advanced by more than 5 ns or delayed by more than 15 ns relative to the reference clock signal refclk_buf, the clock phase detection circuit 100 will detect this time difference and trigger the corresponding adjustment mechanism to ensure the stability and accuracy of the system clock.

[0047] Thus, the clock phase detection circuit according to the embodiments of the present application does not require an external high-frequency clock signal. By using multiple input clock signals with the same frequency but different phases, it can accurately detect the time interval between the input clock signal and the feedback clock signal. Specifically, when the time interval between the input clock signal and the feedback clock signal is less than 0.5 clock cycles or greater than 1.5 clock cycles, the clock phase detection circuit can accurately detect the time difference and quickly realize the detection of the clock phase. Since the clock phase detection circuit of the present application does not depend on an external high-frequency clock, the requirements for the external clock are relatively low, the clock structure is simple, and the complexity and cost of the system are reduced.

[0048] Figure 2 FIG. is a schematic diagram of a clock phase detection circuit according to another embodiment of the present application.

[0049] Among the embodiments of the present application, at least two groups of input clock signals include a first group of input clock signals and a second group of input clock signals. Hereinafter, at least two groups of input clock signals will be described by taking the first group of input clock signals and the second group of input clock signals as an example.

[0050] As Figure 2 shown, the detection module 101 includes: an over-delay detection unit 104 and an under-delay detection unit 106.

[0051] Among them, the over-delay detection unit 104 is configured to generate a detection signal as a voltage boost indication signal over based on the divided clock signal refclk_div and the first group of input clock signals in response to detecting that the time interval is greater than N reference clock signal periods; the under-delay detection unit 106 is configured to generate a detection signal as a voltage drop indication signal under based on the first group of input clock signals and the second group of input clock signals in response to detecting that the time interval is less than M reference clock signal periods; where N > M.

[0052] In this embodiment, the over-delay detection unit 104 is based on the divided clock signal refclk_div and the first group of input clock signals. When it detects that the time interval between the reference clock signal refclk_buf and the feedback clock signal is greater than N (such as 1.5) reference clock signal periods, it indicates that the feedback clock signal arrives with a delay relative to the reference clock signal, and there may be an over-delay, which may also cause a logic timing violation. At this time, the generated detection signal is a voltage boost indication signal over;

[0053] The under-delay detection unit 106 is based on the first set of input clock signals and the second set of input clock signals. When the time interval between the detected reference clock signal refclk_buf and the feedback clock signal is less than M (0.5) reference clock signal periods, it indicates that the feedback clock signal arrives earlier than the reference clock signal, and there may be an under-delay, which may lead to a logic timing violation. At this time, the generated detection signal is the voltage reduction indication signal under.

[0054] For the under-delay detection where the time interval between the reference clock signal refclk_buf and the feedback clock signal is less than M (0.5) reference clock signal periods, this application combines two different types of detection sub-units to achieve complementary circuit characteristics. As Figure 2 shown, the under-delay detection unit 106 includes: a low-frequency under-delay detection sub-unit 107, a high-frequency under-delay detection sub-unit 108, and a first OR gate 109.

[0055] Among them, the low-frequency under-delay detection sub-unit 107 is used to obtain a first comparison result based on the first set of input clock signals according to the magnitude relationship between the time interval and M reference clock signal periods when the frequency of the reference clock signal refclk_buf is less than the first set frequency; the high-frequency under-delay detection sub-unit 108 is used to obtain a second comparison result based on the second set of input clock signals according to the magnitude relationship between the time interval and M reference clock signal periods when the frequency of the reference clock signal refclk_buf is greater than the second set frequency; the first OR gate 109 is used to perform an OR operation on the first comparison result and the second comparison result to generate and output a detection signal characterizing that the time interval is less than M reference clock signal periods.

[0056] In an embodiment of this application, if the first comparison result is that the time interval is less than M reference clock signal periods, or the second comparison result is that the time interval is less than M reference clock signal periods, the detection signal generated by the first OR gate 109 is the voltage reduction indication signal over.

[0057] Figure 3 It is a schematic diagram of a low-frequency under-delay detection sub-unit according to an embodiment of this application.

[0058] It should be noted that, taking the j different-phase input clock signals in the first group of input clock signals as an example, which include the third-phase input clock signal dllclk[2], the sixth-phase input clock signal dllclk[5], and the ninth-phase input clock signal dllclk[8], and taking the j-stage cascaded second low-frequency under-delay detection flip-flops as an example, which include the second low-frequency under-delay detection flip-flop 122, the low-frequency under-delay detection flip-flop 123, the second low-frequency under-delay detection flip-flop 124, and the third low-frequency under-delay detection flip-flop 125, an explanation will be given.

[0059] As Figure 3 shown, the low-frequency under-delay detection subunit 107 of the embodiment of the present application includes: a first low-frequency under-delay detection flip-flop 121, a j-stage cascaded second low-frequency under-delay detection flip-flop, and a low-frequency under-delay detection synchronizer 126. The low-frequency under-delay detection subunit 107 is used to detect the scenario where the time interval between the input clock signal and the feedback clock signal is less than 0.5 input clock cycles, and is applicable to the scenario where the input clock frequency is relatively low. At the same time, using the third-phase input clock signal dllclk[2], the sixth-phase input clock signal dllclk[5], and the ninth-phase input clock signal dllclk[8] as clock signals can ensure that there is no misjudgment, and the adjacent clock time intervals are relatively sufficient to meet the setup time requirements of the flip-flops. In addition, the last stage is the low-frequency under-delay detection synchronizer 126, which completes half-beat timing convergence inside the low-frequency under-delay detection subunit 107 and releases the timing risk for external use.

[0060] Among them, the data output terminal Q of the first low-frequency under-delay detection flip-flop 121 is connected to the data input terminal D of the second low-frequency under-delay detection flip-flop 122, the data output terminal Q of the second low-frequency under-delay detection flip-flop 122 is connected to the data input terminal D of the second low-frequency under-delay detection flip-flop 123, the data output terminal Q of the second low-frequency under-delay detection flip-flop 123 is connected to the data input terminal D of the second low-frequency under-delay detection flip-flop 124, the data output terminal Q of the second low-frequency under-delay detection flip-flop 124 is connected to the data input terminal D of the third low-frequency under-delay detection flip-flop 125, and the data output terminal Q of the third low-frequency under-delay detection flip-flop 125 is connected to the data input terminal D of the low-frequency under-delay detection synchronizer 126;

[0061] The reference clock signal refclk_buf is transmitted to the clock terminals CP of the first low-frequency under-delay detection flip-flop 121 and the low-frequency under-delay detection synchronizer 126 for use as a clock;

[0062] The reference anti-clock signal refclkb_buf, which is opposite in phase to the reference clock signal refclk_buf, is transmitted to the data clear terminals CD of the first low-frequency under-delay detection flip-flop 121, the second low-frequency under-delay detection flip-flop 122, the second low-frequency under-delay detection flip-flop 123, and the second low-frequency under-delay detection flip-flop 124 for clearing the flip-flop data. Also, the reference anti-clock signal refclkb_buf, which is opposite in phase to the reference clock signal refclk_buf, is further transmitted to the clock terminal CP of the third low-frequency under-delay detection flip-flop 125 and used as a clock.

[0063] The third-phase input clock signal dllclk[2] is transmitted to the clock terminal CP of the second low-frequency under-delay detection flip-flop 122 and used as a clock.

[0064] The sixth-phase input clock signal dllclk[5] is transmitted to the clock terminal CP of the second low-frequency under-delay detection flip-flop 123 and used as a clock.

[0065] The ninth-phase input clock signal dllclk[8] is transmitted to the clock terminal CP of the second low-frequency under-delay detection flip-flop 124 and used as a clock.

[0066] The reset signal rst is transmitted to the data clear terminals CD of the third low-frequency under-delay detection flip-flop 125 and the low-frequency under-delay detection synchronizer 126, and at initialization, pulls down the outputs of the third low-frequency under-delay detection flip-flop 125 and the low-frequency under-delay detection synchronizer 126.

[0067] The low-frequency under-delay detection synchronizer 126 is used to generate and output a first comparison result.

[0068] Figure 4 It is a schematic diagram of a high-frequency under-delay detection subunit according to an embodiment of the present application.

[0069] It should be noted that the second group of input clock signals includes k input clock signals with different phases. Taking the third-phase input clock signal dllclk[2], the fifth-phase input clock signal dllclk[4], the seventh-phase input clock signal dllclk[6], and the ninth-phase input clock signal dllclk[8] as examples for illustration.

[0070] As Figure 4 shown, the high-frequency under-delay detection subunit 108 of the embodiment of the present application includes: a half-cycle high-frequency under-delay detection component 129, a full-cycle high-frequency under-delay detection component 130, and a second OR gate 137.

[0071] Among them, the half-cycle high-frequency under-delay detection component 129 uses the reference anti-clock signal refclkb_buf 120b as the clock signal, and uses the third-phase input clock signal dllclk[2], the fifth-phase input clock signal dllclk[4], the seventh-phase input clock signal dllclk[6], and the ninth-phase input clock signal dllclk[8] as input signals. It is used to determine whether the third-phase input clock signal dllclk[2], the fifth-phase input clock signal dllclk[4], the seventh-phase input clock signal dllclk[6], and the ninth-phase input clock signal dllclk[8] are all in the high-level state at the rising edge of the reference anti-clock signal refclkb_buf, and obtain the first determination result. For example, when they are all in the high-level state, the first determination result is a signal used to characterize the occurrence of under-delay, which is applicable to the situation where the high-level duty cycle of the clock is medium or large.

[0072] The full-cycle high-frequency under-delay detection component 130 uses the reference clock signal refclk_buf as the clock signal, and uses the third-phase input clock signal dllclk[2], the fifth-phase input clock signal dllclk[4], the seventh-phase input clock signal dllclk[6], and the ninth-phase input clock signal dllclk[8] as input signals. It is used to determine whether the third-phase input clock signal dllclk[2], the fifth-phase input clock signal dllclk[4], the seventh-phase input clock signal dllclk[6], and the ninth-phase input clock signal dllclk[8] are all in the low-level state at the rising edge of the reference clock signal refclk_buf, and obtain the second determination result. For example, when they are all in the low-level state, the first determination result is a signal used to characterize the occurrence of under-delay, which is applicable to the situation where the high-level duty cycle of the clock is medium or small.

[0073] The second OR gate 137 is used to perform an OR operation on the first determination result and the second determination result to obtain the second comparison result.

[0074] For example, if the first determination result is a signal used to characterize the occurrence of under-delay or the second determination result is a signal used to characterize the occurrence of under-delay, then the second comparison result generated by the second OR gate 137 is a signal used to characterize the occurrence of under-delay.

[0075] As Figure 4 shown, the half-cycle high-frequency under-delay detection component 129 of the embodiment of the present application includes: k / 2 NAND gates (such as including NAND gate 131a and NAND gate 131b), the first NOR gate 132, and the half-cycle detection flip-flop 133.

[0076] Among them, k input clock signals with different phases are divided into a third-phase input clock signal dllclk[2] and a fifth-phase input clock signal dllclk[4], as well as a seventh-phase input clock signal dllclk[6] and a ninth-phase input clock signal dllclk[8].

[0077] The third-phase input clock signal dllclk[2] and the fifth-phase input clock signal dllclk[4] are transmitted to the input terminals of the NAND gate 131a;

[0078] The seventh-phase input clock signal dllclk[6] and the ninth-phase input clock signal dllclk[8] are transmitted to the input terminals of the NAND gate 131b;

[0079] The reference anti-clock signal refclkb_buf is transmitted to the clock terminal of the half-cycle detection flip-flop 133;

[0080] The output terminals of the NAND gate 131a and the NAND gate 131b are connected to the input terminals of the first NOR gate 132;

[0081] The output terminal of the first NOR gate 132 is connected to the data input terminal D of the half-cycle detection flip-flop 133;

[0082] The data output terminal Q of the half-cycle detection flip-flop 133 is used to transmit the first determination result obtained by the half-cycle detection flip-flop 133 to the second OR gate 137.

[0083] As Figure 4 shown, the full-cycle high-frequency under-delay detection component 130 of the embodiment of the present application includes: k / 2 second NOR gates (such as including the second NOR gate 134a and the second NOR gate 134b), an AND gate 135, and a full-cycle detection flip-flop 136; among them,

[0084] The third-phase input clock signal dllclk[2] and the fifth-phase input clock signal dllclk[4] are transmitted to the input terminals of the NAND gate 134b;

[0085] The seventh-phase input clock signal dllclk[6] and the ninth-phase input clock signal dllclk[8] are transmitted to the input terminals of the second NOR gate 134a;

[0086] The reference clock signal refclk_buf is transmitted to the clock terminal of the full-cycle detection flip-flop 136;

[0087] The output terminals of the second NOR gate 134a and the second NOR gate 134b are connected to the input terminals of the AND gate 135;

[0088] The output terminal of the AND gate 135 is connected to the data input terminal D of the full-cycle detection flip-flop 136;

[0089] The data output terminal Q of the full-cycle detection flip-flop 136 is used to transmit the second judgment result obtained by the full-cycle detection flip-flop 136 to the second OR gate 137.

[0090] In the embodiment of the present application, the under-delay detection module 106 is used to detect the scenario where the time interval between the input clock signal and the feedback clock signal is less than 0.5 input clock cycles. By combining the low-frequency under-delay detection unit 107 based on the flip-flop chain and the high-frequency under-delay detection unit 108 based on combinational logic operations, the problem of misjudgment caused by the unsatisfied timing of the flip-flop chain at a high input clock frequency is solved. At the same time, the problem of misjudgment of the time interval caused by the level sensitivity of the combinational logic is also solved, broadening the applicable frequency range of the under-delay detection.

[0091] The low-frequency under-delay detection sub-unit 107 takes the edge-sensitive flip-flop chain as the core, triggers the under-delay detection at the rising edge of the input clock signal, triggers the under-delay result judgment at the falling edge, and reasonably optimizes the clock time interval between two adjacent flip-flops to ensure that the time interval is not less than 3 phase intervals, avoiding false detection. Through the above optimization, the applicable high-frequency upper limit is increased by 50%, further improving the performance of the system.

[0092] The high-frequency under-delay detection sub-unit 108 takes the level-sensitive combinational logic as the core and designs two high-frequency under-delay detection components. Among them, one triggers the under-delay detection at the rising edge of the input clock and triggers the under-delay result judgment at the falling edge; the other triggers the under-delay detection at the rising edge of the input clock and triggers the under-delay result judgment at the next rising edge. By converging the judgment results of the two circuits, the detection window covers the rising edge and the falling edge, greatly alleviating the constraint of the high-frequency under-delay detection circuit on the input clock duty cycle, and the duty cycle constraint is relaxed by about 2 times.

[0093] Through the above design, the applicable frequency upper limit is increased by more than one time, and missed detection or false detection is avoided, ensuring the stability and reliability of the system.

[0094] Figure 5 It is a schematic diagram of an over-delay detection unit according to an embodiment of the present application.

[0095] It should be noted that the following takes the second over-delay detection flip-flops in j-stage cascade, including the second over-delay detection flip-flop 114, the second over-delay detection flip-flop 115, and the second over-delay detection flip-flop 116 as an example for illustration.

[0096] Such as Figure 5As shown in the figure, the over-delay detection module 104 of the embodiment of the present application includes: a first over-delay detection flip-flop 113, a second over-delay detection flip-flop 114, a second over-delay detection flip-flop 115, a second over-delay detection flip-flop 116, a third over-delay detection flip-flop 117, an over-delay detection synchronizer 118, and an inverter 119, which are used to detect the scenario where the time interval between the reference clock signal and the feedback clock signal is greater than N reference clock signal periods, and generate a voltage boost indication signal over; the over-delay detection module 104 starts detection at the rising edge of the divided clock signal and completes detection and generates a detection signal at the falling edge of the divided clock signal, realizing the detection that the time interval between the reference clock signal refclk_buf and the feedback clock signal is greater than N clock periods, and selects the third-phase input clock signal dllclk[2], the sixth-phase input clock signal dllclk[5], and the ninth-phase input clock signal dllclk[8] as the input clock signals of each stage of the over-delay detection flip-flop. The time interval between adjacent clock signals is relatively large, and the over-delay detection module 104 can still work correctly when the frequency of the input clock signal is relatively high, supporting a relatively large frequency range.

[0097] Among them, the data output terminal Q of the first over-delay detection flip-flop 113 is connected to the data input terminal D of the second over-delay detection flip-flop 114, the data output terminal Q of the second over-delay detection flip-flop 114 is connected to the data input terminal D of the second over-delay detection flip-flop 115, the data output terminal Q of the second over-delay detection flip-flop 115 is connected to the data input terminal D of the second over-delay detection flip-flop 116, and the data output terminal Q of the second over-delay detection flip-flop 116 is connected to the data input terminal D of the third over-delay detection flip-flop 117;

[0098] The divided clock signal refclk_div is transmitted to the clock terminal of the first over-delay detection flip-flop 113 and used as a clock;

[0099] The divided anti-clock signal refclkb_div3, which is opposite in phase to the divided clock signal refclk_div, is respectively transmitted to the data clear terminals of the first over-delay detection flip-flop 113, the second over-delay detection flip-flop 114, the second over-delay detection flip-flop 115, and the second over-delay detection flip-flop 116 to clear the flip-flop data, and the divided anti-clock signal refclkb_div, which is opposite in phase to the divided clock signal refclk_div output by the dividing module 102, is also transmitted to the clock terminal of the third over-delay detection flip-flop 117 and used as a clock;

[0100] The third-phase input clock signal dllclk[2] is transmitted to the clock terminal of the second over-delay detection flip-flop 114 and used as a clock signal;

[0101] The sixth-phase input clock signal dllclk[5] is transmitted to the clock terminal of the second over-delay detection flip-flop 115 as a clock signal;

[0102] The ninth-phase input clock signal dllclk[8] is transmitted to the clock terminal of the second over-delay detection flip-flop 116 as a clock signal;

[0103] The reset signal rstn is respectively transmitted to the data set terminals of the third over-delay detection flip-flop 117 and the over-delay detection synchronizer 118. During initialization, the outputs of the third over-delay detection flip-flop 117 and the over-delay detection synchronizer 118 are pulled high;

[0104] The data output terminal Q of the over-delay detection synchronizer 118 is connected to the inverter 119;

[0105] The inverter 119 is used to generate and output a detection signal representing the size relationship between the time interval and the periods of N reference clock signals.

[0106] The over-delay detection circuit 104 of the embodiment of the present application adopts an architecture with a flip-flop chain as the core in the delay detection when the time interval is greater than 1.5 clock cycles. The specific working principle is as follows: The over-delay detection is triggered by the rising edge of the divided clock signal of the input clock signal, and the over-delay result judgment is triggered by the falling edge. The time interval between the input clock signals of adjacent two-stage flip-flops is reasonably optimized to ensure that the time interval is not less than 3 clock intervals, avoiding false detection. Through the above optimization, the applicable high-frequency upper limit is increased by 50%, significantly improving the performance and reliability of the system.

[0107] The clock phase detection circuit 100 of the embodiment of the present application can be applied in a delay-locked loop DLL, Figure 6 which is the architecture diagram of the clock phase detection circuit 100 of an embodiment of the present application applied in a delay-locked loop DLL.

[0108] As Figure 6 shown, the delay-locked loop DLL of the embodiment of the present application includes: a clock phase detection circuit 100, a phase detector 200, a charge pump 300, a voltage-current converter 400, a current-controlled delay circuit 500, and a phase selector 600.

[0109] Among them, the clock phase detection circuit 100 is used to generate and output detection signals over and under.

[0110] The phase detector 200 is used to receive the detection signals over and under and generate and output corresponding response signals up and down according to the detection signals over and under. Among them, up is used to indicate that the delay needs to be increased to reduce the time interval; down is used to indicate that the delay needs to be reduced to reduce the time interval.

[0111] A charge pump 300 is configured to generate a control voltage signal vctrl according to the output signals up and down of a phase detector 200 for adjusting an output voltage.

[0112] A voltage-current conversion module 400 is configured to convert the control voltage signal vctrl into a corresponding current signal ctk.

[0113] A current-controlled delay module 500 includes a plurality of delay units and is configured to adjust the delay duration of each delay unit according to the current signal ctk, and generate and output a plurality of input clock signals clk[n:0] with the same frequency but different phases.

[0114] A phase selection module 600 is configured to select and output an input clock signal with a corresponding phase from the plurality of input clock signals clk[n:0] with the same frequency but different phases according to an enable signal clk_en[n:0].

[0115] The main functions of the clock phase detection circuit 100 according to the embodiment of the present application include: when the time interval is less than 0.5 clock cycles or greater than 1.5 clock cycles, an indication signal of over or under is issued, which helps to timely detect the phase deviation between clock signals and ensure the timing accuracy of the system. Through the phase detector 200 and the charge pump 300, the clock phase detection circuit 100 can greatly adjust the delay time of the delay chain, and this adjustment can shorten the locking time required for the delay locked loop DLL to switch from the unlocked state to the locked state, so that the DLL has more time to stay in the locked state for frequency reduction defense.

[0116] In summary, for the clock phase detection circuit according to the embodiment of the present application, a reference clock signal selected from a plurality of input clock signals with the same frequency but different phases is frequency-divided by a frequency division module to generate a frequency-divided clock signal, and the plurality of input clock signals with the same frequency but different phases are grouped by a clock driving module to generate at least two groups of input clock signals. A detection signal is generated by a detection module based on the frequency-divided clock signal and the at least two groups of input clock signals according to the time interval between the reference clock signal and the feedback clock signal, where the feedback clock signal is the input clock signal of the previous phase of the reference clock signal. Thus, the present application can quickly implement the detection of the clock phase by using a plurality of input clock signals with the same frequency but different phases without introducing an additional clock source.

[0117] Based on the above embodiments, as Figure 6 shown, the present application further provides a delay locked loop, which includes the above-mentioned clock phase detection circuit 100.

[0118] As Figure 6As shown in the figure, the delay locked loop of the embodiment of the present application further includes: a phase detector 200, a charge pump 300, a voltage-current converter 400, a current-controlled delay circuit 500, and a phase selector 600.

[0119] Among them, the phase detector 200 is used to receive the detection signals over and under, and generate and output corresponding response signals up and down according to the detection signals over and under. Among them, up is used to indicate that the delay needs to be increased to reduce the time interval; down is used to indicate that the delay needs to be reduced to reduce the time interval.

[0120] The charge pump 300 is used to generate a control voltage signal vctrl according to the output signals up and down of the phase detector 200 to adjust the output voltage.

[0121] The voltage-current conversion module 400 is used to convert the control voltage signal vctrl into a corresponding current signal ctk.

[0122] The current-controlled delay module 500 is used to adjust the delay duration of the delay unit according to the current signal ctk to generate a plurality of input clock signals clk[n:0] with the same frequency but different phases.

[0123] The phase selection module 600 is used to select and output the input clock signal with the corresponding phase from the plurality of input clock signals clk[n:0] with the same frequency but different phases according to the enable signal clk_en[n:0].

[0124] It should be noted that for the details not disclosed in the delay locked loop of the embodiment of the present application, please refer to the details disclosed in the clock phase detection circuit 100 of the embodiment of the present application, which will not be elaborated here specifically.

[0125] The delay locked loop of the embodiment of the present application can stay in the locked state for more time through the use of the above-mentioned clock phase detection circuit to perform down-frequency defense.

[0126] Based on the above embodiment, the present application also proposes a chip, which includes the above-mentioned clock phase detection circuit.

[0127] In the embodiment of the present application, the chip can be an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA), etc.

[0128] Figure 7 It is a flowchart of the clock phase detection method according to the embodiment of the present application.

[0129] AsFigure 7 As shown in Figure 7 , the clock phase detection method according to the embodiment of the present application includes:

[0130] S1, performing frequency division processing on a reference clock signal selected from multiple input clock signals with the same frequency but different phases to generate a frequency-divided clock signal.

[0131] S2, performing grouping processing on multiple input clock signals with the same frequency but different phases to generate at least two groups of input clock signals.

[0132] S3, generating a detection signal based on the frequency-divided clock signal and at least two groups of input clock signals according to the time interval between the reference clock signal and the feedback clock signal; wherein, the feedback clock signal is the input clock signal of the previous phase of the reference clock signal.

[0133] In an embodiment of the present application, at least two groups of input clock signals include a first group of input clock signals and a second group of input clock signals;

[0134] Generating a detection signal based on the frequency-divided clock signal and at least two groups of input clock signals according to the time interval between the reference clock signal and the feedback clock signal includes:

[0135] Based on the frequency-divided clock signal and the first group of input clock signals, in response to detecting that the time interval is greater than N reference clock signal periods, the generated detection signal is a voltage boost indication signal;

[0136] Based on the first group of input clock signals and the second group of input clock signals, in response to detecting that the time interval is less than M reference clock signal periods, the generated detection signal is a voltage reduction indication signal; wherein, N > M.

[0137] In an embodiment of the present application, based on the first group of input clock signals and the second group of input clock signals, in response to detecting that the time interval is less than M reference clock signal periods, the generated detection signal is a voltage reduction indication signal, including:

[0138] In the case where the frequency of the reference clock signal is less than the first set frequency, based on the first group of input clock signals, obtaining a first comparison result according to the magnitude relationship between the time interval and M reference clock signal periods;

[0139] In the case where the frequency of the reference clock signal is greater than the second set frequency, based on the second group of input clock signals, obtaining a second comparison result according to the magnitude relationship between the time interval and M reference clock signal periods;

[0140] Performing an OR operation on the first comparison result and the second comparison result to generate and output a detection signal.

[0141] In one embodiment of the present application, based on the second set of input clock signals, a second comparison result is obtained according to the magnitude relationship between the time interval and the periods of M reference clock signals, including:

[0142] At the rising edge of the reference anti-clock signal, it is determined whether the third-phase input clock signal, the fifth-phase input clock signal, the seventh-phase input clock signal, and the ninth-phase input clock signal are all in the high-level state to obtain a first determination result;

[0143] At the rising edge of the reference clock signal, it is determined whether the third-phase input clock signal, the fifth-phase input clock signal, the seventh-phase input clock signal, and the ninth-phase input clock signal are all in the low-level state to obtain a second determination result;

[0144] The first determination result and the second determination result are subjected to an OR operation to obtain a second comparison result.

[0145] It should be noted that for the details not disclosed in the clock phase detection method of the embodiments of the present application, please refer to the details disclosed in the clock phase detection circuit of the embodiments of the present application, and will not be elaborated here specifically.

[0146] According to the clock phase detection method of the embodiments of the present application, the reference clock signal selected from multiple input clock signals with the same frequency but different phases is frequency-divided to generate a frequency-divided clock signal, and the multiple input clock signals with the same frequency but different phases are grouped to generate at least two sets of input clock signals. Then, based on the frequency-divided clock signal and at least two sets of input clock signals, a detection signal is generated according to the time interval between the reference clock signal and the feedback clock signal. The present application can quickly realize the detection of the clock phase by using multiple input clock signals with the same frequency but different phases without introducing an additional clock source.

[0147] To implement the above embodiments, the present application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the method described in the foregoing method embodiments is implemented.

[0148] Figure 8 It is a schematic structural diagram of an electronic device provided by the embodiments of the present application. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0149] Refer to Figure 8, the electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0150] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above-described method. Additionally, the processing component 802 may include one or more modules to facilitate interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

[0151] The memory 804 is configured to store various types of data to support the operation of the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0152] The power component 806 provides power to the various components of the electronic device 800. The power component 806 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the electronic device 800.

[0153] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of a touch or swipe action but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

[0154] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 further includes a speaker for outputting audio signals.

[0155] The I / O interface 812 provides an interface between the processing component 802 and a peripheral interface module, which can be a keyboard, a click wheel, buttons, etc. These buttons can include but are not limited to: a home button, a volume button, a power button, and a lock button.

[0156] The sensor component 814 includes one or more sensors for providing an assessment of the various aspects of the status of the electronic device 800. For example, the sensor component 814 can detect the on / off state of the electronic device 800, the relative positioning of components, such as the display and the keypad of the electronic device 800. The sensor component 814 can also detect a change in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor component 814 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 814 can also include a light sensor, such as a CMOS or a CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 814 can further include an acceleration sensor, a gyro sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0157] The communication component 816 is configured to facilitate communication between the electronic device 800 and other devices in a wired or wireless manner. The electronic device 800 can access a communication standard-based wireless network, such as WiFi, 4G, or 5G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0158] In an exemplary embodiment, the electronic device 800 can be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above method.

[0159] Based on the above embodiments, the present application proposes a non-transitory computer-readable storage medium.

[0160] Computer program instructions are stored on the non-transitory computer-readable storage medium of the embodiments of the present application, and when the computer program instructions are executed by a processor, the steps of the clock phase detection method as described above are implemented.

[0161] Based on the above embodiments, the present application proposes a computer program product.

[0162] The computer program product of the embodiments of the present application includes a computer program, and when the computer program is executed by a processor, the steps of the clock phase detection method as described above are implemented.

[0163] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without conflict, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0164] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0165] Any process or method description represented in a flowchart or described otherwise herein may be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logical function or process. The scope of the preferred embodiments of the present application includes additional implementations, where functions may be executed in a substantially simultaneous manner or in an order opposite to that shown or discussed, according to the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application pertain.

[0166] The logic and / or steps represented in a flowchart or described otherwise herein, for example, may be considered a sequenced list of executable instructions for implementing a logical function and may be embodied specifically in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection portion having one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, as the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0167] It should be understood that each part of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits with appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), and the like.

[0168] Those of ordinary skill in the art can understand that all or part of the steps carried by the methods in the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0169] In addition, in each embodiment of the present application, the functional units can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0170] The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

[0171] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present application. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the appended claims.

[0172] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A clock phase detection circuit, characterized in that: include: A frequency division module, used for performing frequency division processing on a reference clock signal selected from a plurality of input clock signals of the same frequency but different phases to generate a frequency-divided clock signal; A clock driving module, used for grouping the multiple input clock signals with the same frequency but different phases to generate at least two groups of input clock signals; A detection module, wherein the detection module is connected to the frequency division module and the clock driving module respectively, and the detection module is used to generate a detection signal based on the frequency division clock signal and the at least two groups of input clock signals and according to the time interval between the reference clock signal and the feedback clock signal; wherein the feedback clock signal is the input clock signal of the previous phase of the reference clock signal.

2. The clock phase detection circuit according to claim 1, characterized in that: The at least two groups of input clock signals include a first group of input clock signals and a second group of input clock signals; The detection module comprises: An over-delay detection unit, configured to generate the detection signal as a voltage rise indication signal in response to detecting that the time interval is greater than N reference clock signal cycles based on the divided clock signal and the first group of input clock signals; The under-delay detection unit is used to generate the detection signal as a voltage reduction indication signal based on the first group of input clock signals and the second group of input clock signals in response to detecting that the time interval is less than M reference clock signal cycles; wherein N>M.

3. The clock phase detection circuit according to claim 2, characterized in that: The under-delay detection unit comprises: A low-frequency under-delay detection subunit, configured to obtain a first comparison result based on the first group of input clock signals and according to a size relationship between the time interval and the M reference clock signal periods when the frequency of the reference clock signal is less than a first set frequency; a high-frequency under-delay detection subunit, configured to obtain a second comparison result based on the second group of input clock signals and according to a size relationship between the time interval and the M reference clock signal periods when the frequency of the reference clock signal is greater than a second set frequency; The first OR gate is used to perform an OR operation on the first comparison result and the second comparison result to generate and output a detection signal.

4. The clock phase detection circuit according to claim 3, characterized in that: The first group of input clock signals includes j input clock signals of different phases; The low-frequency under-delay detection subunit includes: a first low-frequency under-delay detection trigger, a j-stage cascaded second low-frequency under-delay detection trigger, a third low-frequency under-delay detection trigger and a low-frequency under-delay detection synchronizer; wherein, The data output terminal Q of the first low-frequency under-delay detection trigger is connected to the data input terminal D of the j-stage cascaded second low-frequency under-delay detection trigger, the data output terminal Q of the j-stage cascaded second low-frequency under-delay detection trigger is connected to the data input terminal D of the third low-frequency under-delay detection trigger, and the data output terminal Q of the third low-frequency under-delay detection trigger is connected to the data input terminal D of the low-frequency under-delay detection synchronizer; The reference clock signal is transmitted to the first low-frequency under-delay detection trigger and the clock terminal CP of the low-frequency under-delay detection synchronizer; A reference anti-clock signal having a phase opposite to that of the reference clock signal is transmitted to the data clearing terminal CD of the first low-frequency under-delay detection trigger, the j-stage cascaded second low-frequency under-delay detection trigger, and the clock terminal CP of the third low-frequency under-delay detection trigger; j input clock signals with different phases in the first group of input clock signals are transmitted to the clock terminals CP of the corresponding second low-frequency under-delay detection triggers in the j-stage cascaded second low-frequency under-delay detection triggers; A reset signal is transmitted to the third low-frequency under-delay detection trigger and the data clearing terminal CD of the low-frequency under-delay detection synchronizer; The low-frequency under-delay detection synchronizer is used to generate and output a first comparison result.

5. The clock phase detection circuit according to claim 3, characterized in that: The second group of input clock signals includes k input clock signals with different phases; The high-frequency under-delay detection subunit includes: a half-cycle high-frequency under-delay detection component, a full-cycle high-frequency under-delay detection component and a second OR gate; wherein, The half-cycle high-frequency under-delay detection component is used to determine whether all of the k input clock signals of different phases in the second group of input clock signals are in a high-level state at the rising edge of the reference inverse clock signal to obtain a first determination result; The full-cycle high-frequency under-delay detection component is used to determine whether all of the k input clock signals of different phases in the second group of input clock signals are in a low-level state at the rising edge of the reference clock signal, and obtain a second determination result; The second OR gate is used to perform an OR operation on the first determination result and the second determination result to obtain the second comparison result.

6. The clock phase detection circuit according to claim 5, characterized in that: The half-cycle high-frequency under-delay detection component includes: k / 2 NAND gates, a first NOR gate and a half-cycle detection trigger; wherein, Dividing the k input clock signals of different phases in the second group of input clock signals into k / 2 groups, and transmitting them to the input ends of the corresponding NAND gates in the k / 2 NAND gates respectively; The reference inverse clock signal is transmitted to the clock terminal of the half-cycle detection trigger; The output end of each of the k / 2 NAND gates is connected to the input end of the first NOR gate; The output end of the first NOR gate is connected to the data input end D of the half-cycle detection trigger; The data output terminal Q of the half-cycle detection trigger is used to transmit the first determination result obtained by the half-cycle detection trigger to the second OR gate.

7. The clock phase detection circuit according to claim 5, characterized in that: The full-cycle high-frequency under-delay detection component includes: k / 2 second NOR gates, an AND gate and a full-cycle detection trigger; wherein, Dividing the k input clock signals of different phases in the second group of input clock signals into k / 2 groups, and transmitting them to the input ends of the corresponding NOR gates in the k / 2 second NOR gates respectively; The reference clock signal is transmitted to the clock terminal of the full-cycle detection trigger; The output end of each of the k / 2 second NOR gates is connected to the input end of the AND gate; The output end of the AND gate is connected to the data input end D of the full-cycle detection trigger; The data output terminal Q of the full-cycle detection trigger is used to transmit the second judgment result obtained by the full-cycle detection trigger to the second OR gate.

8. The clock phase detection circuit according to claim 2, characterized in that: The over-delay detection module includes: a first over-delay detection trigger, a j-stage cascaded second over-delay detection trigger, a third over-delay detection trigger, an over-delay detection synchronizer and an inverter; wherein, The data output terminal Q of the first over-delay detection trigger is connected to the data input terminal D of the j-stage cascaded second over-delay detection trigger, and the data output terminal Q of the j-stage cascaded second over-delay detection trigger is connected to the data input terminal D of the third over-delay detection trigger; The divided clock signal is transmitted to the clock terminal CP of the first over-delay detection trigger; The divided anti-clock signal with a phase opposite to that of the divided clock signal is transmitted to the first over-delay detection trigger, the data clearing terminal CD of the j-stage cascaded second over-delay detection trigger, and the clock terminal CP of the third over-delay detection trigger respectively; j input clock signals of different phases in the first group of input clock signals are transmitted to the clock terminals CP of corresponding second over-delay detection triggers in j-stage cascaded second over-delay detection triggers; A reset signal is transmitted to the third over-delay detection trigger and the data setting terminal SDN of the over-delay detection synchronizer respectively; The data output terminal Q of the over-delay detection synchronizer is connected to the input terminal of the inverter; The inverter is used to generate and output a detection signal representing the magnitude relationship between the time interval and the N reference clock signal cycles.

9. A delay-locked loop, characterized in that: include: A clock phase detection circuit as claimed in any one of claims 1 to 8.

10. The delay locked loop according to claim 9, characterized in that: The delay phase-locked loop also includes: a phase detector, a charge pump, a voltage-current converter, a current control delay circuit and a phase selector; wherein, The phase detector is used to receive the detection signal, and generate and output a response signal according to the detection signal; The charge pump is used to receive the response signal, and generate and output a control voltage signal according to the response signal; The voltage-current conversion module is used to convert the control voltage signal into a corresponding current signal; The current-controlled delay module includes a plurality of delay units, which are used to adjust the delay time of each delay unit according to the current signal, and generate and output a plurality of input clock signals with the same frequency but different phases; The phase selection module is used to select and output an input clock signal of a corresponding phase from the multiple input clock signals of the same frequency but different phases according to an enable signal.

11. A chip, characterized in that: include: A clock phase detection circuit as claimed in any one of claims 1 to 8.

12. A clock phase detection method, characterized in that: include: Performing frequency division processing on a reference clock signal selected from a plurality of input clock signals of the same frequency but different phases to generate a frequency-divided clock signal; Performing group processing on the multiple input clock signals with the same frequency but different phases to generate at least two groups of input clock signals; Based on the divided clock signal and the at least two groups of input clock signals, a detection signal is generated according to the time interval between the reference clock signal and the feedback clock signal; wherein the feedback clock signal is an input clock signal of a previous phase of the reference clock signal.

13. The clock phase detection method according to claim 12, characterized in that: The at least two groups of input clock signals include a first group of input clock signals and a second group of input clock signals; The generating a detection signal based on the divided clock signal and the at least two groups of input clock signals according to the time interval between the reference clock signal and the feedback clock signal comprises: Based on the divided clock signal and the first group of input clock signals, in response to detecting that the time interval is greater than N reference clock signal cycles, the generated detection signal is a voltage rise indication signal; Based on the first group of input clock signals and the second group of input clock signals, in response to detecting that the time interval is less than M reference clock signal cycles, the generated detection signal is a voltage reduction indication signal; wherein N>M.

14. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the clock phase detection method according to claim 12 or 13 is implemented.

15. A non-transitory computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the steps of the clock phase detection method according to claim 12 or 13 are implemented.

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