Topcon battery and preparation method thereof

Abstract

The topcon battery comprises an n-type silicon substrate, and a P-type emitting electrode, a first tunneling oxide layer, a local POLY layer, a first aluminum oxide passivation layer, a first silicon oxide layer, a first silicon oxynitride layer, a silicon nitride anti-reflection layer and a first silk-screen printing layer are sequentially arranged on the front face of the n-type silicon substrate. And a second tunneling oxide layer, a POLY layer, a second aluminum oxide passivation layer, a second silicon dioxide layer, a second silicon oxynitride layer, a third silicon nitride layer and a second silk-screen printing layer are sequentially arranged on the back surface. According to the invention, optimization is carried out by adopting a film layer superposition passivation principle, and the TOPCon efficiency and reliability are improved.

Description

Technical Field

[0001] The present invention belongs to the field of solar cells, and particularly relates to a topco's n-type battery and a preparation method thereof. Background Art

[0002] As the mainstream product TOPCon battery in the current photovoltaic power generation market, it has greatly reduced the electrical losses of conventional batteries and improved the battery power. However, there is still a large room for improvement in the power improvement of the core technologies POLY layer, ALD, and coating technology of TOPCon batteries. The preparation technology of the new film layer structure TOPCon battery mainly optimizes the POLY passivation, alumina passivation, and back film passivation structures, bringing higher power output and better reliability. This technology changes the passivation effect of traditional TOPCon batteries. On the basis of the original TOPCon process, through laser masking technology on the front side, selective increase of front POLY passivation is achieved. Under the original alumina layer passivation, the POLY passivation effect is increased, reducing the metal recombination caused by paste burn-through. At the same time, the passivation effect on the front side is improved, making the light absorption coefficient stronger, better improving the conversion efficiency. At the same time, on the back side, alumina passivation and back side silicon oxynitride passivation layer are added to improve the back side passivation effect, enhance the denseness of the back side film layer, increase the passivation effect, and promote the reaction of the battery chip to generate silicon oxide and silicon oxynitride films. On the back side, nitrous oxide reaction is used to generate a silicon oxynitride layer film. By making good use of the strong denseness characteristics of the POLY layer, alumina passivation layer, and silicon oxynitride film, the new film layer effectively shields metal ions, and when stacked with the silicon nitride film, it can achieve a good anti-PID effect. At the same time, the extinction coefficients of the POLY layer, alumina, and silicon oxynitride are low, and the refractive index is controllable within a certain range. By controlling the film layer stacking, a better optical response can be achieved. Contents of the Invention In view of this, the present invention aims to propose a topcon battery and a preparation method thereof to solve at least one technical problem in the background art.

[0004] This application adds laser flooding film technology on the front side to selectively passivate the POLY layer on the basis of the original TOPCon process, solves the influence of front side metal recombination, and adds alumina, silicon oxynitride, and annealing on the back side to enhance the passivation effect. While improving the efficiency, it also synchronously improves the PID problem caused by the back side passivation, ensuring the product stability and efficiency, and promoting the rapid innovation of TOPCon technology.

[0005] To achieve the above object, the technical solution of the present invention is realized as follows: A topcon battery includes an n-type silicon substrate, and a P-type emitter, a first tunneling oxide layer, a local POLY layer, a first alumina passivation layer, a first silicon oxide layer, a first silicon oxynitride layer, a silicon nitride antireflection layer, and a first screen printing layer are sequentially arranged on the front side of the n-type silicon substrate; On the back side, a second tunneling oxide layer, a POLY layer, a second aluminum oxide passivation layer, a second silicon oxide layer, a second silicon oxynitride layer, a third silicon nitride layer, and a second screen printing layer are sequentially provided.

[0006] Furthermore, the thicknesses of both the first tunneling oxide layer and the second tunneling oxide layer are 1.4 - 1.6 nm.

[0007] The thickness of the silicon nitride antireflection layer is 3 - 10 nm; The thickness of the first silicon oxynitride film is 70 - 90 nm.

[0008] A preparation method of a topcon cell includes the following steps: S1: Texturing the silicon wafer; S2: Boron diffusion to form a phosphorus-doped polysilicon layer and a borosilicate glass layer, and the phosphorus-doped polysilicon layer and the borosilicate glass layer are diffused around the back side edge, Use HF to remove the borosilicate glass around the back side edge and at the edge, Alkaline polishing on the back side to remove the phosphorus-doped polysilicon layer around the edge and on the back side, forming a P-type emitter; S3: Perform back side deposition to form a first tunneling oxide layer and a second tunneling oxide layer; S4: Phosphorus diffusion to dope phosphorus into the back side polysilicon, forming a phosphosilicate glass layer, a locally phosphorus-doped polysilicon layer, and a phosphorus-doped polysilicon layer; S5: Use HF to remove the phosphosilicate glass layer on the front side and at the edge; S6: Laser masking; S7: Perform RCA cleaning to remove the phosphorus-doped polysilicon layer on the front side and at the edge, and the polysilicon layer and the borosilicate glass layer on the front side; S8: Respectively form a first aluminum oxide passivation layer and a second aluminum oxide passivation layer on the boron diffusion surface and the front side passivation; S9: Single-sided annealing to form a first silicon oxide layer on the back side of the cell and a second silicon oxide layer on the front side of the cell; S10: After back side passivation, form a second silicon oxynitride layer on the back side of the cell; Form a first silicon oxynitride layer on the front side of the cell; Back side deposition, form a silicon nitride antireflection layer on the front side and a third silicon nitride layer on the back side; S11: Screen printing and sintering to form a first screen printing layer and a second screen printing layer.

[0009] Furthermore, the texturing in step S1 is carried out in a tank-type cleaning equipment; The temperature of texturing is 75 - 85 °C, the time is 4 - 6 min, and the thinning amount of the silicon wafer is 0.36 - 0.42 g.

[0010] Further, in step S2, the boron diffusion includes introducing O at a temperature of 860 - 880 °C, a furnace tube pressure of 90 - 110 mbar, and introducing 2900 - 3100 sccm of O 2 , introducing for a time of 170 - 190 s to form a polysilicon layer; then introducing 2000 sccm of N 2 to purge for 0.5 - 1.5 min, and then introducing 190 - 210 sccm of BCL 3 , 600 - 700 sccm of O 2 , 3900 - 4100 sccm of N 2 , introducing for a time of 600 - 800 s for boron diffusion deposition, and then introducing 2400 - 2600 sccm of N 2 to purge for 0.5 - 1.5 min, heating up to 900 - 1000 °C, with a furnace tube pressure of 400 - 500 mbar, and introducing 3900 - 4100 sccm of N 2 , introducing for a time of 500 - 600 s, heating up to 1000 - 1100 °C, with a furnace tube pressure of 200 - 400 mbar, and introducing 9000 - 11000 sccm of O 2 , introducing for a time of 4500 - 4700 s to form a phosphorus - doped polysilicon layer and a back - side edge over - diffusion of a borosilicate glass layer, forming a sheet resistance of 250 - 350 Ω / sq; In step S2, HF is used to remove the back - side edge over - diffusion and the borosilicate glass at the edge. Chain cleaning and polishing are carried out in a tank - type cleaning equipment, and the cleaning liquid of the tank - type cleaning equipment is KOH; The cleaning temperature is 60 - 70 °C, the time is 210 - 230 s, and the thinning amount of the silicon wafer is 0.1 - 0.3 g; Back - side alkaline polishing is carried out in a tank - type cleaning equipment, and the cleaning liquid of the tank - type cleaning equipment is KOH; the cleaning temperature is 60 - 70 °C, the time is 210 - 230 s, and the thinning amount of the silicon wafer is 0.1 - 0.3 g.

[0011] Further, the back - side deposition of the polished silicon wafer in step S3 includes oxidizing at a temperature above 600 °C, introducing 35000 - 37000 sccm of O 2 , for a time of 470 - 490 s, evacuating, purging oxygen, and then introducing 800 - 1000 sccm of silane, with a reaction time of 1500 - 1700 s and a pressure of 250 - 350 mbar; The thicknesses of both the first tunneling oxide layer and the second tunneling oxide layer are 1.4 - 1.6 nm.

[0012] Further, in step S4, the phosphorus diffusion includes forming a phosphosilicate glass layer and a phosphorus-doped polysilicon layer by means of thermal diffusion through a tube furnace tube. At a temperature of 900 - 940 °C, 850 - 900 sccm of PClO 3 gas is introduced, the oxygen flow rate is 700 - 900 sccm, and the time is 50 - 70 min.

[0013] Further, in step S8, trimethylaluminum and water are introduced into the furnace tube to form a first aluminum oxide passivation layer and a second aluminum oxide passivation layer with a thickness of 5 - 10 nm.

[0014] In step S9, the annealing temperature is 480 °C, 800 - 1000 sccm of silane, 7000 - 9000 nitrous oxide are introduced, the pressure is 1800 - 2000 mbar, the radio frequency power is 13000 - 14000 W, the duty cycle is 15 to 500, and the reaction time is 60 - 80 s, respectively forming a 1 - 3 nm first silicon oxide layer and a 1 - 3 nm second silicon oxide layer.

[0015] Further, in step S10, forming a second silicon oxynitride layer on the back side includes using a graphite boat as a carrier, placing the cell annealed in step S9 into the furnace tube, and introducing 1100 - 1300 sccm of silane, 5100 - 5300 sccm of ammonia, and 7300 - 7500 sccm of nitrous oxide at a temperature of 500 °C, with a pressure of 1500 - 1700 mbar, a radio frequency power of 230000 - 250000 W, and a duty cycle of 50:1200 - 1300; the reaction time is 260 - 280 s to form a second silicon oxynitride film on the back side of the cell; Raise the temperature. When the temperature reaches 510 °C, introduce 2800 sccm of silane, 10000 sccm of ammonia, with a pressure of 1600 mbar, a radio frequency power of 240000 W, and a duty cycle of 50 to 1000. The reaction time is 605 s to form a first silicon nitride film on the back side of the cell.

[0016] The thickness of the second silicon oxynitride film is 70 - 90 nm; The thickness of the second silicon nitride film is 1 - 5 nm.

[0017] Further, on the front side of the cell in step S10, at a temperature of 500 °C, introduce 800 - 1000 sccm of silane, 2800 - 3200 sccm of ammonia, 7500 - 8500 sccm of nitrous oxide, with a pressure of 1800 - 2000 mbar, a radio frequency power of 12000 - 14000 W, a duty cycle of 15 to 500, and a reaction time of 260 - 280 s to form a 35 - 45 nm first silicon oxynitride film; Heat up to a temperature of 510 °C, introduce 1700 - 1900 sccm of silane, 6200 - 6400 sccm of ammonia, with a pressure of 1800 - 2000 mbar, a radio frequency power of 11000 - 12000 W, a duty cycle of 30 to 500, and a reaction time of 700 - 900 s to form a first silicon nitride film with a thickness of 1 - 5 nm.

[0018] Compared with the prior art, a topcon battery and its preparation method according to the present invention have the following advantages: 1. The tunneling oxide layer passivation contact provided in this application enables electrons to tunnel into the doped polysilicon layer while blocking holes, reducing the metal contact recombination current. The electrons that enter the doped polysilicon layer are longitudinally transported and collected by the back full-contact metal. Therefore, this structure has carrier selectivity. 2. AL 2 O 3 mainly has two characteristics, field passivation and chemical passivation, to provide a passivation effect for the battery: Utilizing the negative charge characteristic of AL 2 O 3 , an interfacial electric field pointing into the silicon wafer is generated at the AL 2 O 3 / Si interface, enabling carriers to quickly escape from the interface, reducing the interface recombination rate, and increasing the minority carrier lifetime. 3. The Si x O y film prepared by the nitrous oxide process. Nitrous oxide and silane are activated by physical action through radio frequency discharge to generate plasma for chemical deposition. A large amount of hydrogen will be generated during the process, and the hydrogen will migrate through energy to repair the defects and dangling bonds of the silicon substrate, reducing recombination and increasing efficiency. 4. The SiOxNy film prepared by the nitrous oxide process is obtained by plasma-enhanced chemical vapor deposition of nitrous oxide, silane, and ammonia. The passivation performance of the battery cell is a prerequisite for the PID performance of the module. The silicon oxynitride (SiOxNy) film is an intermediate phase between silicon dioxide and silicon nitride and has excellent passivation and antireflection characteristics. By changing the composition ratio, its refractive index can be adjusted within a certain range (1.45 - 2.3), enabling the SiON film to have antireflection performance; at the same time, SiON also contains a large number of hydrogen atoms, which can achieve a good passivation effect; the silicon oxynitride film has good compactness and strong shielding ability for metal ions, and superimposing it with the silicon nitride film can achieve a good anti-PID effect.

[0019] 5. Based on optical and electrical principles, and according to physical characteristics, this application prepares a controllability that matches the passivation effect, makes the film layers complement each other's advantages and avoid their disadvantages, and achieves a better film layer structure. This application adopts the principle of film layer superposition passivation for optimization, improving the efficiency and reliability of TOPCon.

[0020] 6. This application upgrades the traditional process, achieving a simple backside POLY, frontside alumina passivation, and frontside silicon oxynitride for solar cell products, and updating to a double-sided POLY layer, double-sided alumina passivation stacked with double-sided silicon oxynitride passivation, reducing the refractive index of light, increasing the short-circuit current of the solar cell, and achieving a good passivation effect; the silicon oxynitride film has good compactness and strong shielding ability for metal ions, and stacking with the silicon nitride film can achieve a good anti-PID effect. The double-sided POLY layer passivation can well activate the electron transport speed and avoid the frontside silver paste from penetrating the alumina layer and damaging the silicon bottom P-type emitter, reducing the influence of metal recombination, and achieving the purpose of improving efficiency and PID. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings constituting a part of this invention are used to provide a further understanding of the invention. The schematic embodiments and descriptions thereof of the invention are used to explain the invention and do not unduly limit the invention. In the drawings: Figure 1 is a schematic structural diagram of a topcon battery according to an embodiment of the invention; Figure 2 is a schematic diagram according to an embodiment of the invention. BRIEF DESCRIPTION OF THE DRAWINGS: n-type silicon bottom; 2. P-type emitter; 3. First tunneling oxide layer; 4. Local POLY layer; 5. First alumina passivation layer; 6. First silicon oxide layer; 7. First silicon oxynitride layer; 8. Silicon nitride antireflection layer; 9. First screen printing layer; 10. Second tunneling oxide layer; 11. POLY layer; 12. Second alumina passivation layer; 13. Second silicon oxide layer; 14. Second silicon oxynitride layer; 15. Third silicon nitride layer; 16. Second screen printing layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0024] The following will refer to the drawings and combine with embodiments to detail the present invention.

[0025] The preparation technology of the new film layer structure TOPCon battery includes the following steps: Step 1: Frontside local POLY; POLY deposits an ultra-thin oxide layer on the backside of the silicon wafer to provide good interface passivation, and at the same time provides different carrier tunneling barriers. A layer of amorphous silicon is deposited on the oxide layer to increase the electron migration rate and inhibit the hole migration rate (forming band bending and heterojunction contact). In addition, the amorphous silicon contacts the metal and acts as an electron transport bridge.

[0026] POLY layer deposition principle: Oxygen is introduced at high temperature. Oxygen reacts with silicon to produce silicon oxide. Reaction equation: O2 + Si SiOx; Principle of n-type polysilicon film: Silane is introduced at high temperature. Silane thermally decomposes into silicon and hydrogen. Reaction equation: SiH 4 (gas) = Si (solid) + H 2 Step 2: The laser masking technology is to spray wax selectively on the front side through the laser wax spraying method to prevent the front POLY layer from being washed away, so as to retain the POLY layer in the local area, increase the passivation effect, and reduce the metal composite affected by the subsequent paste sintering penetration. Step 3: Alumina passivation technology, that is, passivated emitter rear contact. Use Al 2 O 3 To form a passivation layer on the back of the battery as a back reflector, increasing the absorption of long waves and the passivation effect. After the back is passivated, the recombination rate of photo-generated carriers on the back will drop significantly, and the minority carrier lifetime will increase greatly, thereby improving the efficiency. In this project, a layer of Al 2 O 3 Passivation film layer is deposited on the back of the battery cell through an ALD device.

[0027] Step 4: Annealing During the battery manufacturing process, the silicon wafer with the formed p-n junction is placed in a high-temperature furnace and reacts with an oxidant at high temperature to grow a layer of SiO 2 Film, which plays a passivation role on the surface of the solar cell. The SiO 2 Film prepared by the thermal oxidation method, due to the presence of a large number of fixed positive charges in the thermally oxidized silicon dioxide, these fixed positive charges will produce a field effect passivation effect, reducing the defect density on the surface of the silicon wafer and obtaining a low surface recombination rate.

[0028] Step 5: Back passivation film After the back is passivated, a silicon oxynitride and silicon nitride antireflection film are sequentially deposited on the alumina film layer. The preparation of silicon oxynitride mainly adds an N 2 O pipeline in the furnace tube, adding a 1-5nm silicon oxynitride film on the conventional back passivation layer alumina thin film to ensure that the total film thickness on the back is 80-110nm for double-sided cells / 130-160nm for single-sided cells, and adding a 3-10nm silicon oxynitride film on the front bottom film to ensure that the total film thickness on the front is 62-82nm, forming a positive film coating (nitrous oxide) silicon oxynitride - silicon nitride film, reducing the front reflectivity can achieve a good passivation effect; the silicon oxynitride film has good compactness and strong shielding ability for metal ions, and superimposing with the silicon nitride film can play a good anti-PID effect; Principle formula: SiH 4+NH 3 +N 2 O → SiyONx + H 2 SiH 4 +NH 3 → SixNyHz Specifically, in step 1, single insertion is required to ensure double-sided coating. In step 2, a laser machine needs to be added to perform laser flooding to ensure that the front POLY layer is not washed away. In step 3, the ALD equipment needs to perform single insertion to ensure that an aluminum oxide passivation layer can be deposited on both sides. In step 4, N 2 O supply is increased in the back coating tube P machine to prepare silicon oxide and silicon oxynitride thin films.

[0029] Example 1: The preparation technology of the new film layer structure TOPCon battery includes the following steps: 1. Texturing Utilizing the anisotropic etching characteristics of silicon in low-concentration alkaline solution, after etching for a certain time, a "pyramid" structure as shown in the following figure is formed on the surface of the monocrystalline silicon wafer. Silicon can react with the sodium hydroxide solution to generate sodium silicate and release hydrogen. The chemical reaction is: Si + 2NaOH + H 2 O = Na 2 SiO 3 + 2H 2 ↑ A trough-type cleaning equipment is adopted. During cleaning, NaOH and additives are used, the temperature is maintained at 80 °C, the time is 5 min, and the weight reduction of the battery wafer is controlled within 0.36 - 0.42 g 2. Boron diffusion Junction formation is to generate diffusion layers of different conductive types on the substrate material to form a P-N junction. The thermal diffusion method adopted in this project. In the diffusion process of the silicon wafer, boron trichloride and oxygen are used. Under high-temperature diffusion conditions, boron trichloride and oxygen react to generate 2B 2 O 3 + 6Cl 2 , and the generated 2B 2 O 3 reacts with silicon to generate 3SiO 2 + 4B to form a P-type junction on the surface, completing the diffusion junction formation process with the N-type silicon substrate and realizing the conversion of light energy to electrical energy.

[0030] The furnace tube temperature is raised to 870 °C, the furnace tube pressure is 100 mbar, 3000 sccm of O 2 is introduced, and the introduction time is 180 s to form an oxide layer. Subsequently, 2000 sccm of N 2Purge for 1 min, maintain the furnace tube temperature at 870 °C, the furnace tube pressure at 100 mbar, and introduce 200 sccm of BCL 3 , 650 sccm of O 2 , 4000 sccm of N 2 , introduce for 700 s for boron diffusion deposition, then introduce 2500 sccm of N 2 Purge for 1 min 3, heat up to 950 °C, the furnace tube pressure is 300 mbar, and introduce 4000 sccm of N 2 , introduce for 550 s to further push the boron atoms in the BsG layer into the silicon substrate. Heat up to 1040 °C, the furnace tube pressure is 300 mbar, and introduce 10000 sccm of O 2 , introduce for 4600 s to form an oxide layer and a BsG layer. Finally, phosphorus diffuses into the N-type silicon wafer to form a sheet resistance of 250 - 350 Ω / sq. Remove BsG and back polish: Remove all the borosilicate glass on the back surface and the edge diffusion area of the N-type polycrystalline silicon substrate, then remove the P+ doped layer on the back surface and the edge of the N-type crystalline silicon, and only retain the P+ doped layer on the front surface; Use a chain cleaner for BsG and use an HF solution to remove the BsG on the edge and surface. Use a tank-type equipment for polishing, with a KOH and additive solution at a temperature of 65 °C for 220 s, and control the thinning amount of the solar cell to 0.1 - 0.3 g.

[0031] 3. poly (single insertion) POLY layer deposition principle: Pass oxygen at high temperature, and oxygen reacts with silicon to produce silicon oxide. The reaction equation is: O 2 + Si SiO x n-type polysilicon film principle: Pass silane at high temperature, and silane thermally decomposes into silicon and hydrogen. The reaction equation is: SiH 4 (gas) = Si (solid) + H 2 Deposit an ultra-thin tunneling oxide layer and an amorphous silicon layer on the back of the polished silicon substrate through an LPCVD equipment. The thickness of the tunneling oxide layer is about 1.5 nm, and the thickness of the amorphous silicon layer is 115 nm - 160 nm.

[0032] 1) Raise the temperature in the diffusion furnace tube above 600 °C, introduce 36000 sccm of oxygen into the tube for 480 s for oxidation. 2) Evacuate and clean the oxygen in the furnace tube. 3) Introduce 900 sccm of silane into the furnace tube for a reaction time of 1600 s, and the furnace tube pressure is 300 mbar. Form a POLY layer.

[0033] 4. Backside phosphorus diffusion POCl 3 Decomposes at high temperature (>600 °C) to generate phosphorus pentachloride (PCl5 ), and phosphorus pentoxide (P 2 O 5 ), and the reaction formula is as follows: 5POCl 3 → high temperature (>600 °C) → 3PCl 5 + P 2 0 5 4PCl 5 + 5O 2 --- excess O 2 → 2P 2 0 5 + 10Cl 2 By means of thermal diffusion through a tubular furnace tube, a phosphorus-doped polysilicon layer is formed: at a temperature of 920 °C, PClO 3 gas is introduced at a flow rate of 870 sccm, the oxygen flow rate is 800 sccm, and the process time is 60 min; Remove PsG Use the HF etching process to clean and remove the residual phosphosilicate glass on the surface and edges of the silicon wafer; 6. Laser masking The local area of the electrode position is protected by spraying wax through a laser machine. The line width of the wax protection layer is wider than that of the Ag grid line. The POLY layer at the electrode position is retained and will not be etched off in the subsequent cleaning operation, and the other positions are polished normally on the front side.

[0034] 7. RCA positive etching In a trough machine, the reaction of chemicals with POLY silicon achieves the front-side polishing effect, and at the same time, the local protection of the laser masking technology is used to retain the tunneling oxide layer at the local position.

[0035] 8. Preparation of ALD (single insertion) double-sided aluminum oxide The raw material for preparing Al 2 O 3 is TMA (trimethylaluminum), and the reaction equation is 2AL(CH 3 ) 3 + 3H 2 O = Al 2 O 3 + 6CH 4 ; TMA and water are introduced into the furnace tube for 30 cycles to form a first aluminum oxide passivation layer and a second aluminum oxide passivation layer with a thickness of 5 - 10 nm.

[0036] 9. Annealing (single side) Place the silicon wafer in a reaction tube made of quartz glass. The reaction tube is heated to a certain temperature by a resistance wire heating furnace (the commonly used temperature is 900 - 1200 °C, and it can be reduced to below 600 °C under special conditions). When oxygen passes through the reaction tube, a chemical reaction occurs on the surface of the silicon wafer: Si (solid) + O 2 (gaseous) → SiO 2 (solid), forming a first silicon oxide layer and a second silicon oxide layer of 2 nm.

[0037] At a temperature of 480 °C, introduce 900 sccm of silane, 8000 of nitrous oxide, a pressure of 1900 mbar, a radio frequency power of 13500 W, a duty cycle of 15 to 500, and a reaction time of 70 s to form a first silicon oxide layer and a second silicon oxide layer of 1 - 3 nm.

[0038] 10. Back passivation film After back passivation, a silicon oxynitride and a silicon nitride antireflection film are sequentially deposited on the alumina film layer. The preparation of silicon oxynitride mainly adds an N 2 O pipeline in the furnace tube, and a 1 - 5 nm silicon oxynitride film is added on the conventional back passivation alumina thin film. The principle formula: SiH 4 + NH 3 + N 2 O → SiyON x + H 2 SiH 4 + NH 3 → Si x N y H z Using a graphite boat as a carrier, place the silicon wafer in the furnace tube. At a temperature of 500 degrees, introduce 1200 sccm of silane, 5200 sccm of ammonia, 7400 sccm of nitrous oxide, a pressure of 1600 mbar, a radio frequency power of 240000 W, and a duty cycle of 50 to 1250. The reaction time is 270 s to form a 70 - 90 second silicon oxynitride film.

[0039] At a temperature of 510 °C, introduce 2800 sccm of silane, 10000 sccm of ammonia, a pressure of 1600 mbar, a radio frequency power of 240000 W, a duty cycle of 50 to 1000, and a reaction time of 605 s to form a 1 - 5 nm second silicon nitride film.

[0040] 11. Front antireflection film In this application, a front deposition of ① (nitrous oxide reaction) silicon dioxide / ② silicon oxynitride / ③ silicon nitride antireflection film is carried out. Add N 2O pipeline. Before the conventional process, 1-3 nm (nitrous oxide reaction) silicon dioxide and 3-10 nm silicon oxynitride film are added to the bottom film to ensure that the total front film thickness is 62-82 nm, forming a positive film coating (nitrous oxide) silicon oxynitride-silicon nitride film to reduce the front reflectivity; Principle formula: SiH 4 +N 2 O→Si x O y +Si x N y +SiO x N y +N 2 +H 2 SiH 4 +NH 3 +N 2 O→Si y ON x + H 2 SiH 4 +NH 3 →Si x N y H z At a temperature of 500 °C, 900 sccm of silane, 3000 sccm of ammonia, and 8000 sccm of nitrous oxide are introduced, with a pressure of 1900 mbar, a radio frequency power of 13000 W, a duty cycle of 15 to 500, and a reaction time of 270 s to form a 35-45 nm first silicon oxynitride film on the front side. When the temperature is raised to 510 °C, 1800 sccm of silane, 6300 sccm of ammonia are introduced, with a pressure of 1900 mbar, a radio frequency power of 11500 W, a duty cycle of 30 to 500, and a reaction time of 800 s to form a 1-5 nm first silicon nitride film.

[0041] 12. Screen printing and sintering to form the first screen printing layer and the second screen printing layer.

[0042] Printing process: Loading -> First printing (back electrode) -> Oven -> Second printing (back field) -> Oven -> Third printing (main grid) -> Oven -> Fourth printing (fine grid) -> Sintering When the solar cell is illuminated, positive and negative charges accumulate on both sides of the P-N junction, thus generating a photo-induced electromotive force. In actual applications, current output is required through the upper and lower electrodes. The electrodes are conductive materials that form a tight ohmic contact with both ends of the P-N junction. Conventionally, the electrode fabricated on the illuminated surface of the cell is called the upper electrode, usually in the form of grid lines to collect the photo-generated current; while the electrode fabricated on the back of the cell is called the lower electrode or back electrode, and the lower electrode covers as much of the back of the cell as possible to reduce the series resistance of the cell. The sintering process mainly forms a good ohmic contact between the printed positive and negative electrodes and the silicon wafer under the action of high temperature. At the same time, the high temperature in the sintering furnace can promote the diffusion of H generated during the coating process into the interior of the cell, which has a good passivation effect on the solar cell and improves the conversion efficiency of the solar cell. After the screen printing process, there is a drying furnace. For the cell passing through the drying furnace, the organic substances contained in the paste are volatilized. At this time, we consider it to be in contact. When passing through the sintering furnace, the metal electrode material and the silicon on the surface of the cell reach the eutectic temperature of the material under the heating of infrared rays. At this time, silicon atoms will enter the molten metal electrode material to form an alloy system. When the temperature drops to a certain range, the silicon atoms in the alloy system will recrystallize to form an epitaxial layer between the silicon wafer and the metal electrode, forming a good ohmic contact. Among them, the sintering section rapidly heats up from 500 °C to about 820 °C, and the substrate must reach the eutectic temperature in a very short time, and then rapidly cool down to below 500 °C. This period is about 10 s, and it only stays at 820 °C for 2 - 3 s.

[0043] 1) Optical injection Reduce the light-induced degradation of the cell through the light degradation furnace.

[0044] Classification and detection process Table 1 Test machine display

[0045] Δuoc is the change value of the open-circuit voltage; UOC is the open-circuit voltage, that is, when the solar cell is irradiated by a light source of 100 mW / cm 2 and the output voltage value of the solar cell when it is open-circuited at both ends.

[0046] ΔISC is the change value of the short-circuit current; ISC is the short-circuit current, which is the current flowing through both ends of the solar cell when the output is short-circuited under the irradiation of a standard light source.

[0047] ΔFF is the change value of the maximum output power; FF is an important indicator for measuring the output characteristics of solar cells. It represents the characteristic of the maximum power that a solar cell can output when connected to the optimal load. The larger its value, the greater the output power of the solar cell. The value of FF is always less than 1. In fact, due to the influence of series resistance and parallel resistance, the fill factor value of an actual solar cell is lower than the ideal value given by the above formula. Series and parallel resistances have a greater impact on the fill factor. The greater the series resistance, the more the short-circuit current decreases, and the more the fill factor also decreases; the smaller the parallel resistance, the greater this part of the current, the more the open-circuit voltage decreases, and the more the fill factor also decreases.

[0048] ΔETa is the change value of the maximum energy conversion efficiency at the optimal load resistance; ETa is the conversion efficiency of the solar cell, which refers to the maximum energy conversion efficiency when connecting the optimal load resistance in the external circuit and is equal to the ratio of the output power of the solar cell to the energy incident on the surface of the solar cell. The photoelectric conversion efficiency of a solar cell is an important parameter for measuring the quality and technical level of the cell, and it is related to the cell structure, junction characteristics, material properties, working temperature, radioactive particle radiation damage, and environmental changes, etc.

[0049] Table 2 Front PID test data

[0050] Table 3 Back PID test data

[0051] Table 4 PID test data of Example 1

[0052] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A topcon battery, characterized in that: It comprises an n-type silicon base, and a P-type emitter, a first tunneling oxide layer, a local POLY layer, a first aluminum oxide passivation layer, a first silicon oxide layer, a first silicon oxynitride layer, a silicon nitride anti-reflection layer, and a first screen-printed layer are sequentially arranged on the front side of the n-type silicon base; The back side is provided with a second tunneling oxide layer, a POLY layer, a second aluminum oxide passivation layer, a second silicon oxide layer, a second silicon oxynitride layer, a third silicon nitride layer, and a second screen printing layer in sequence.

2. A topcon battery according to claim 1, characterized in that: The thickness of the first tunneling oxide layer and the second tunneling oxide layer are both 1.4-1.6nm; The thickness of the silicon nitride anti-reflection layer is 3-10nm; The thickness of the first silicon oxynitride film is 70-90 nm.

3. A method for preparing a topcon battery according to claim 1 or 2, characterized in that: The steps include: S1: Texturing treatment of silicon wafer; S2: Boron expansion, forming a phosphorus-doped polysilicon layer and a borosilicate glass layer, and the back edges of the phosphorus-doped polysilicon layer and the borosilicate glass layer are expanded around. Use HF to remove the borosilicate glass on the back edge and the edge. Back alkali polishing to remove the phosphorus-doped polysilicon layer at the edge and back to form a P-type emitter; S3: performing back side deposition to form a first tunneling oxide layer and a second tunneling oxide layer; S4: phosphorus diffusion, phosphorus doping the back polysilicon to form a phosphorus silicon glass layer and a local phosphorus doped polysilicon layer and a phosphorus doped polysilicon layer; S5: Use HF to remove the phosphosilicate glass layer on the front and edge; S6: laser mask; S7: performing RCA cleaning to remove the phosphorus-doped polysilicon layer on the front and edge, and the polysilicon layer and borosilicate glass layer on the front; S8: forming a first aluminum oxide passivation layer and a second aluminum oxide passivation layer on the boron diffusion surface and the front passivation surface respectively; S9: single-sided annealing, forming a first silicon oxide layer on the back of the cell and a second silicon oxide layer on the front of the cell; S10: After back passivation, a second silicon oxynitride layer is formed on the back of the cell; A first silicon oxynitride layer is formed on the front side of the cell; Back deposition, forming a silicon nitride anti-reflection layer on the front side and a third silicon nitride layer on the back side; S11: screen printing and sintering to form a first screen printing layer and a second screen printing layer.

4. The method for preparing a topcon battery according to claim 3, characterized in that: The texturing in step S1 is carried out in a tank cleaning device; The temperature of texturing is 75-85℃, the time is 4-6min, and the thinning amount of silicon wafer is 0.36-0.42g.

5. The method for preparing a topcon battery according to claim 3, characterized in that: In step S2, the boron diffusion includes: the temperature is 860-880°C, the furnace pressure is 90-110 mbar, 2900-3100 sccm of O2 is introduced for 170-190s to form a polysilicon layer; then 2000 sccm of N2 is introduced for 0.5-1.5min, and then 190-210 sccm of BCL3, 600-700 sccm of O2, and 3900-4100 sccm of N2 are introduced for 600-800s to perform boron diffusion deposition, and then 2400-2 600sccm N2 purge for 0.5-1.5min, heat up to 900-1000℃, furnace tube pressure 400-500mbar, introduce 3900-4100sccm N2, introduction time 500-600s, heat up to 1000-1100℃, furnace tube pressure 200-400mbar, introduce 9000-11000sccm O2, introduction time 4500-4700s, form phosphorus-doped polysilicon layer and borosilicate glass layer back edge expansion, form square resistance 250-350Ω / sq; In step S2, HF is used to remove the borosilicate glass on the back edge and the edge, and chain cleaning is adopted. Polishing is performed in a tank cleaning device, and the cleaning liquid of the tank cleaning device is KOH; The cleaning temperature is 60-70°C, the cleaning time is 210-230s, and the thinning amount of the silicon wafer is 0.1-0.3g; The back side alkaline polishing is carried out in a tank cleaning device, the cleaning liquid of the tank cleaning device is KOH; the cleaning temperature is 60-70°C, the time is 210-230s, and the thinning amount of the silicon wafer is 0.1-0.3g.

6. The method for preparing a topcon battery according to claim 3, characterized in that: The backside deposition of the polished silicon wafer in step S3 includes oxidation at a temperature above 600° C., introducing 35000-37000 sccm of O2 for 470-490 seconds, evacuating, removing oxygen, and then introducing 800-1000 sccm of silane for 1500-1700 seconds at a pressure of 250-350 mbar; The thickness of the first tunneling oxide layer and the second tunneling oxide layer are both 1.4-1.6 nm.

7. The method for preparing a topcon battery according to claim 3, characterized in that: In step S4, phosphorus diffusion includes forming a phosphorus silicon glass layer and a phosphorus-doped polysilicon layer by thermal diffusion in a tubular furnace, at a temperature of 900-940°C, introducing 850-900sccm of PClO3 gas, an oxygen flow rate of 700-900sccm, and a time of 50-70min.

8. The method for preparing a topcon battery according to claim 3, characterized in that: In step S8, trimethylaluminum and water are introduced into the furnace tube to form a first aluminum oxide passivation layer and a second aluminum oxide passivation layer with a thickness of 5-10 nm; The annealing temperature in step S9 is 480°C, 800-1000sccm silane, 7000-9000 nitrous oxide, pressure 1800-2000mbar, RF power 13000-14000W, duty cycle 15:500, reaction time 60-80s, forming a 1-3nm first silicon oxide layer and a 1-3nm second silicon oxide layer respectively.

9. The method for preparing a topcon battery according to claim 3, characterized in that: The second silicon oxynitride layer is formed on the back in step S10, which includes using a graphite boat as a carrier, placing the battery cell annealed in step S9 into a furnace tube, introducing 1100-1300sccm of silane, 5100-5300sccm of ammonia, 7300-7500sccm of nitrous oxide, a pressure of 1500-1700mbar, a radio frequency power of 230000-250000W, and a duty cycle of 50:1200-1300 at a temperature of 500°C, and a reaction time of 260-280s to form a second silicon oxynitride film on the back of the battery cell; The temperature was raised to 510°C, and 2800 sccm of silane and 10000 sccm of ammonia were introduced. The pressure was 1600 mbar, the RF power was 240000 W, and the duty cycle was 50:1000. The reaction time was 605 s, and the first silicon nitride film was formed on the back of the cell. The thickness of the second silicon oxynitride film is 70-90 nm; The thickness of the second silicon nitride film is 1-5 nm.

10. The method for preparing a topcon battery according to claim 3, characterized in that: Step S10: On the front side of the battery, at a temperature of 500°C, 800-1000sccm of silane, 2800-3200sccm of ammonia, 7500-8500sccm of nitrous oxide, a pressure of 1800-2000mbar, a radio frequency power of 12000-14000W, a duty cycle of 15:500, a reaction time of 260-280s, and a 35-45nm first silicon oxynitride film are introduced; The temperature is raised to 510°C, 1700-1900sccm of silane and 6200-6400sccm of ammonia are introduced, the pressure is 1800-2000mbar, the RF power is 11000-12000W, the duty cycle is 30:500, the reaction time is 700-900s, and a first silicon nitride film of 1-5nm is formed.

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