Stacked field effect transistor structure with independent gate control between top and bottom gates

Abstract

The semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is on top of the first transistor. The second gate is electrically coupled to the second transistor. A dielectric isolation layer is between the first gate and the second gate. The first conductive contact is electrically coupled to the first gate. The second conductive contact is electrically coupled to the second gate. Control of the first gate through the first conductive contact is independent of control of the second gate through the second conductive contact.

Description

Technical Field

[0001] The present disclosure generally relates to electrical devices, and more particularly, to a stacked FET structure capable of achieving independent gate control of a top gate and a bottom gate. Background Art

[0002] In a stacked nanosheet transistor structure, the gate control of each transistor can typically be shared by the same gate element. Figure 1A A conventional stacked transistor device is shown. As can be seen from the figure, the top transistor and the bottom transistor share the same gate. In some devices, the top transistor and the bottom transistor can be different types of devices (e.g., pFET and nFET). In I / O circuit designs, not all gates of nFET / pFET structures are connected. By sharing the same gate, the nFET can induce noise in a circuit connected to the pFET.

[0003] Although noise is undesirable, current manufacturing processes are typically limited by the standard practice of forming dummy gate regions for all channels in a stacked nanosheet structure. The nanosheets of the semiconductor channels are formed with a sacrificial layer that ultimately defines the insulator between each channel layer. Dummy gate material is deposited around the nanosheet stack until the signal channels are defined. When the dummy gate material is removed, the dummy gate cavities are adjacent to all signal channels. The gate material fills the cavities adjacent to the channels indiscriminately, such that each transistor contacts the same gate metal. Thus, when a signal is conducted by the gate of one transistor, another transistor sharing contact with the same gate material can cause parasitic elements, such as noise. Summary of the Invention

[0004] Generally speaking, embodiments provide a semiconductor device and a manufacturing method capable of achieving independent gate control between a top gate and a bottom gate in a stacked transistor device. The stacked transistors no longer need to share the same gate element. By separating the gate control, the device eliminates parasitic elements, such as noise, from transistors that are not part of the circuit generating the signal but share a gate with transistors used in a different circuit generating the signal.

[0005] According to an embodiment of the present disclosure, a semiconductor chip device is provided. The semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A dielectric isolation layer is on top of at least a portion of the first transistor. A second transistor is on top of at least a portion of the dielectric isolation layer. A second gate is electrically coupled to the second transistor. The dielectric isolation layer is arranged to isolate the first gate from the second gate. A first conductive contact is electrically coupled to the first gate. The first conductive contact is within a first lateral boundary of the first transistor and outside a second lateral boundary of the second transistor.

[0006] In one embodiment, a second conductive contact is electrically coupled to a second gate. The second conductive contact is within a first lateral boundary and within a second lateral boundary. As can be appreciated, the structure defines separate access to the respective gates by offsetting the boundaries of each gate. In a stacked structure, the gates typically share the same contact because the bottom gate is blocked from accessing the top side by the top gate. However, by offsetting the gate boundaries, a path is opened to access the bottom gate independently of the top gate.

[0007] According to an embodiment of the present disclosure, a semiconductor chip device is provided. The semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is located on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is located between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. Control of the first gate through the first conductive contact is independent of control of the second gate through the second conductive contact.

[0008] In an embodiment that can be combined with the foregoing embodiments, the semiconductor device includes a third conductive contact electrically coupled to a first source / drain of the first transistor. The third conductive contact is connected to the front side of the first transistor. A fourth conductive contact is electrically coupled to a second source / drain of the first transistor. The fourth conductive contact is connected to the front side of the first transistor. A fifth conductive contact is electrically coupled to a first source / drain of the second transistor. The fifth conductive contact is connected to the front side of the second transistor. A sixth conductive contact is electrically coupled to a second source / drain of the second transistor. The sixth conductive contact is connected to the front side of the second transistor. When combined with independent gate access, access to the bottom transistor element can be achieved simultaneously with access to the top transistor element from the front side of the device. Thus, the manufacturing process can be made easier by forming access to the stacked transistors entirely on the front side of the device.

[0009] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device is provided. The method includes forming a first nanosheet stack on a substrate. A second nanosheet stack is formed on top of the first nanosheet stack. A first dummy gate is adjacent to the first nanosheet stack and is formed under the bottom nanosheet of the second nanosheet stack. A dielectric isolation layer is formed on top of the first dummy gate and between the first nanosheet stack and the second nanosheet stack. A second dummy gate is formed on top of the dielectric isolation layer and is adjacent to the second nanosheet stack. The first dummy gate is electrically coupled to a bottom gate of the first nanosheet stack instead. The first nanosheet stack cooperates with the gate material of the bottom gate to form a first transistor. The second dummy gate is replaced with a top gate electrically coupled to the second nanosheet stack. The second nanosheet stack cooperates with the gate material of the top gate to form a second transistor. A first conductive contact electrically coupled to the bottom gate is formed. A second conductive contact electrically coupled to the top gate is formed. The control of the bottom gate through the first conductive contact is independent of the control of the top gate through the second conductive contact.

[0010] In an embodiment that can be combined with the foregoing embodiments, the method includes forming a third conductive contact electrically coupled to a first source / drain of the first transistor. The third conductive contact is connected to the back side of the first transistor. A fourth conductive contact electrically coupled to a second source / drain of the first transistor is formed. The fourth conductive contact is connected to the back side of the first transistor. A fifth conductive contact electrically coupled to a first source / drain of the second transistor is formed. The fifth conductive contact is connected to the front side of the second transistor. A sixth conductive contact electrically coupled to a second source / drain of the second transistor is formed. The sixth conductive contact is connected to the front side of the second transistor. This embodiment provides backside access to the bottom transistor element, which may be useful in applications including a backside layer. For example, some applications include a back-end process layer and / or a wafer carrier on the device back side. The connection to the bottom transistor becomes accessible from the back side, which saves top-side area for more circuit elements.

[0011] The techniques described herein can be implemented in a variety of ways. Example implementations are provided below with reference to the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings are illustrative embodiments. They do not show all embodiments. Other embodiments may be used additionally or alternatively. Details that may be apparent or unnecessary may be omitted to save space or for more efficient illustration. Some embodiments may be practiced with additional components or steps and / or without all of the components or steps shown. When the same numeral appears in different drawings, it refers to the same or similar components or steps.

[0013] Figure 1A is a cross-sectional view of a conventional field-effect transistor with shared gate control.

[0014] Figure 1B is a cross-sectional view of an independently controlled field effect transistor having a top gate and a bottom gate, consistent with an embodiment of the present disclosure.

[0015] Figure 2 shows a perspective axis legend of the views in Figure 3A , Figure 3B , Figure 3C-18A , Figure 18B and Figure 18C consistent with an embodiment of the present disclosure.

[0016] Figure 3A-3C shows a view of an initial starting formation process for manufacturing a semiconductor with independent gate control according to an embodiment.

[0017] Figures 4A to 4C shows a view of depositing a hard mask and an organic planarization layer according to an embodiment.

[0018] Figures 5A to 5C shows a view of etching the hard mask and some dummy gate material downward according to an embodiment.

[0019] Figures 6A to 6C shows a view of removing the organic planarization layer according to one embodiment.

[0020] Figure 7A-7C shows a view of depositing a dielectric isolation layer according to an embodiment.

[0021] Figure 8A-Figure 8C shows a view of removing some of the dielectric isolation layer from the top stack of nanosheets according to an embodiment.

[0022] Figure 9A-9C shows a view of depositing the top portion of the dummy gate material around the top stack of nanosheets according to an embodiment.

[0023] Figure 10A-10C shows a view of patterning the top of the dummy gate material according to an embodiment.

[0024] Figure 11A-11C shows a view of recessing downward through the top stack of nanosheets according to an embodiment.

[0025] Figure 12A-12C shows a view of selectively removing sacrificial layer material from the top stack of nanosheets and from a portion of the bottom stack of nanosheets according to an embodiment.

[0026] Figures 13A to 13C shows a view of depositing spacer material into the cavity formed by selectively removing the sacrificial layer material according to an embodiment.

[0027] Figures 14A to 14C Shows a view of removing some bottom gate material according to an embodiment.

[0028] Figures 15A to 15C Shows a view of removing some top gate material according to an embodiment.

[0029] Figures 16A to 16C Shows a view of replacing the top dummy gate material with a metal gate material according to an embodiment.

[0030] Figures 17A to 17C Shows a view of removing the intermediate dielectric material above the bottom dummy gate material from the top side according to an embodiment.

[0031] Figure 18A-18C Shows a view of replacing the bottom dummy gate material with a metal gate material according to an embodiment.

[0032] Figure 19A Is similar to that consistent with the embodiment Figure 2 But includes a legend of a fourth axis M.

[0033] Figure 19B-19E Shows a view of forming a metal contact according to an embodiment.

[0034] Figures 20A to 20D Shows a view of coupling a back-end process layer and a carrier wafer to the bottom side of a substrate according to an embodiment. Detailed Description

[0035] Overview

[0036] In traditional stacked transistor devices, transistor structures typically have to share the same gate elements and metal contacts. Sharing gate control results in various signal problems, including unwanted noise from adjacent transistors that are not part of the circuit. Generally, the embodiments in the present disclosure provide a semiconductor device that enables independent gate control between top and bottom fully surrounding gate structures in a transistor. In one example, the device is a field effect transistor (FET) having a stacked nanosheet structure.

[0037] In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the teachings may be practiced without these details. In other instances, well-known methods, procedures, components, and / or circuits have been described at a relatively high level without detailed description in order to avoid unnecessarily obscuring aspects of the teachings.

[0038] In one aspect, spatial relative terms are used with reference to the orientation of the described drawings, such as "front", "rear", "top", "bottom", "beneath", "below", "lower", "above", "upper", "side", "left", "right", etc. Since the components of the embodiments of the present disclosure can be positioned in a plurality of different orientations, the directional terms are for illustrative purposes and are in no way limiting. Thus, it will be understood that, in addition to the orientations depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device during use or operation. For example, if the device in the figures is flipped, the component described as "beneath" or "below" other elements or features will be oriented "above" the other elements or features. Thus, for example, the term "beneath" can encompass both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or viewed in other directions or references), and the spatially relative descriptors used herein should be interpreted accordingly.

[0039] As used herein, the terms "lateral", "planar", and "horizontal" describe an orientation parallel to the first surface of the chip or substrate. In the present disclosure, the "first surface" may be the top layer of a semiconductor device, where individual circuit devices are patterned in the semiconductor material.

[0040] As used herein, the term "vertical" describes an orientation disposed perpendicular to the first surface of the chip, chip carrier, chip substrate, or semiconductor body.

[0041] As used herein, the terms "coupled" and / or "electrically coupled" do not mean that the elements must be directly coupled together - intermediate elements may be provided between the "coupled" or "electrically coupled" elements. In contrast, if an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements. The term "electrically connected" refers to a low-ohm electrical connection between elements that are electrically connected together. The phrase "electrically connected" does not necessarily mean that the elements must be in direct physical contact with each other - intermediate elements may be provided between the "connected" or "electrically connected" elements.

[0042] Although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Describing an element as "first" or "second", etc. does not necessarily imply any order or precedence of the elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] In this document, example embodiments are described with reference to cross-sectional illustrations, which are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the regions shown in the figures are schematic in nature, and their shapes do not necessarily represent the actual shape of the regions of the device, and do not limit the scope. It should be understood that the figures and / or drawings attached to this disclosure are exemplary, non-limiting, and not necessarily drawn to scale.

[0044] It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the scope defined by the claims. The description of the embodiments is not restrictive. In particular, the elements of the embodiments described below may be combined with elements of different embodiments.

[0045] Example device structure

[0046] Now refer to Figure 1B, which shows a cross-sectional view of a semiconductor device 100 (collectively referred to as "device 100") consistent with an embodiment of the present disclosure. Device 100 includes a first transistor structure 110 and a second transistor structure 120. The regions of each of the transistor structures 110 and 120 are demarcated by dashed lines. Each of the transistor structures 110 and 120 may include a plurality of stacked nanosheet semiconductor channels (115 and 125 respectively). The transistor structures 110 and 120 may be pFETs, nFETs, or each of pFET or nFET type transistors. In the illustrated embodiment, the transistor structure 110 is stacked on top of the transistor structure 120. Thus, sometimes the transistor structure 110 will be referred to as the "top transistor 110", and the transistor structure 120 will be referred to as the "bottom transistor 120". The embodiment may also include a gate element 340 dedicated to the top transistor 110 and a gate element 350 independent of the gate element 340 and dedicated to the bottom transistor 120. The gate element 340 may sometimes be referred to as the "top gate 340" consistent with embodiments involving the "top transistor 100". The gate element 350 may sometimes be referred to as the "bottom gate 350" consistent with embodiments involving the "bottom transistor 120". Device 100 includes a dielectric isolation layer 235 that separates or partitions the gate element 340 from the gate element 350. The transistor structures 110 and 120, the gate elements 340 and 350 may be supported by a substrate 150. The embodiment generally will also include a metal contact 135 electrically connected to the first transistor structure 110. The embodiment may include separate metal contacts for the top gate 340 and the bottom gate 350. The metal contact 135 may be electrically connected from the top side of the device 100 to the gate element 340. The metal contact 145 may be electrically connected and dedicated to the gate element 350. Although not shown in this figure, the embodiment may include a separate metal contact electrically connected to the transistor 120.

[0047] Example manufacturing method

[0048] Hereinafter, the process describes a general method of forming a semiconductor device having independent gate control for multiple transistors in the same device. Figure 2 A legend is shown providing various views of the semiconductor device during the manufacturing process. Axis "X" is an end perspective view of the nanosheet stack, showing the bottom gate and the top gate. Axis "Y" is a side perspective view from along the top of the nanosheet stack. Axis "M" is a perspective view downward from the center of the bottom stack of nanosheets.

[0049] Now start referring to Figures 3A to 3C , to describe by illustration a method for manufacturing a semiconductor device 100 having independent gate control for a top transistor and a bottom transistor. Figure 3A-20DA manufacturing process including additive and subtractive processes is shown to form some circuit elements in a terminal device. The additive and subtractive processes involved (e.g., masking, deposition, etching, lithography, etc.) may be known to those skilled in the art and are not necessarily identified in each action shown. The manufacture of the devices described herein may include, for example, a multi-step sequence of lithography and / or chemical processing steps, which contribute to gradually creating electron-based systems, devices, components, and / or circuits in semiconductor and / or superconducting devices (e.g., integrated circuits). For example, devices can be manufactured on one or more substrates (e.g., a silicon (Si) substrate and / or another substrate) by methods employing techniques including but not limited to: lithography techniques, photolithography techniques, nano-lithography techniques, nanoimprint lithography techniques, photomask techniques, patterning techniques, photoresist techniques (e.g., positive photoresist, negative photoresist, hybrid photoresist, and / or another photoresist technique), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, and / or another etching technique), evaporation techniques, sputtering techniques, plasma ashing techniques, heat treatment (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, and / or another heat treatment), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical polishing (CMP), back grinding techniques, and other techniques for manufacturing integrated circuits. In some of the figures, some reference numerals of elements not affected by the steps may not be repeated.

[0050] Now referring to Figure 3A-3C , the process is shown starting from an initial starting point, which includes a first nanosheet stack formed beneath a second nanosheet stack on a substrate 150. One of ordinary skill in the art will understand the process to reach this initial structure without an explanation of forming nanosheets on the substrate 150. References to the "first" structure generally may refer to a bottom gate and a bottom transistor element. References to the "second" structure generally may refer to a top gate and a top transistor element.

[0051] The first nanosheet stack includes alternating layers of a sacrificial material 240 (e.g., silicon-germanium (SiGe30) including 30% germanium concentration) and a semiconductor layer (e.g., silicon) 125. The second nanosheet stack is similar to the first stack, except the semiconductor layer is referred to as 115. Additionally, the first nanosheet stack may be formed to be longer in the lateral direction than the width of the second stack, as Figure 3Aas shown in the perspective view. Some embodiments include a sacrificial layer 250 (e.g., SiGe60) formed between the first nanosheet stack and the second nanosheet stack. As a prelude to the end result, the second nanosheet stack will be used to define the second (or top) transistor structure 110, while the first nanosheet stack will be used to define the first (or bottom) transistor structure 120 (both shown in Figure 1B ).

[0052] An oxide layer 230 can be formed on top of both the top stack and the bottom stack of the nanosheets. A first dummy gate material 220 is formed on top of the oxide layer 230. At this stage, the first dummy gate material 220 surrounds both the top stack and the bottom stack of the nanosheets. A hard mask 210 can be added to the top of the structure to define the area for recessing.

[0053] Figure 4A-4C The deposition of an organic planarization layer (OPL) 260 into the recess created by Figure 3B and 3C is shown.

[0054] In Figure 5A-5C , the hard mask 210 has been stripped. The dummy gate material 220 is etched down around the second nanosheet stack (using, for example, reactive ion etching (RIE)). In the vertical plane, the top layer of the dummy gate material 220 can be removed until the top layer is below the bottommost semiconductor layer 115. In the illustrated embodiment, the removal is performed down to the same level as the sacrificial layer 250, but some of the dummy gate material 220 remains on top of the oxide layer 230, above and to the sides of the first nanosheet stack. In Figure 6A-6C , the OPL 260 can be removed, exposing the oxide layer 230 around the entire second nanosheet stack. As a preface, the remaining dummy gate material 220 defines the gate region of the bottom transistor 120.

[0055] In Figure 7A-7C , a dielectric layer 235 (e.g., silicon nitride or any non-EG oxide) is deposited on top of the oxide layer 230 and the dummy gate material 220 using, for example, an atomic layer deposition (ALD) process. Figure 8A-8C The deposition of an OPL 245 on top of the dielectric 235 located above the dummy gate material 220 is shown. Some of the OPL 245 can cover the vertical portion of the dielectric 235 that extends up to the sides of the base of the top stack of the nanosheets. The dielectric 235 surrounding the top stack of the nanosheets above the OPL 245 can be removed, exposing the oxide layer 230.

[0056] In Figure 9A-9CIn [description], the second dummy gate material 280 may be deposited on top of the exposed portions of the dielectric 235 and the oxide 230 that are stacked on top of the nanosheets. The second dummy gate material 280 may be the same as or different from the dummy gate material 220. Some of the second dummy gate material 280 is deposited in the area planned for forming the top gate element. As can be appreciated, the position of the dielectric 235 insulates the top gate region from the bottom gate region (outside the region transitioning from the top transistor to the bottom transistor), which will ultimately result in the formation of a connection that provides independent control of the top gate element and the bottom gate element. Figure 10A-10C It shows patterning a recess into the dummy gate material 280 using the gate hard mask 290.

[0057] Figure 11A-11C It shows performing a groove in the top stack of the nanosheets. The level of the groove may extend through the sacrificial layer 250 and into the topmost sacrificial layer 240 of the bottom stack of the nanosheets. Some embodiments may include depositing the spacer layer 225 on the sidewalls of the recess. Some embodiments include depositing the dielectric layer 265 on a portion of the oxide layer 230 covering the bottom stack of the nanosheets using, for example, a spin-on glass (SOG) process.

[0058] In Figure 12A-12C , the material in the sacrificial layer 240 in the top stack of the nanosheets may be selectively removed to form a recess that indents inward from the side of the semiconductor channel 115 (see Figure 12B ). The removal of the material may occur at the topmost sacrificial layer 240 of the bottom stack of the nanosheets. Additionally, the same process for removing the sacrificial layer 240 may completely remove the sacrificial layer 250 between the top nanosheet stack and the bottom nanosheet stack, leaving a space 250e. In Figure 13A-13C , the cavity defining the recess and the space 250e left from removing the sacrificial layer material may be filled with the insulating spacer material 270. The insulating spacer material 270 provides a conduction barrier layer between the top transistor structure 110 and the bottom transistor structure 120. At this stage, the insulating spacer material 270 cooperates with the dielectric layer 235 to form an insulating barrier layer between the top gate region and the bottom gate region.

[0059] Figure 14A-14C It shows the process of removing some of the dummy gate materials 220 and 280 (exposing the oxide 275 in the process) using the hard mask 290. The left and right edges of the dummy gate material 220 define the lateral boundaries of the bottom gate region. In Figure 14B , it shows the source-drain material 310 (horizontally oriented) of the top transistor. In Figure 14B and 14CIn [reference], the source-drain material 320 (horizontally oriented) of the bottom transistor is shown. The insulator 330 is located between the top transistor source-drain 310 and the bottom transistor source-drain 320.

[0060] In Figure 15A-15C [reference], a cutting process for removing the dummy gate material 220 for the top gate element is shown. As Figure 15A shown, some of the dummy gate material 280 is removed. In one embodiment, the left lateral boundary edge of the dummy gate material 280 shares the lateral boundary edge with the left side of the dummy gate material 220. The right side of the dummy gate material 280 can be removed laterally inward, passing the outer right lateral boundary edge of the dummy material 220. By offsetting the gate region, space will become available for adding a separate metal contact for the bottom gate accessed from the top side (which can be seen in Figure 19B [reference]).

[0061] In Figure 16A-16C [reference], the process removes the sacrificial layer 240 of the top stack and the top dummy gate material 280 for the nanosheets. The top dummy gate material 280 is replaced with a metal gate 340. Those of ordinary skill in the art will understand the techniques available for replacing the dummy gate material 280 with the metal gate 340. The removal of the sacrificial layer 240 can also form cavities between the semiconductor channels 115. The deposition of the metal gate 340 can fill the channel cavities, thereby forming a mandrel around the channels. In some embodiments, the top transistor 110 can be a gate-all-around structure.

[0062] In Figure 17A-17C [reference], an area of the oxide 275 above the dummy gate material 220 can be opened. In the shown embodiment, the opened area is above a portion of the bottom nanosheet stack that laterally extends to the right of the top transistor 110. The opening can remove both a portion of the oxide 275 and the dielectric 235, thereby exposing the dummy gate material 220 to the top side of the device 100. Figure 18A-18C The result of removing the dummy gate material 220 and replacing the dummy gate material 220 with a metal gate 350 is shown. The metal gate 350 can be the same metal as the gate 340 or a different metal. Similar to the top transistor 110, the metal gate 350 can wrap around the channel 125 to form a transistor 120.

[0063] Figure 19A-19E An example of the resulting structure of the device 100 after adding the metal contacts 130, 135, and 145 to connect the top gate 340 and the bottom gate 350 to the top side of the device 100 is shown. Figure 19A is related to Figure 2A legend similar to the legend in [reference] is shown, except that a fourth axis H is added, which shows a cross-sectional perspective view along the bottom gate contact. The process of showing the material depression to form the openings for the metal contacts 130, 135, and 145 is omitted.

[0064] In Figure 19B , the metal contact 130 electrically couples the source-drain of the top transistor 110 to the top surface through the top side of the transistor 110. The metal contact 140 electrically couples the source-drain of the bottom transistor 120 to the top surface through the top side of the transistor 120. The metal contact 135 electrically couples the gate 340 of the top transistor 110 to the top surface. The metal contact 145 electrically couples the bottom gate 350 of the bottom transistor 120 to the top surface. An additional perspective view shown along axis H (as Figure 19D shown) is a perspective view from a cross-section along the device structure including multiple metal contacts 145.

[0065] Figures 20A-20D An embodiment of the device 100 is shown, which is similar to the embodiment shown in Figure 19B-19E , except that the device 100 is configured for backside access of the bottom transistor 120. The metal contact 165 can be formed on the backside of the substrate 150 ( Figure 20C ). The metal contact 165 can be electrically coupled to the source-drain region 320 of the bottom transistor 120. In some embodiments, the back end of the layer 370 can be formed under the substrate 150. Some embodiments can include a carrier wafer 380 formed under the back end of the layer 370.

[0066] Conclusion

[0067] The description of various embodiments of the present teachings has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology found in the market, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

[0068] Although the best mode and / or other examples have been described above, it should be understood that various modifications can be made therein, and the subject matter disclosed herein can be implemented in various forms and examples, and the teachings can be applied to many applications, only some of which are described herein. The appended claims are intended to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0069] The components, steps, features, objects, benefits, and advantages discussed herein are merely illustrative. None of them, nor the discussions related to them, are intended to limit the scope of protection. Although various advantages have been discussed herein, it should be understood that not all embodiments must include all advantages. Unless otherwise specified, all measurements, values, ratings, positions, sizes, dimensions, and other specifications set forth in this specification (including the appended claims) are approximate, not exact. They are intended to have a reasonable range consistent with the functions they relate to and the conventions in the fields to which they belong.

[0070] Numerous other embodiments are also contemplated. These embodiments include those having fewer, additional, and / or different components, steps, features, objects, benefits, and advantages. These also include embodiments in which the components and / or steps are arranged and / or ordered differently.

[0071] Although the foregoing has been described in connection with exemplary embodiments, it should be understood that the term "exemplary" merely means as an example, not the best or optimal. Except as just stated above, nothing stated or shown is intended or should be construed to result in any component, step, feature, object, benefit, advantage, or equivalent being dedicated to the public, whether or not recited in the claims.

[0072] It should be understood that the terms and expressions used herein have the ordinary meanings consistent with these terms and expressions in their corresponding respective fields of investigation and study, unless a specific meaning has been set forth herein. Relational terms such as first and second may be used solely to distinguish one entity or action from another entity or action, and do not necessarily require or imply any actual such relationship or order between these entities or actions. The terms "comprising," "including," or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "a" or "an" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0073] A summary of the present disclosure is provided to enable a reader to quickly ascertain the nature of the technical disclosure. It should be understood that the summary will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing detailed description, it can be seen that for the purpose of simplifying the present disclosure, various features are grouped together in various embodiments. The method of the present disclosure should not be construed as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. On the contrary, as reflected by the following claims, the inventive subject matter lies in less than all of the features of a single disclosed embodiment. Accordingly, the appended claims are hereby incorporated into the detailed description, where each claim stands on its own as a separately claimed subject matter.

Claims

1. A semiconductor device, comprising: a first transistor; a first gate electrically coupled to the first transistor; a dielectric isolation layer on top of at least a portion of the first transistor; a second transistor on top of at least a portion of the dielectric isolation layer; a second gate electrically coupled to the second transistor, wherein the dielectric isolation layer is arranged to isolate the first gate from the second gate; and a first conductive contact electrically coupled to the first gate, wherein the first conductive contact is within a first lateral boundary of the first transistor and outside a second lateral boundary of the second transistor.

2. The semiconductor device according to claim 1, further comprising a second conductive contact electrically coupled to the second gate, wherein the second conductive contact is within the first lateral boundary and within the second lateral boundary.

3. The semiconductor device according to claim 1, further comprising: a second conductive contact electrically coupled to a first source or drain of the first transistor, wherein the second conductive contact is connected to a front side of the first transistor; and a third conductive contact electrically coupled to a second source or drain of the first transistor, wherein the third conductive contact is connected to the front side of the first transistor.

4. The semiconductor device according to claim 3, further comprising: a fourth conductive contact electrically coupled to a first source or drain of the second transistor, wherein the fourth conductive contact is connected to a front side of the second transistor; and a fifth conductive contact electrically coupled to a second source or drain of the second transistor, wherein the fifth conductive contact is connected to the front side of the second transistor.

5. The semiconductor device according to claim 1, further comprising: a second conductive contact electrically coupled to a first source or drain of the first transistor, wherein the second conductive contact is connected to a back side of the first transistor; a third conductive contact electrically coupled to a second source or drain of the first transistor, wherein the third conductive contact is connected to the back side of the first transistor; a fourth conductive contact electrically coupled to a first source or drain of the second transistor, wherein the fourth conductive contact is connected to a front side of the second transistor; and a fifth conductive contact electrically coupled to a second source or drain of the second transistor, wherein the fifth conductive contact is connected to the front side of the second transistor.

6. The semiconductor device according to claim 1, further comprising a nanosheet stack in the first transistor and in the second transistor.

7. A semiconductor device, comprising: a first transistor; a first gate electrically coupled to the first transistor; a second transistor on top of the first transistor; a second gate electrically coupled to the second transistor; a dielectric isolation layer between the first gate and the second gate; a first conductive contact electrically coupled to the first gate; and a second conductive contact electrically coupled to the second gate, wherein control of the first gate through the first conductive contact is independent of control of the second gate through the second conductive contact.

8. The semiconductor device according to claim 7, wherein the second gate is located on top of at least a portion of the first gate.

9. The semiconductor device according to claim 7, further comprising a nanosheet stack in the first transistor and in the second transistor.

10. The semiconductor device according to claim 9, further comprising gate materials for the first gate and the second gate, wherein the gate materials wrap around the nanosheet stack.

11. The semiconductor device according to claim 7, further comprising: A third conductive contact electrically coupled to a first source or drain of the first transistor, wherein the third conductive contact is connected to the front side of the first transistor; A fourth conductive contact electrically coupled to a second source or drain of the first transistor, wherein the fourth conductive contact is connected to the front side of the first transistor; A fifth conductive contact electrically coupled to a first source or drain of the second transistor, wherein the fifth conductive contact is connected to the front side of the second transistor; and A sixth conductive contact electrically coupled to a second source or drain of the second transistor, wherein the sixth conductive contact is connected to the front side of the second transistor.

12. The semiconductor device according to claim 7, further comprising: A third conductive contact electrically coupled to a first source or drain of the first transistor, wherein the third conductive contact is connected to the back side of the first transistor; A fourth conductive contact electrically coupled to a second source or drain of the first transistor, wherein the fourth conductive contact is connected to the back side of the first transistor; A fifth conductive contact electrically coupled to a first source or drain of the second transistor, wherein the fifth conductive contact is connected to the front side of the second transistor; and A sixth conductive contact electrically coupled to a second source or drain of the second transistor, wherein the sixth conductive contact is connected to the front side of the second transistor.

13. The semiconductor device according to claim 7, wherein the first transistor is an nFET and the second transistor is a pFET.

14. The semiconductor device according to claim 7, wherein the first transistor is a pFET and the second transistor is an nFET.

15. A method of manufacturing a semiconductor device, comprising: Forming a first nanosheet stack on a substrate; Forming a second nanosheet stack on top of the first nanosheet stack; Forming a first dummy gate adjacent to the first nanosheet stack and under a bottom nanosheet of the second nanosheet stack; Forming a dielectric isolation layer on top of the first dummy gate and between the first nanosheet stack and the second nanosheet stack; Forming a second dummy gate on top of the dielectric isolation layer and adjacent to the second nanosheet stack; Replacing the first dummy gate with a bottom gate electrically coupled to the bottom of the first nanosheet stack, wherein the first nanosheet stack cooperates with the gate material of the bottom gate to form a first transistor; Replacing the second dummy gate with a top gate electrically coupled to the top of the second nanosheet stack, wherein the second nanosheet stack and the gate material of the top gate cooperate to form a second transistor; Forming a first conductive contact electrically coupled to the bottom gate; and Forming a second conductive contact electrically coupled to the top gate, wherein the control of the bottom gate through the first conductive contact is independent of the control of the top gate through the second conductive contact.

16. The method according to claim 15, further comprising forming the first nanosheet stack to have a width greater than the width of the second nanosheet stack.

17. The method according to claim 16, further comprising: Indenting the lateral boundaries of the second dummy gate inwardly, wherein the lateral boundaries of the second dummy gate are within the lateral boundaries of the first dummy gate; and Positioning the first conductive contact outside the lateral boundary of the top gate and within the lateral boundary of the bottom gate.

18. The method according to claim 15, further comprising: Forming a third conductive contact electrically coupled to the first source or drain of the first transistor, wherein the third conductive contact is connected to the front side of the first transistor; Forming a fourth conductive contact electrically coupled to the second source or drain of the first transistor, wherein the fourth conductive contact is connected to the front side of the first transistor; Forming a fifth conductive contact electrically coupled to the first source or drain of the second transistor, wherein the fifth conductive contact is connected to the front side of the second transistor; and Forming a sixth conductive contact electrically coupled to the second source or drain of the second transistor, wherein the sixth conductive contact is connected to the front side of the second transistor.

19. The method according to claim 15, further comprising: Forming a third conductive contact electrically coupled to the first source or drain of the first transistor, wherein the third conductive contact is connected to the back side of the first transistor; Forming a fourth conductive contact electrically coupled to the second source or drain of the first transistor, wherein the fourth conductive contact is connected to the back side of the first transistor; Forming a fifth conductive contact electrically coupled to the first source or drain of the second transistor, wherein the fifth conductive contact is connected to the front side of the second transistor; and Forming a sixth conductive contact electrically coupled to the second source or drain of the second transistor, wherein the sixth conductive contact is connected to the front side of the second transistor.

20. The method according to claim 19, further comprising: Forming a back-end process layer on the back side of the substrate; and Forming a wafer carrier on the back side of the back-end process layer.

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