Action potential half-width detector and method based on odd nonlinear energy operator
Through an action potential half-width detector based on odd nonlinear energy operators, the operation potential signal is processed using the odd nonlinear energy operator, a positive and negative peak detection circuit and an exclusive OR gate, the problem of difficulty in detecting the action potential half-width in the prior art is solved, and the accurate half-width detection and signal-to-noise ratio improvement of the action potential signal is achieved.
Patent Information
- Application Number
- CN202510190042.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-20
- Publication Date
- 2025-06-13
AI Technical Summary
It is difficult for the prior art to accurately detect the half-width of the action potential, and the signal-to-noise of the action potential signal is relatively low. The existing algorithms mainly target positive peak amplitude preprocessing, and do not involve the measurement of basic characteristics such as the time range and half-width of the action potential.
The operation potential half-width detector based on odd nonlinear energy operators is adopted, and the operation potential signal is detected by a cascaded odd nonlinear energy operator, a positive and negative peak detection circuit and an exclusive OR gate. The odd nonlinear energy operator includes multiple low-voltage high-linear multiplier, single-order differentializer and subtractor. Through these circuit units, the action potential signal is differentially amplified, amplitude multiplied, and positive and negative peak detection, and finally outputs the half-width detection result through the exclusive OR gate.
The half-width detection of the action potential signal is realized, and the half-width of the action potential signal with a smaller amplitude can be accurately detected without missed detection and misdetection, which improves the signal-to-noise ratio and retains the characteristic value of the action potential.
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Figure CN120150680A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of medical electronic integrated circuits, relates to the detection of the half-width of action potentials, and specifically relates to an action potential half-width detector and method based on an odd non-linear energy operator. Background Art
[0002] The necessity of neuroscience research and clinical diagnosis and treatment have led to early attempts to analyze and process a large number of electrophysiological signals recorded by a nerve recording system through various methods and means. One of the most critical steps in electrophysiological signal processing is the detection of action potentials. Action potential detection is not only an important tool for basic biological research but also plays a key role in medical diagnosis, drug development, and bioengineering applications. Since the signal-to-noise ratio of typical action potential signals is low, the action potential detector based on the non-linear energy operator preprocesses the action potential by enhancing the signal-to-noise ratio. In recent years, some scholars have proposed improved algorithms based on the traditional non-linear energy operator (OddNon-linear Energy Operator, NEO). For example, the Amplitude Slope Operator (ASO) algorithm improves the amplitude and slope of the spikes; the Frequency Enhancement NEO (fNEO) solves the problem of low sensitivity of the traditional NEO; the Energy Derivative (ED) eliminates the instantaneous background noise of the spikes.
[0003] The above algorithms only preprocess the positive peak amplitude of the action potential, but do not involve measuring the basic characteristics of the original action potential, such as the action potential duration, the interval time (half-width) between the positive and negative peak extrema, the maximum and minimum values of the action potential, and the slope. The action potential half-width refers to the time interval corresponding to half of the maximum potential value at the intersection of the rising and falling edges of the action potential in a neuron or muscle cell. This parameter reflects the duration and shape characteristics of the action potential and is usually used to compare the action potential characteristics of different cell types or different states. In neurobiology and physiology, by detecting the half-width of electroencephalogram signals, researchers can deeply understand the activity patterns of neurons and their relationship with behavior, and reveal the signal transmission mechanisms of different cell types and the electrophysiological changes under pathological conditions. Summary of the Invention
[0004] Object of the Invention: In order to overcome the deficiencies in the prior art, the present invention provides an action potential half-width detector and method based on an odd non-linear energy operator, which can accurately detect the half-width of action potentials in intracranial electroencephalogram signals.
[0005] Technical solution: To achieve the above object, the present invention provides an action potential half-width detector based on an odd-order non-linear energy operator, which is composed of three parts: an odd-order non-linear energy operator, a positive and negative peak detection circuit, and an exclusive OR gate connected in series in sequence;
[0006] The odd-order non-linear energy operator includes a first first-order differentiator, a second first-order differentiator, [(n + 1) / 2]+1 low-voltage high-linearity multipliers, and a subtractor; among them, [(n + 1) / 2]+1 low-voltage high-linearity multipliers are respectively the first low-voltage high-linearity multiplier, the second low-voltage high-linearity multiplier,..., the [(n + 1) / 2]+1th low-voltage high-linearity multiplier, and n is the odd order;
[0007] The positive and negative peak detection circuit is composed of a positive peak detection circuit and a negative peak detection circuit. The positive peak detection circuit is composed of a positive peak detector, a positive-stage gain control circuit, and a first comparator. The negative peak detection circuit is composed of a negative peak detector, a negative-stage gain control circuit, and a second comparator;
[0008] The exclusive OR gate is composed of an OR gate (constituted by PMOS), an AND gate (constituted by NMOS), and two inverters for generating non-signals.
[0009] Further, the first low-voltage high-linearity multiplier, the second low-voltage high-linearity multiplier,..., the [(n + 1) / 2]th low-voltage high-linearity multiplier are connected in series in sequence. The second first-order differentiator is cascaded with the [(n + 1) / 2]+1th low-voltage high-linearity multiplier. The first low-voltage high-linearity multiplier, the second low-voltage high-linearity multiplier,..., and the [(n + 1) / 2]th low-voltage high-linearity multiplier are connected in parallel with the second first-order differentiator and the [(n + 1) / 2]+1th low-voltage high-linearity multiplier to the first first-order differentiator and the subtractor.
[0010] Further, in the positive peak detection circuit, the positive peak detector, the positive-stage gain control circuit, and the first comparator are connected in series in sequence. In the negative peak detection circuit, the negative peak detector, the negative-stage gain control circuit, and the second comparator are connected in series in sequence.
[0011] Further, both the first first-order differentiator and the second first-order differentiator are circuit units with single-ended input and single-ended output, and the [(n + 1) / 2]+1 low-voltage high-linearity multipliers and subtractors are all circuit units with differential input and single-ended output; the input end of the first first-order differentiator is connected to the action potential signal to be detected, and its output end is simultaneously connected to two input ends of the first low-voltage high-linearity multiplier, one input end of the second low-voltage high-linearity multiplier, and the input end of the second first-order differentiator. The output end of the first low-voltage high-linearity multiplier is simultaneously connected to the other input ends of the second to the (n + 1) / 2 low-voltage high-linearity multipliers. The output end of the second first-order differentiator is connected to the input end of the [(n + 1) / 2]+1 low-voltage high-linearity multiplier, and the other input end of the [(n + 1) / 2]+1 low-voltage high-linearity multiplier is connected to the action potential signal to be detected. The two input ends of the subtractor are respectively connected to the output end of the (n + 1) / 2 low-voltage high-linearity multiplier and the output end of the [(n + 1) / 2]+1 low-voltage high-linearity multiplier.
[0012] Further, the output end of the subtractor is simultaneously connected to the input ends of the positive peak detector and the negative peak detector; the output end of the positive peak detector is connected to the input end of the positive gain control circuit, and the output end of the positive gain control circuit is connected to the inverting input end of the first comparator. The non-inverting input end of the first comparator is connected to the output end of the subtractor; the output end of the negative peak detector is connected to the input end of the negative gain control circuit, and the output end of the negative gain control circuit is connected to the inverting input end of the second comparator. The non-inverting input end of the second comparator is connected to the output end of the subtractor. The output ends of the first comparator and the second comparator are respectively connected to the two input ends of the exclusive OR gate, and the output end of the exclusive OR gate is the detection result of the action potential half-width.
[0013] Further, the positive gain control circuit is composed of five cascaded unity gain control circuits (Variable Gain Amplifier, VGA), and the negative gain control circuit is composed of three cascaded unity gain control circuits; the unity gain control circuit includes an input end, an output end, and a voltage gain control end, and the voltage gain control end of the unity gain control circuit is connected to a control voltage.
[0014] Further, the calculation formula of the odd-order non-linear energy operator is as follows:
[0015]
[0016] where x(t) is the action potential signal, and y(t) ONEO is the potential signal processed by the odd-order non-linear energy operator, and n is the odd order.
[0017] The present invention also provides a detection method for an action potential half-width detector based on an odd-order non-linear energy operator, comprising the following steps:
[0018] S1: The first first-order differentiator and the second first-order differentiator perform differential amplification on the action potential signal to obtain useful information hidden at the edges of the action potential signal;
[0019] S2: The first low-voltage high-linearity multiplier, the second low-voltage high-linearity multiplier,..., and the [(n + 1) / 2]th low-voltage high-linearity multiplier perform amplitude multiplication on the action potential signal processed by the first first-order differentiator; the [(n + 1) / 2] + 1th low-voltage high-linearity multiplier performs amplitude multiplication on the action potential signal processed by the second first-order differentiator;
[0020] S3: The two action potential signals after amplitude multiplication are output to a positive and negative peak detection circuit through a subtractor. The positive peak detector and the negative peak detector are respectively used to perform positive peak detection and negative peak detection on the action potential signal. Then, the positive gain control circuit and the negative gain control circuit respectively perform positive gain adjustment and negative gain adjustment on the signals detected by the positive peak detector and the negative peak detector. Then, the signals after positive gain adjustment and negative gain adjustment are respectively output to an exclusive-OR gate through the first comparator and the second comparator;
[0021] S4: The detection result of the action potential half-width is output through the exclusive-OR gate.
[0022] In the present invention, the first-order differentiator unit is used to perform differential amplification on the action potential signal to obtain useful information hidden at the edges of the action potential signal;
[0023] The low-voltage high-linearity multiplier unit is used to perform amplitude multiplication on the action potential signal processed by the differentiator to highlight the amplitude peak. The principle is that the larger the amplitudes of the two signals are, the larger the amplitude after multiplication by the multiplier; the multiplier can strengthen certain specific parts of the input signal, especially when the signal contains sudden spikes or pulses. The sudden nature of such pulses can cause the signal output by the multiplier to have an amplitude peak at a specific moment, thereby highlighting its amplitude.
[0024] The positive and negative peak detectors are used to perform positive and negative peak detection on the action potential signal preprocessed based on the odd-order non-linear energy operator;
[0025] The positive and negative gain control circuits are used to perform positive and negative gain control on the signals detected by the positive and negative peak detectors;
[0026] The odd-order non-linear energy operator can enhance the positive and negative peak information of the action potential signal to improve the signal-to-noise ratio of the signal to be detected. While increasing the signal amplitude, the characteristic values of the action potential are retained. The principle is that the odd-order non-linear energy operator not only highlights the positive peak of the processed signal but also the negative peak, while the even-order non-linear energy operator can only highlight the positive peak of the processed signal;
[0027] The gain control circuit can perform gain amplification on signals of different amplitudes in inverse proportion to the amplitude. At the same time, the thresholds of the positive and negative peaks are adjusted through cascaded unit gain control circuits so that the half-width of the action potential can be detected by a comparator and an exclusive-OR gate. The principle is that the positive and negative gain control circuits first generate a control current opposite to the amplitude of the input signal voltage, and then this control current controls the voltage gain of the gain control circuit (VGA), thereby realizing gain amplification on input signals of different amplitudes in inverse proportion to their amplitudes. Secondly, the thresholds of the positive and negative peaks are generated by the positive and negative peak detectors and the positive and negative gain control circuits, and their threshold values are related to the amplitude of the signal to be detected and change adaptively. When the amplitude of the signal processed by the odd-order non-linear energy operator exceeds the thresholds of the positive and negative peaks, the first comparator and the second comparator will each output a pulse signal, and the half-width of the action potential signal can be obtained after the two pulse signals are exclusive-ORed by the exclusive-OR gate;
[0028] The gain amplification can be expressed by the following formula:
[0029] Vout = A · Vin. Where: Vout is the voltage of the output signal. Vin is the voltage of the input signal. A is the gain, which is an adjustable parameter representing the amplification factor of the amplifier.
[0030] The core function of the gain control circuit is to adjust the gain according to the intensity of the input signal, thereby avoiding signal distortion or being too small, and at the same time ensuring the stability of the amplitude of the output signal and adapting to the dynamic changes of the system.
[0031] Advantageous effects: Compared with the prior art, the present invention performs gain amplification on the action potential signal in inverse proportion to its amplitude. While enhancing the amplitude characteristics of the action potential signal, it can detect the half-width of the action potential signal with a small amplitude and will not miss detection or misdetection. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 is the circuit block diagram of the present invention;
[0033] Figure 2 is the three-order circuit block diagram of the present invention;
[0034] Figure 3 is the circuit diagram of the first and second single-stage differentiators in the present invention;
[0035] Figure 4 Circuit diagram of the first to [(n + 1) / 2]+1 low-voltage high-linearity multipliers in the present invention;
[0036] Figure 5 Circuit diagram of the subtractor in the present invention;
[0037] Figure 6 Circuit diagram of the positive peak detector in the present invention;
[0038] Figure 7 Circuit diagram of the unity gain control in the present invention;
[0039] Figure 8 Circuit diagram of the exclusive OR gate in the present invention;
[0040] Figure 9 MATLAB simulation verification diagram of the odd-order non-linear energy operator of the present invention;
[0041] Figure 10 Circuit simulation diagram of the third-order odd-order non-linear energy operator of the present invention.
[0042] Figure 11 Circuit simulation diagram of the comparator and the exclusive OR gate of the present invention. Specific embodiments
[0043] The present invention will be further illustrated below in conjunction with the accompanying drawings and specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. After reading the present invention, various equivalent modifications made by those skilled in the art fall within the scope defined by the appended claims of this application.
[0044] Embodiment 1:
[0045] As Figure 1 shown, the present invention provides an action potential half-width detector based on an odd-order non-linear energy operator, which is composed of three parts: an odd-order non-linear energy operator 10, a positive and negative peak detection circuit 20, and an exclusive OR gate 30 connected in series in sequence; the odd-order non-linear energy operator 10 includes [(n + 1) / 2]+1 low-voltage high-linearity multipliers, and n is the odd order.
[0046] As Figure 2As shown in the figure, this embodiment provides an action potential half-width detector based on a third-order odd-order non-linear energy operator, that is, n = 3. The odd-order non-linear energy operator 10 includes a first single-order differentiator 101, a second single-order differentiator 102, a first low-voltage high-linearity multiplier 104, a second low-voltage high-linearity multiplier 105, a third low-voltage high-linearity multiplier 103, and a subtractor 106. Both the first single-order differentiator 101 and the second single-order differentiator 102 are single-ended input and single-ended output circuits. The circuits of the three low-voltage high-linearity multipliers and the subtractor 106 are all double-ended input and single-ended output circuits. The first low-voltage high-linearity multiplier 104 and the second low-voltage high-linearity multiplier 105 are cascaded. The second single-order differentiator 102 is cascaded with the third low-voltage high-linearity multiplier 103. The first low-voltage high-linearity multiplier 104 and the second low-voltage high-linearity multiplier 105 are connected in parallel with the second single-order differentiator 102 and the third low-voltage high-linearity multiplier 103 to the first single-order differentiator 101 and the subtractor 106.
[0047] The positive and negative peak detection circuit 20 is composed of a positive peak detection circuit and a negative peak detection circuit. The positive peak detection circuit is composed of a positive peak detector 201, a positive stage gain control circuit 202, and a first comparator 203 cascaded in sequence. The negative peak detection circuit is composed of a negative peak detector 204, a negative stage gain control circuit 205, and a second comparator 206 cascaded in sequence. The positive peak detection circuit and the negative peak detection circuit are connected in parallel to the subtractor 106 and the exclusive-OR gate 30. The positive peak detector 201 and the negative peak detector 204, the positive stage gain control circuit 202 and the negative stage gain control circuit 205 are all single-ended input and single-ended output circuit modules. The first comparator 203 and the second comparator 206 are double-ended input and single-ended output circuits. The exclusive-OR gate 30 is a double-ended input and single-ended output circuit.
[0048] The input end of the first single-order differentiator 101 is connected to the action potential signal to be detected, and its output end is simultaneously connected to the two input ends of the first low-voltage high-linearity multiplier 104, one input end of the second low-voltage high-linearity multiplier 105, and the input end of the second single-order differentiator 102. The output end of the first low-voltage high-linearity multiplier 104 is connected to one input end of the second low-voltage high-linearity multiplier 105. The output end of the second single-order differentiator 102 is connected to the input end of the third low-voltage high-linearity multiplier 103. The other input end of the third low-voltage high-linearity multiplier 103 receives the action potential signal to be detected. The two input ends of the subtractor 106 are respectively connected to the output end of the second low-voltage high-linearity multiplier 105 and the output end of the third low-voltage multiplier 103, and its output end is simultaneously connected to the input end of the positive peak detector 201 and the input end of the negative peak detector 204.
[0049] The output terminal of the positive peak detector 201 is connected to the input terminal of the positive gain control circuit 202. The output terminal of the positive gain control circuit 202 is connected to the inverting input terminal of the first comparator 203. The non-inverting input terminal of the first comparator 203 is connected to the output terminal of the subtractor 106. The output terminal of the negative peak detector 204 is connected to the input terminal of the negative gain control circuit 205. The output terminal of the negative gain control circuit 205 is connected to the inverting input terminal of the second comparator 206. The non-inverting input terminal of the second comparator 206 is connected to the output terminal of the subtractor 106.
[0050] The positive gain control circuit 202 is composed of five cascaded unity gain control circuits. The negative gain control circuit 205 is composed of three cascaded unity gain control circuits. The unity gain control circuit includes an input terminal, an output terminal, and a voltage gain control terminal. The voltage gain control terminal of the unity gain control circuit is connected to a 1.2V voltage source.
[0051] The output terminal of the first comparator 203 and the output terminal of the second comparator 206 are respectively connected to two input terminals of the exclusive OR gate 30. The output terminal of the exclusive OR gate 30 is the detection result of the action potential half-width.
[0052] As Figure 3 shown, the first single-stage differentiator 101 and the second single-stage differentiator 102 include capacitors C 1012 , C 1013 , resistors R 1011 , R 1014 and a dual-input single-output operational amplifier gm1. Among them, the capacitance value of capacitor C 1012 is 10nF, the capacitance value of C 1013 is 1nF, the resistance value of resistor R 1011 is 1kΩ, the resistance value of resistor R 1014 is 100kΩ, one end of resistor R 1011 is connected to the input signal (v in101 ), the other end is connected to the inverting input terminal of the operational amplifier g 1012 through capacitor C m1 . The non-inverting input terminal of the operational amplifier g m1 is grounded. The output terminal of the operational amplifier g m1 (v out101 ) is feedback to the inverting input terminal of the operational amplifier g 1014 through a parallel circuit of resistor R 1013 and capacitor C m1 . The output terminal of the single-stage differentiator (v out101 ) is the input terminal of the low-voltage high-linearity multiplier.
[0053] As Figure 4 shown, the first to [(n + 1) / 2]+1 low-voltage high-linearity multipliers include PMOS transistors M 10401, M 10402 , M 10403 , M 10404 , M 10405 , M 10406 , M 10407 , M 10408 , the NMOS transistor M 10409 , M 10410 , M 10411 , M 10412 , the resistor R 10401 and R 10402 . Among them, the PMOS transistors M 10401 , M 10402 , M 10403 , M 10404 , M 10405 , M 10406 , M 10407 , M 10408 have a W / L of 0.6μm / 0.5μm, and the NMOS transistors M 10409 , M 10410 , M 10411 , M 10412 have a W / L of 0.25μm / 2.5μm. The resistors R 10401 and R 10402 have a resistance value of 15kΩ. The drains of the NMOS transistors M 10409 , M 10412 are respectively connected to the power supply voltage VDD through R 10401 and R 10402 . The gate of the NMOS transistor M 10409 is connected to the gate of the NMOS transistor M 10410 . The gate of the PMOS transistor M 10401 is connected to the input terminal (v in10401 ), and the drain is connected to the source of the PMOS transistor M 10405 . The gate of the PMOS transistor M 10402 is connected to the input terminal (v in10402 ), and the drain is connected to the source of the PMOS transistor M 10406 . The gates of the PMOS transistors M 10405 and M 10406 are connected to the input terminal (v in10403 ). The drain of the NMOS transistor M 10410 is connected to the power supply voltage VDD through the resistor R 10402 . The drain of the PMOS transistor M 10402 is connected to the source of M 10406 . The drain of the NMOS transistor M 10411 is connected to the power supply voltage VDD through the resistor R 10401 . The gate of the PMOS transistor M 10403 is connected to the input terminal (v in10401 ), and the drain is connected to the PMOS transistor M10407 is connected to the source of M 10411 and is connected to the gate of PMOS transistor M 10404 . The gate of PMOS transistor M in10402 is connected to the input terminal (v 10408 ), and the drain is connected to the source of PMOS transistor M 10412 and is connected to the gate of M 10407 . The gates of PMOS transistors M 10408 and M in10404 are connected to the input terminal (v 10401 ). The sources of PMOS transistors M 10402 , M 10403 , M 10404 are connected to the power supply voltage VDD. The drains of PMOS transistors M 10405 , M 10406 , M 10407 , M 10408 are grounded. The sources of NMOS transistors M 10409 , M 10410 , M 10411 , M 10412 are grounded. The output terminals (v out104 ) of the second and third low-voltage high-linearity multipliers are the input terminals of the subtractor 106.
[0054] As Figure 5 shown, the subtractor 106 includes resistors R 1061 , R 1062 , R 1063 , R 1064 , R 1065 , R 1066 , fully differential amplifiers g m2 , g m3 . Among them, the resistance values of R 1061 , R 1062 , R 1063 , R 1064 , R 1065 , R 1066 are all 1KΩ. The non-inverting input terminal of the operational amplifier g m2 is connected to the input signal (v 1062 ) through the resistor R in1061 . The inverting input terminal is grounded through the resistor R 1061 , and is connected to the output terminal of the operational amplifier through the resistor R 1063 . The output terminal of the operational amplifier g m2 is connected to the inverting input terminal of the operational amplifier g 1064 through the resistor R m3 . The inverting output terminal of the operational amplifier g m2 is connected to the output terminal (v 1065 ) through R out106) are connected. The non-inverting output terminal of the operational amplifier is connected to the input terminal through R 1065 to the input terminal (v in1062 ). The output terminal (v out106 ) of the operational amplifier gm3 is the input terminal of the positive and negative peak detector.
[0055] As Figure 6 shown, the positive peak detector 201 includes PMOS transistors M 20101 , M 20102 , M 20103 , M 20104 , NMOS transistors M 20105 , M 20106 , M 20107 , M 20109 , M 20110 , M 20111 , M 20112 , M 20113 , capacitor C 2011 and C 2012 . Among them, the W / L of M 10201 , M 10202 , M 10203 , M 10212 , M 10213 is 2μm / 10μm, the W / L of M 10204 , M 10211 , M 10210 is 4μm / 10μm, the W / L of M 10207 , M 10205 , M 10206 is 40μm / 0.5μm, the W / L of M 10208 , M 10209 is 20μm / 0.5μm. The sources of the PMOS transistors M 20101 , M 20102 , M 20103 , M 20104 are connected to the voltage source VDD. The drain of the PMOS transistor M 20101 is connected to the drain of the NMOS transistor M 20107 and the gate of M 20105 , and is grounded through the capacitor C 2011 . The gate of M 20107 is connected to the input terminal (v in201 ), and the source is connected to the source of M 20108 and the drain of M 20112 and is grounded through the capacitor C 2012 . The input current (I 201 ) is connected to the drain of the M 20110 transistor, the gate of M 20112 and the gate of M 20113 transistor. The drain of the M 20105 transistor is connected to the power supply voltage VDD, and the source and M20106 The source of 20111 is connected to the drain of M 20102 The gate of 20101 is connected to the gate of M 20106 The drain of 20106 is connected to the gate of M 20103 、M 20108 The drain of 20108 The gate of 20109 is shorted to the drain and connected to the gate of M out201 ) as the output terminal (v 20104 The gate of 20103 is shorted to the drain and connected to the gate of M 20109 and connected to the drain of M 20109 The source of 20113 is connected to the drain of M 20110 、M 20111 、M 20112 、M 20113 、M
[0056] As Figure 7 shown, the unity-gain control circuit includes PMOS transistors M 2021 、M 2024 , NMOS transistors M 2022 、M 2023 、M 2025 、M 2026 . The W / L of NMOS transistors M 2022 、M 2023 is 5μm / 1μm, the W / L of M 2027 is 2μm / 1μm, the W / L of M 2025 、M 2026 is 10μm / 1μm. The W / L of PMOS transistors M 2021 、M 2024 is 1μm / 1μm. The sources of PMOS transistors M 2021 、M 2024 are connected to the power supply voltage, and the drains of NMOS transistors M 2022 、M 2023 are connected to the power supply voltage. The gate of PMOS transistor M 2021 is shorted to the drain and connected to the source of M 2022 . The source of M 2022 is connected to the drain of M 2025 , the source of M 2025 is connected to the source of M 2026 and connected to the drain of M 2027 , the gate of M 2023 is connected to the gate of M 2022 , the source is connected to the drain of M 2026 2024 The gate and drain of 2026 are short - circuited and connected to the drain of M 2025 . The gate of M in202+ is connected to the input terminal (v 2026 ). The gate of M in202- is connected to the input terminal (v 2027 ). The gate of M bias202 is connected to the bias voltage (V 2027 ). The source of M out202+ , v out202- is grounded. The output terminals (v
[0057] As shown in Figure 8 , the exclusive - OR gate 30 consists of an OR gate (generally composed of PMOS), an AND gate (generally composed of NMOS), and two inverters for generating non - signals. Specifically, the OR gate is composed of two parallel PMOS transistors, and the AND gate is composed of two series - connected NMOS transistors. It includes PMOS transistors M 301 , M 303 , M 305 , M 306 , M 307 , M 308 , NMOS transistors M 302 , M 304 , M 309 , M 310 , M 311 , M 312 . The W / L of PMOS transistors M 301 , M 303 , M 302 , M 304 is 2μm / 1μm, the W / L of PMOS transistors M 305 , M 306 , M 307 , M 308 is 8μm / 1μm, and the W / L of NMOS transistors M 309 , M 310 , M 311 , M 312 is 16μm / 1μm. The input signal (v in301 ) is connected to the output terminal of the first comparator 203, and the input signal (v in302 ) is connected to the output terminal of the second comparator 206. The sources of PMOS transistors M 301 , M 303 are connected to the power supply voltage, and the drains are respectively connected to the drains of NMOS transistors M 302 , M 304 . The gates of PMOS transistor M 305 and NMOS transistor M 309 are connected to the input terminal (vin301 ) are connected. The source electrode of PMOS transistor M 305 is connected to the source electrode of M 306 and is connected to the power supply voltage VDD. The gate electrode of M 306 is connected to the gate electrode of M 311 and is connected to the input terminal (v in302 ). The drain electrode is connected to M 305 and is connected to M 307 is connected to M 308 and is connected to the gate electrode of M 307 is connected to the gate electrode of M 301 , M 302 and is connected to the drain electrode of M 310 and is connected to the gate electrode of M 308 and is connected to the drain electrode of M 307 and is connected to M 309 is connected to M 310 and is connected to the drain electrode of M 312 and is connected to the gate electrode of M 303 and is connected to the drain electrode of M 309 and is connected to the source electrode of M 311 and is connected to the source electrode of M 310 is connected to M 312 and is connected to the source electrode of M 311 and is connected to the source electrode of M 312 and is grounded. The output terminal (v out301 ) outputs the detection result of the half-width of the action potential signal.
[0058] Embodiment 2:
[0059] Based on the action potential half-width detector based on the third-order odd-order non-linear energy operator provided in Embodiment 1, this embodiment provides a detection method for the action potential half-width detector based on the odd-order non-linear energy operator. As Figure 2 shown, it includes the following steps:
[0060] S1: The first first-order differentiator 101 and the second first-order differentiator 102 perform differential amplification on the action potential signal to obtain the useful information hidden at the edge of the action potential signal;
[0061] S2: The first low-voltage high-linearity multiplier 104 and the second low-voltage high-linearity multiplier 105 perform amplitude multiplication on the action potential signal processed by the first first-order differentiator 101; The third low-voltage high-linearity multiplier 103 performs amplitude multiplication on the action potential signal processed by the second first-order differentiator 102; to highlight the amplitude peak;
[0062] S3: The two action potential signals obtained by amplitude multiplication are output to the subtractor 106 and then sent to the positive and negative peak detection circuit 20. The positive peak detector 201 and the negative peak detector 204 are respectively used to perform positive peak detection and negative peak detection on the action potential signals. Then, the positive gain control circuit 202 and the negative gain control circuit 205 are respectively used to perform positive gain adjustment and negative gain adjustment on the signals detected by the positive peak detector 201 and the negative peak detector 204. Subsequently, the signals after positive gain adjustment and negative gain adjustment are respectively output to the exclusive-OR gate 30 through the first comparator 203 and the second comparator 206;
[0063] S4: The detection result of the action potential half-width is output through the exclusive-OR gate 30.
[0064] In the present invention, the calculation formula of the odd-order non-linear energy operator 10 is as follows:
[0065]
[0066] where x(t) is the action potential signal, and y(t) ONEO is the potential signal processed by the odd-order non-linear energy operator, and n is the odd-order number.
[0067] The odd-order non-linear energy operator 10 can enhance the positive and negative peak information of the action potential signal to improve the signal-to-noise ratio of the signal to be detected. While increasing the signal amplitude, the characteristic values of the action potential are retained;
[0068] The gain control circuit can perform gain amplification on signals with different amplitudes in inverse proportion to the amplitude. At the same time, the thresholds of the positive and negative peaks are adjusted through cascaded unit gain control circuits, so as to detect the half-width of the action potential using a comparator and an exclusive-OR gate.
[0069] The gain amplification can be expressed by the following formula:
[0070] Vout = A · Vin. Where: Vout is the voltage of the output signal. Vin is the voltage of the input signal. A is the gain, which is an adjustable parameter representing the amplification factor of the amplifier.
[0071] The core function of the gain control circuit is to adjust the gain according to the intensity of the input signal, thereby avoiding signal distortion or being too small, and ensuring the stability of the amplitude of the output signal to adapt to the dynamic changes of the system.
[0072] Embodiment 3:
[0073] To verify the effectiveness and actual effect of the solution of the present invention, this embodiment uses a simulation experiment for verification and respectively obtains the Figure 9 and Figure 10 shown simulation results.
[0074] AsFigure 9 As shown, V out is the output result of MATLAB simulation. It can be seen that the odd-order non-linear energy operator can accurately retain the half-width of the action potential, and the larger the odd-order value, the more prominent the positive and negative peaks are.
[0075] As Figure 10 shown, v in is the original signal of the action potential, and V out is the output signal of the subtractor (V out106 ). It can be seen that the third-order odd-order non-linear energy operator circuit can realize the pre-emphasis of the positive and negative peaks of the action potential, and the half-width of the original action potential is consistent with the half-width after passing through the third-order odd-order non-linear energy operator circuit.
[0076] As Figure 11 shown, Vout+ is the pulse signal output by the first comparator, Vout- is the pulse signal output by the second comparator, and the time difference between two pulses close to each other in Vxor is the half-width of the corresponding action potential signal.
[0077] Therefore, it can be seen that the present invention can detect the half-width of the action potential signal with a small amplitude, and there will be no missed detection and false detection.
Claims
1. An action potential half-width detector based on an odd-order nonlinear energy operator, characterized in that: It consists of three parts: odd-order nonlinear energy operator, positive and negative peak detection circuit and XOR gate which are cascaded in sequence; The odd-order nonlinear energy operator includes a first single-order differentiator, a second single-order differentiator, [(n+1) / 2]+1 low-voltage high-linear multipliers, and a subtractor; wherein the [(n+1) / 2]+1 low-voltage high-linear multipliers are respectively a first low-voltage high-linear multiplier, a second low-voltage high-linear multiplier, ..., the [(n+1) / 2]+1th low-voltage high-linear multiplier, and n is an odd order; The positive and negative peak detection circuit is composed of a positive peak detection circuit and a negative peak detection circuit, wherein the positive peak detection circuit is composed of a positive peak detector, a positive gain control circuit and a first comparator, and the negative peak detection circuit is composed of a negative peak detector, a negative gain control circuit and a second comparator; The XOR gate is composed of an OR gate (composed of PMOS), an AND gate (composed of NMOS) and two inverters for generating a negation signal.
2. The action potential half-width detector based on odd-order nonlinear energy operator according to claim 1, characterized in that: The first low-voltage high-linear multiplier, the second low-voltage high-linear multiplier, ..., the [(n+1) / 2]th low-voltage high-linear multiplier are cascaded in sequence, the second single-order differentiator is cascaded with the [(n+1) / 2]+1th low-voltage high-linear multiplier, the first low-voltage high-linear multiplier, the second low-voltage high-linear multiplier, ... and the [(n+1) / 2]th low-voltage high-linear multiplier are connected in parallel with the second single-order differentiator and the [(n+1) / 2]+1th low-voltage high-linear multiplier, the first single-order differentiator and the subtractor.
3. The action potential half-width detector based on odd-order nonlinear energy operator according to claim 1, characterized in that: The positive peak detection circuit and the negative peak detection circuit are connected in parallel with a subtractor and an XOR gate. In the positive peak detection circuit, a positive peak detector, a positive-stage gain control circuit and a first comparator are cascaded in sequence, and in the negative peak detection circuit, a negative peak detector, a negative-stage gain control circuit and a second comparator are cascaded in sequence.
4. The action potential half-width detector based on odd-order nonlinear energy operator according to claim 2, characterized in that: The first single-order differentiator and the second single-order differentiator are both circuit units with single-end input and single-end output, and the [(n+1) / 2]+1 low-voltage high-linear multipliers and subtractors are both circuit units with double-end input and single-end output; the input end of the first single-order differentiator is connected to the action potential signal to be detected, and its output end is simultaneously connected to the two input ends of the first low-voltage high-linear multiplier, one input end of the second low-voltage high-linear multiplier, and the input end of the second single-order differentiator; the output end of the first low-voltage high-linear multiplier is connected to the input end of the first low-voltage high-linear multiplier, and the output end of the second low-voltage high-linear multiplier is connected to the input end of the second single-order differentiator. The output end is simultaneously connected to the other input end of the second to (n+1) / 2th low-voltage high-linear multipliers, the output end of the second single-order differentiator is connected to the input end of the [(n+1) / 2]+1th low-voltage high-linear multiplier, the other input end of the [(n+1) / 2]+1th low-voltage high-linear multiplier is connected to the action potential signal to be detected, and the two input ends of the subtractor are respectively connected to the output end of the (n+1) / 2th low-voltage high-linear multiplier and the output end of the [(n+1) / 2]+1th low-voltage high-linear multiplier.
5. The action potential half-width detector based on odd-order nonlinear energy operator according to claim 3, characterized in that: The output end of the subtractor is simultaneously connected to the input end of the positive peak detector and the input end of the negative peak detector; the output end of the positive peak detector is connected to the input end of the positive gain control circuit, the output end of the positive gain control circuit is connected to the inverting input end of the first comparator, and the non-inverting input end of the first comparator is connected to the output end of the subtractor; the output end of the negative peak detector is connected to the input end of the negative gain control circuit, the output end of the negative gain control circuit is connected to the inverting input end of the second comparator, the non-inverting input end of the second comparator is connected to the output end of the subtractor, the output end of the first comparator and the output end of the second comparator are respectively connected to the two input ends of the exclusive OR gate, and the output end of the exclusive OR gate is the detection result of the action potential half width.
6. The action potential half-width detector based on odd-order nonlinear energy operator according to claim 5, characterized in that: The positive-stage gain control circuit is composed of a cascade of five-stage unit gain control circuits, and the negative-stage gain control circuit is composed of a cascade of three-stage unit gain control circuits; the unit gain control circuit comprises an input terminal, an output terminal and a voltage gain control terminal, and the voltage gain control terminal of the unit gain control circuit is connected to a voltage source.
7. The action potential half-width detector based on odd-order nonlinear energy operator according to claim 1, characterized in that: The calculation formula of the odd-order nonlinear energy operator is as follows: Among them, x(t) is the action potential signal, y(t) ONEO is the potential signal after being processed by the odd-order nonlinear energy operator, and n is the odd order.
8. A detection method of an action potential half-width detector based on an odd-order nonlinear energy operator, characterized in that: The steps include: S1: The first single-order differentiator and the second single-order differentiator perform differential amplification on the action potential signal to obtain useful information hidden in the edge of the action potential signal; S2: the first low-voltage high-linear multiplier, the second low-voltage high-linear multiplier, ... and the [(n+1) / 2]th low-voltage high-linear multiplier perform amplitude multiplication on the action potential signal processed by the first single-order differentiator; the [(n+1) / 2]+1th low-voltage high-linear multiplier performs amplitude multiplication on the action potential signal processed by the second single-order differentiator; S3: The two action potential signals with amplitude multiplication are output to the positive and negative peak detection circuits through the subtractor, and the action potential signals are subjected to positive peak detection and negative peak detection respectively through the positive peak detector and the negative peak detector, and then the signals detected by the positive peak detector and the negative peak detector are subjected to positive gain adjustment and negative gain adjustment respectively through the positive gain control circuit and the negative gain control circuit, and then the signals after positive gain adjustment and negative gain adjustment are respectively output to the XOR gate through the first comparator and the second comparator; S4: Output the detection result of the action potential half-width through the XOR gate.
9. The detection method of the action potential half-width detector based on odd-order nonlinear energy operator according to claim 8, characterized in that: The gain amplification in the gain adjustment of step S3 is expressed by the following formula: Vout = A·Vin, where: Vout is the voltage of the output signal, Vin is the voltage of the input signal, and A is the gain, which is an adjustable parameter representing the amplification factor of the amplifier.