Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The device comprises a substrate; the N-type drift layer is positioned on one side of the substrate; the P-type base region is positioned on one side, far away from the substrate, of the N-type drift layer; the N-type source region and the P-type source region are located in the P-type base region; a gate trench located between the N-type source region and the P-type source region; the gate dielectric layer is located at the bottom and on the side wall of the gate groove, and the gate groove is filled with the gate layer; the total interlayer dielectric layer is positioned on one side, far away from the substrate, of the P-type base region; the N-type source region and the P-type source region are isolated by the total interlayer dielectric layer; the source electrode is positioned between the total interlayer dielectric layers and is respectively connected with the N-type source region and the P-type source region; and the drain is positioned on one side, far away from the N-type drift layer, of the substrate. According to the invention, the N-type source region and the P-type source region are separated by the total interlayer dielectric layer, so that the electron current and the hole current can be detected respectively, and whether the conduction failure of the parasitic bipolar transistor exists or not can be judged accurately when the failure occurs.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor devices, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the application of semiconductor devices, extreme operating conditions such as unclamped inductive switching (UIS), short-circuit current, or surge current are often encountered. These operating conditions will form a scenario where large voltage and large current exist simultaneously inside the device, resulting in very high power consumption of the device, generating a large amount of heat in a short time, and further causing the device to fail.

[0003] Currently, regarding the UIS failure mechanism of semiconductor devices, there are two viewpoints: high-temperature thermal failure and parasitic bipolar junction transistor (BJT) conduction failure, and there is no good method to distinguish between them.

[0004] Therefore, how to provide a semiconductor device that can accurately determine whether there is parasitic bipolar junction transistor conduction failure when the device fails is a technical problem to be solved in this field. Summary of the Invention

[0005] In view of this, this Summary of the Invention section is provided to introduce the concepts in a concise form. These concepts will be described in detail in the following Detailed Description section. This Summary of the Invention section is not intended to identify the key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0006] The purpose of this application is to provide a semiconductor device and a manufacturing method thereof, which can accurately determine whether there is parasitic bipolar junction transistor conduction failure when the device fails.

[0007] To achieve the above purpose, this application has the following technical solutions:

[0008] In a first aspect, an embodiment of this application provides a semiconductor device, including:

[0009] A substrate;

[0010] An N-type drift layer located on one side of the substrate;

[0011] A P-type base region located on the side of the N-type drift layer away from the substrate; an N-type source region and a P-type source region located in the P-type base region;

[0012] A gate trench located between the N-type source region and the P-type source region;

[0013] A gate dielectric layer located at the bottom and sidewalls of the gate trench, and a gate layer filling the gate trench;

[0014] A total interlayer dielectric layer located on the side of the P-type base region away from the substrate; the total interlayer dielectric layer separates the N-type source region and the P-type source region;

[0015] Source electrodes respectively connected to the N-type source region and the P-type source region and located between the total interlayer dielectric layers; a drain electrode located on the side of the substrate away from the N-type drift layer.

[0016] In a possible implementation manner, it further includes:

[0017] An N-type blocking layer located between the N-type drift layer and the substrate.

[0018] In a possible implementation manner, the total interlayer dielectric layer includes: a first interlayer dielectric layer and a second interlayer dielectric layer; the total interlayer dielectric layer separating the N-type source region and the P-type source region includes:

[0019] The first interlayer dielectric layer is located on the side of the gate layer and the gate dielectric layer away from the substrate, and on the side of the junction of the N-type source region and the P-type source region away from the substrate;

[0020] The second interlayer dielectric layer is located on the side of the P-type source region away from the substrate in the region connected to the N-type source region, connects the first interlayer dielectric layer, covers the P-type source region and exposes the N-type source region to separate the N-type source region and the P-type source region;

[0021] The second interlayer dielectric layer is located on the side of the N-type source region away from the substrate in the region connected to the P-type source region, connects the first interlayer dielectric layer, covers the N-type source region and exposes the P-type source region to separate the N-type source region and the P-type source region.

[0022] In a possible implementation manner, the source electrode includes: a source metal interconnect layer and a source metal layer;

[0023] The source metal interconnect layer is arranged on the same layer as the first interlayer dielectric layer and is respectively connected to the N-type source region and the P-type source region;

[0024] The source metal layer covers the second interlayer dielectric layer and is respectively connected to the source metal interconnect layer connected to the N-type source region and the source metal interconnect layer connected to the P-type source region.

[0025] In a possible implementation manner, the shapes of the N-type source region and the P-type source region include square, hexagonal or strip-shaped.

[0026] Second aspect, an embodiment of the present application provides a manufacturing method of a semiconductor device, including:

[0027] Providing a substrate;

[0028] Forming an N-type drift layer on one side of the substrate by using an epitaxial process;

[0029] Forming a P-type base region on the side of the N-type drift layer away from the substrate by using an epitaxial or ion implantation process;

[0030] Forming an N-type source region and a P-type source region in the P-type base region by using photolithography and ion implantation processes;

[0031] Forming a gate trench between the N-type source region and the P-type source region by using photolithography and etching processes;

[0032] Forming a gate dielectric layer at the bottom and sidewalls of the gate trench by using a thermal oxidation or deposition process, and filling the gate trench to form a gate layer by using deposition, photolithography and etching processes;

[0033] Forming a total interlayer dielectric layer on the side of the P-type base region away from the substrate by using deposition, photolithography and etching processes; the total interlayer dielectric layer separates the N-type source region and the P-type source region;

[0034] Forming source electrodes respectively connected to the N-type source region and the P-type source region between the total interlayer dielectric layers by using deposition, photolithography and etching processes; forming a drain electrode on the side of the substrate away from the N-type drift layer by using laser annealing, metal thickening and deposition processes.

[0035] In a possible implementation manner, after providing the substrate and before forming the N-type drift layer on one side of the substrate by using the epitaxial process, it further includes:

[0036] Forming an N-type blocking layer between the substrate and the N-type drift layer by using an epitaxial process.

[0037] In a possible implementation manner, the source electrode includes a source electrode metal interconnection layer and a source electrode metal layer; the total interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer; the forming of the total interlayer dielectric layer on the side of the P-type base region away from the substrate by using deposition, photolithography and etching processes includes:

[0038] Forming an initial interlayer dielectric layer on the side of the gate layer, the gate dielectric layer, the N-type source region and the P-type source region away from the substrate by using deposition, photolithography and etching processes;

[0039] Using a photolithography and etching process, vias are formed in the initial interlayer dielectric layer to form the side of the gate layer and the gate dielectric layer away from the substrate, and the first interlayer dielectric layer on the side of the junction between the N-type source region and the P-type source region away from the substrate; the source metal interconnect layer is disposed on the same layer as the first interlayer dielectric layer and is respectively connected to the N-type source region and the P-type source region;

[0040] Using a deposition, photolithography, and etching process, an intermediate interlayer dielectric layer is formed on the side of the first interlayer dielectric layer and the source metal interconnect layer away from the substrate;

[0041] Using a photolithography and etching process, an N-type source via and a P-type source via are formed in the intermediate interlayer dielectric layer to respectively expose the N-type source region and the P-type source region, and to isolate the N-type source region and the P-type source region, and the etched intermediate interlayer dielectric layer is used as the second interlayer dielectric layer.

[0042] In a possible implementation, the forming of the source electrodes respectively connected to the N-type source region and the P-type source region between the total interlayer dielectric layers by using a deposition, photolithography, and etching process includes:

[0043] Using a deposition, photolithography, and etching process, the source metal interconnect layer disposed on the same layer as the first interlayer dielectric layer is formed in the vias and is respectively connected to the N-type source region and the P-type source region;

[0044] Using a deposition, photolithography, and etching process, the source metal layer covering the second interlayer dielectric layer and respectively connected to the source metal interconnect layer connected to the N-type source region and the source metal interconnect layer connected to the P-type source region is formed.

[0045] In a possible implementation, the width of the first interlayer dielectric layer on the side of the junction between the N-type source region and the P-type source region away from the substrate is greater than or equal to 1 μm.

[0046] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0047] Embodiments of the present application provide a semiconductor device and a manufacturing method thereof. The device includes: a substrate; an N-type drift layer on one side of the substrate; a P-type base region on the side of the N-type drift layer away from the substrate; an N-type source region and a P-type source region in the P-type base region; a gate trench between the N-type source region and the P-type source region; a gate dielectric layer at the bottom and sidewalls of the gate trench, and a gate layer filling the gate trench; a total interlayer dielectric layer on the side of the P-type base region away from the substrate; the total interlayer dielectric layer separates the N-type source region and the P-type source region; source electrodes located between the total interlayer dielectric layers and connected to the N-type source region and the P-type source region respectively; a drain on the side of the substrate away from the N-type drift layer. By separating the N-type source region and the P-type source region with the total interlayer dielectric layer in the present application, the electron current and the hole current can be detected respectively, so that when a failure occurs, it can be accurately determined whether there is a parasitic bipolar transistor conduction failure. At the same time, in the present application, the conventional gate structure is replaced with a trench-type gate structure, which can significantly reduce the device size, increase the current density, make the gate capacitance smaller, reduce the Miller effect of the device caused by the gate capacitance, enhance the dynamic characteristics of the device, and greatly reduce the on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0049] Combined with the drawings and referring to the following specific embodiments, the above and other features, advantages and aspects of the various embodiments of the present disclosure will become more obvious. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic, and the original components and elements are not necessarily drawn to scale.

[0050] Figure 1 FIG. shows a schematic diagram of a semiconductor device in the related art;

[0051] Figure 2 FIG. shows a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present application;

[0052] Figures 3 - 13 FIG. shows schematic diagrams of various structures in the manufacturing process of a semiconductor device provided by an embodiment of the present application;

[0053] Figure 14 FIG. shows a schematic diagram of a semiconductor device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0054] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe the specific embodiments of the present application in detail with reference to the accompanying drawings.

[0055] In the following description, many specific details are set forth to facilitate a thorough understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the spirit of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0056] As described in the background art, in the application of semiconductor devices, extreme working conditions such as unclamped inductive switching (UIS), short-circuit current, or surge current are often encountered. The above-mentioned working conditions will form a scenario where large voltage and large current coexist inside the device, resulting in very high power consumption of the device, generating a large amount of heat in a short time, and further causing the device to fail.

[0057] Currently, regarding the UIS failure mechanism of semiconductor devices, there are two viewpoints: high-temperature thermal failure and parasitic bipolar junction transistor (BJT) conduction failure, and there is no good method to distinguish between them.

[0058] Therefore, how to provide a semiconductor device that can accurately determine whether there is parasitic bipolar junction transistor conduction failure when a failure occurs is a technical problem that needs to be solved in the art.

[0059] Specifically, refer to Figure 1 As shown, it is a schematic diagram of a semiconductor device in the related art. It includes: a substrate 1, an N-type blocking layer 2 on one side of the substrate 1, a drain 11 on the other side of the substrate 1, an N-type drift layer 3 on the side of the N-type blocking layer 2 away from the substrate 1, a P-type base region 4 in the N-type drift layer 3, an N-type source region 5 and a P-type source region 6 in the P-type base region 4; a gate dielectric layer 7 on the side of the P-type base region 4 away from the substrate 1, a gate layer 8 on the side of the gate dielectric layer 7 away from the substrate 1, a total interlayer dielectric layer 9 on the side of the gate layer 8 away from the substrate 1, and a source electrode 10 on the side of the total interlayer dielectric layer 9 away from the substrate 1. The source electrode 10 is connected to both the N-type source region 5 and the P-type source region 6 at the same time. As a result, during the unclamped inductive switching S process, the electron current and the hole current will be mixed together and cannot be distinguished. It is impossible to determine whether there is a phenomenon of parasitic bipolar junction transistor conduction failure.

[0060] To solve the above technical problems, an embodiment of the present application provides a semiconductor device and a manufacturing method thereof. The device includes: a substrate; an N-type drift layer located on one side of the substrate; a P-type base region located on the side of the N-type drift layer away from the substrate; an N-type source region and a P-type source region located in the P-type base region; a gate trench located between the N-type source region and the P-type source region; a gate dielectric layer located at the bottom and sidewalls of the gate trench, and a gate layer filling the gate trench; a total interlayer dielectric layer located on the side of the P-type base region away from the substrate; the total interlayer dielectric layer separates the N-type source region and the P-type source region; source electrodes located between the total interlayer dielectric layers and connected to the N-type source region and the P-type source region respectively; a drain electrode located on the side of the substrate away from the N-type drift layer. By separating the N-type source region and the P-type source region with the total interlayer dielectric layer in the present application, the electron current and the hole current can be detected respectively, so that when a failure occurs, it can be accurately determined whether there is a parasitic bipolar transistor conduction failure. At the same time, in the present application, the conventional gate structure is replaced with a trench-type gate structure, which can significantly reduce the device size, increase the current density, make the gate capacitance smaller, reduce the Miller effect of the device caused by the gate capacitance, enhance the dynamic characteristics of the device, and greatly reduce the on-resistance.

[0061] Exemplary method

[0062] See Figure 2 As shown, it is a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present application, including:

[0063] S101: Provide a substrate 1.

[0064] In the embodiment of the present application, see Figure 3 As shown, it is a schematic diagram of the structure in the manufacturing process of a semiconductor device provided by an embodiment of the present application.

[0065] The substrate 1 provided in the embodiment of the present application may include a semiconductor substrate, for example, it may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator), or a GOI (Germanium On Insulator), etc. In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, GaN, InP, or SiC, etc., and may also be a stacked structure, such as Si / SiGe, etc., and may also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc. In this embodiment, the substrate 1 is made of SiC material.

[0066] As one of the most representative materials in the third-generation semiconductor materials, SiC has characteristics such as a wide bandgap, high thermal conductivity, and a large breakdown electric field. The bandgap of 4H-SiC material is approximately three times that of Si, and intrinsic excitation requires more energy, which enables SiC devices to withstand higher operating temperatures and also greatly improves the survival ability of SiC devices under extreme working conditions. Therefore, devices made of 4H-SiC materials, especially SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices, can be widely used in high-power equipment.

[0067] In the application of SiC MOSFETs, they often face extreme working conditions such as unclamped inductive switching (UIS), short-circuit current, and surge current. The above-mentioned working conditions will form a scenario where large voltage and large current exist simultaneously inside the device, resulting in very high power consumption of the device, generating a large amount of heat in a short time, and then causing the device to fail. The thermal conductivity and bandgap of SiC materials are three times higher than those of Si. Therefore, theoretically, they can withstand higher temperatures.

[0068] Specifically, the resistivity of the substrate 1 provided in the embodiments of the present application can be [0.01, 0.03] Ω·cm, and the thickness is [100, 500] μm.

[0069] S102: Form an N-type drift layer on one side of the substrate by using an epitaxial process.

[0070] S103: Use photolithography and ion implantation processes to form a P-type base region on the side of the N-type drift layer away from the substrate.

[0071] In the embodiments of the present application, as shown in Figure 3 it is possible to form an N-type drift layer 3 on one side of the substrate 1 by using an epitaxial process. Optionally, after providing the substrate 1 and before forming the N-type drift layer 3 on one side of the substrate 1 by using an epitaxial process, the method provided in the embodiments of the present application may further include:

[0072] Form an N-type blocking layer 2 between the substrate 1 and the N-type drift layer 3 by using an epitaxial process.

[0073] Specifically, the doping concentration of the N-type blocking layer 2 provided in the embodiments of the present application can be [1e17, 1e19] cm -3 , and the thickness is [0.3, 10] μm. By setting the N-type blocking layer 2, it is possible to prevent the electric field during reverse voltage withstand of the device from penetrating into the substrate 1 and changing the electric field distribution.

[0074] The doping concentration of the N-type drift layer 3 provided by the embodiment of the present application can be [5e14, 5e16] cm -3 , and the thickness is [8, 20] μm. By setting the N-type drift layer 3, it can withstand pressure during device operation, prevent voltage from damaging the device structure, and facilitate the epitaxial growth of subsequent film layers.

[0075] Then, in the embodiment of the present application, an epitaxial or ion implantation process can be used to form a P-type base region 4 on the side of the N-type drift layer 3 away from the substrate 1, so as to form a P-well.

[0076] Specifically, the junction depth of the P-type base region 4 provided by the embodiment of the present application can be [0.5, 1.0] μm, and the peak implantation concentration of the P-type base region 4 is [1e16, 3e17] cm -3 .

[0077] Specifically, the materials of the N-type blocking layer 2, the N-type drift layer 3, and the P-type base region 4 provided by the embodiment of the present application can be the same as the material of the substrate 1, that is, they can all be set to SiC materials.

[0078] S104: Use photolithography and ion implantation processes to form an N-type source region and a P-type source region in the P-type base region.

[0079] In the embodiment of the present application, as shown in Figure 4 , it is a schematic diagram of the structure in the manufacturing process of another semiconductor device provided by the embodiment of the present application.

[0080] Specifically, in the embodiment of the present application, an N-type source region 5 can be first formed in the P-type base region 4 by using photolithography and ion implantation processes. Specifically, N elements can be implanted in the embodiment of the present application to form the N-type source region 5.

[0081] The junction depth of the N-type source region 5 can be [0.1, 0.5] μm, and the junction depth of the N-type source region 5 is less than the junction depth of the P-type base region 4 [0.1, 1.5] μm, and the peak doping concentration can be [5e18, 5e20] cm -3 .

[0082] Then, a P-type source region 6 can be formed in the P-type base region 4 by using photolithography and ion implantation processes, that is, as shown in Figure 4 , a P-type source region 6 can be formed beside the N-type source region 5. Specifically, AL can be implanted in the embodiment of the present application + to form the P-type source region 6.

[0083] Optionally, the junction depth of the P-type source region 6 provided by the embodiment of the present application can be [1.0, 3.0] μm, and the peak implantation concentration of the P-type source region 6 can be [5e18, 5e21] cm -3In the embodiments of the present application, the junction depth of the P-type source region 6 is set to be relatively deep to protect the subsequently formed gate trench.

[0084] S105: Form a gate trench between the N-type source region and the P-type source region by using photolithography and etching processes.

[0085] S106: Form a gate dielectric layer on the bottom and sidewalls of the gate trench by using thermal oxidation or deposition processes, and form a gate layer by filling the gate trench by using deposition, photolithography, and etching processes.

[0086] In the embodiments of the present application, as shown in Figure 5 FIG., which is a schematic diagram of the structure in the manufacturing process of another semiconductor device provided by the embodiments of the present application.

[0087] Specifically, in the embodiments of the present application, a gate trench 70 can be formed between the N-type source region 5 and the P-type source region 6 by using photolithography and etching processes. Optionally, the depth of the gate trench 70 provided by the embodiments of the present application can be [0.5, 1.5] μm, and the width can be [0.3, 2.0] μm.

[0088] Then, a gate dielectric layer 7 can be formed on the bottom and sidewalls of the gate trench 70 by using thermal oxidation or deposition processes. Optionally, the thickness of the gate dielectric layer 7 provided by the embodiments of the present application can be [10, 100] nm, and can be specifically set according to the threshold voltage of the device.

[0089] Then, in the embodiments of the present application, a gate layer 8 can be formed by filling the gate trench 70 by using deposition, photolithography, and etching processes. The gate layer 8 is located on the side of the gate dielectric layer 7 away from the substrate 1. Optionally, the material of the gate layer 8 provided by the embodiments of the present application can be polysilicon, and the redundant polysilicon material on the device can be removed by photolithography and etching.

[0090] S107: Form a total interlayer dielectric layer on the side of the P-type base region away from the substrate by using deposition, photolithography, and etching processes; the total interlayer dielectric layer separates the N-type source region and the P-type source region.

[0091] In the embodiments of the present application, as shown in Figures 6 - 13 FIG., which is a schematic diagram of the structure in the manufacturing process of another semiconductor device provided by the embodiments of the present application.

[0092] Optionally, as shown in Figure 10 FIG., the total interlayer dielectric layer 95 provided by the embodiments of the present application can include a first interlayer dielectric layer 9 and a second interlayer dielectric layer 94; forming the total interlayer dielectric layer 95 on the side of the P-type base region 4 away from the substrate 1 by using deposition, photolithography, and etching processes provided by the embodiments of the present application can specifically include:

[0093] See Figure 6 As shown, in the embodiment of the present application, an initial interlayer dielectric layer 90 can be formed on the sides of the gate layer 8, the gate dielectric layer 7, the N-type source region 5, and the P-type source region 6 away from the substrate 1 by using deposition, photolithography, and etching processes. Optionally, the excess interlayer dielectric material is removed by photolithography and etching.

[0094] Then, see Figure 7 As shown, in the embodiment of the present application, a via hole 91 can be formed in the initial interlayer dielectric layer 90 by using photolithography and etching processes to form a first interlayer dielectric layer 9 on the sides of the gate layer 8 and the gate dielectric layer 7 away from the substrate 1, and on the side of the junction of the N-type source region 5 and the P-type source region 6 away from the substrate 1.

[0095] Specifically, the first interlayer dielectric layer 9 on the sides of the gate layer 8 and the gate dielectric layer 7 away from the substrate 1 extends beyond the two sides of the gate layer 8 and the gate dielectric layer 7 by a width of 0.5 μm, thereby protecting the device and preventing gate-source short circuit and gate-source leakage caused by process alignment deviation.

[0096] The width of the first interlayer dielectric layer 9 on the side of the junction of the N-type source region 5 and the P-type source region 6 away from the substrate 1 is not less than 1.0 μm to facilitate subsequent isolation of the N-type source region 5 and the P-type source region 6.

[0097] See Figure 8 As shown, the source metal interconnect layer 92 provided in the embodiment of the present application is disposed on the same layer as the first interlayer dielectric layer 9 and is respectively connected to the N-type source region 5 and the P-type source region 6. The manufacturing method of the source metal interconnect layer 92 is specifically described in detail later.

[0098] In addition, see Figure 9 As shown, in the embodiment of the present application, an intermediate interlayer dielectric layer 93 can be formed on the sides of the first interlayer dielectric layer 9 and the source metal interconnect layer 92 away from the substrate 1 by using deposition, photolithography, and etching processes.

[0099] The intermediate interlayer dielectric layer 93 and the first interlayer dielectric layer 9 provided in the embodiment of the present application can separate the source metal interconnect layers 92 corresponding to the N-type source region 5 and the P-type source region 6 above, so as to completely separate the hole current and the electron current, facilitating the study of the failure mechanism of the device under extreme working conditions.

[0100] Then, see Figure 10 and Figure 11 As shown, in the embodiment of the present application, an N-type source via hole and a P-type source via hole can be formed in the intermediate interlayer dielectric layer 93 by using photolithography and etching processes to respectively expose the N-type source region 5 and the P-type source region 6, isolate the N-type source region 5 and the P-type source region 6, and use the etched intermediate interlayer dielectric layer 93 as the second interlayer dielectric layer 94.

[0101] S108: Use deposition, photolithography, and etching processes to form source electrodes respectively connected to the N-type source region and the P-type source region between the total interlayer dielectric layers; use laser annealing, metal thickening, and deposition processes to form a drain electrode on the side of the substrate away from the N-type drift layer.

[0102] In the embodiment of the present application, as shown in Figure 12 and Figure 13 it is possible to use deposition, photolithography, and etching processes to form source electrodes 96 respectively connected to the N-type source region 5 and the P-type source region 6 between the total interlayer dielectric layers 95.

[0103] Optionally, the source electrode 96 provided in the embodiment of the present application may include: a source metal interconnect layer 92 and a source metal layer 10.

[0104] The formation of the source electrode 96 respectively connected to the N-type source region 5 and the P-type source region 6 between the total interlayer dielectric layers 95 by using deposition, photolithography, and etching processes provided in the embodiment of the present application may include:

[0105] As shown in Figure 8 it is possible to use deposition, photolithography, and etching processes to form a source metal interconnect layer 92 disposed on the same layer as the first interlayer dielectric layer 9 in the via 91, which is respectively connected to the N-type source region 5 and the P-type source region 6. That is, in the embodiment of the present application, the thicknesses of the first interlayer dielectric layer 9 and the source metal interconnect layer 92 may be similar.

[0106] As shown in Figure 12 and 13 it is possible to use deposition, photolithography, and etching processes to form a source metal layer 10 covering the second interlayer dielectric layer 94, which is respectively connected to the source metal interconnect layer 92 connected to the N-type source region 5 and the source metal interconnect layer 92 connected to the P-type source region 6.

[0107] Then, as shown in Figure 14 it is possible to use laser annealing, metal thickening, and deposition processes to form a drain electrode 11 on the side of the substrate 1 away from the N-type drift layer 3. A MOSFET device for distinguishing electron and hole currents is manufactured.

[0108] Optionally, the semiconductor device corresponding to the embodiment of the present application may include, but is not limited to, a planar MOSFET, a planar Insulated-Gate Bipolar Transistor (IGBT), and a JBS (Junction Barrier Schottky).

[0109] An embodiment of the present application provides a method for manufacturing a semiconductor device. The device manufactured by applying this method includes: a substrate; an N-type drift layer located on one side of the substrate; a P-type base region located on the side of the N-type drift layer away from the substrate; an N-type source region and a P-type source region located in the P-type base region; a gate trench located between the N-type source region and the P-type source region; a gate dielectric layer located at the bottom and sidewalls of the gate trench, and a gate layer filling the gate trench; a total interlayer dielectric layer located on the side of the P-type base region away from the substrate; the total interlayer dielectric layer separates the N-type source region and the P-type source region; source electrodes located between the total interlayer dielectric layers and connected to the N-type source region and the P-type source region respectively; and a drain electrode located on the side of the substrate away from the N-type drift layer. By separating the N-type source region and the P-type source region with the total interlayer dielectric layer, the present application can detect the electron current and the hole current respectively, so that when a failure occurs, it can accurately determine whether there is a parasitic bipolar transistor conduction failure. At the same time, the present application replaces the conventional gate structure with a trench-type gate structure, which can significantly reduce the device size, increase the current density, make the gate capacitance smaller, reduce the Miller effect of the device caused by the gate capacitance, enhance the dynamic characteristics of the device, and greatly reduce the on-resistance.

[0110] Exemplary device

[0111] See Figure 14 As shown, it is a schematic diagram of a semiconductor device provided by an embodiment of the present application, including:

[0112] Substrate 1;

[0113] An N-type drift layer 3 located on one side of the substrate 1;

[0114] A P-type base region 4 located on the side of the N-type drift layer 3 away from the substrate 1; an N-type source region 5 and a P-type source region 6 located in the P-type base region 4;

[0115] A gate trench located between the N-type source region 5 and the P-type source region 6;

[0116] A gate dielectric layer 7 located at the bottom and sidewalls of the gate trench, and a gate layer 8 filling the gate trench;

[0117] A total interlayer dielectric layer 95 located on the side of the P-type base region 5 away from the substrate 1; the total interlayer dielectric layer 95 separates the N-type source region 5 and the P-type source region 6;

[0118] Source electrodes 96 located between the total interlayer dielectric layers 95 and connected to the N-type source region 5 and the P-type source region 6 respectively; a drain electrode 11 located on the side of the substrate 1 away from the N-type drift layer 3.

[0119] In a possible implementation manner, it further includes:

[0120] The N-type blocking layer 2 located between the N-type drift layer 3 and the substrate 1.

[0121] In a possible implementation, the total interlayer dielectric layer 95 includes: a first interlayer dielectric layer 9 and a second interlayer dielectric layer 94; the total interlayer dielectric layer 95 isolates the N-type source region 5 and the P-type source region 6, including:

[0122] The first interlayer dielectric layer 9 is located on the side of the gate dielectric layer 7 and the gate layer 8 away from the substrate 1, and is located on the side of the junction of the N-type source region 5 and the P-type source region 6 away from the substrate 1;

[0123] The second interlayer dielectric layer 94 is located on the side of the P-type source region 6 away from the substrate 1 in the region where the N-type source region 5 is connected, connects the first interlayer dielectric layer 9, covers the P-type source region 6 and exposes the N-type source region 5 to isolate the N-type source region 5 and the P-type source region 6;

[0124] The second interlayer dielectric layer 94 is located on the side of the N-type source region 5 away from the substrate 1 in the region where the P-type source region 6 is connected, connects the first interlayer dielectric layer 9, covers the N-type source region 5 and exposes the P-type source region 6 to isolate the N-type source region 5 and the P-type source region 6.

[0125] In a possible implementation, the source electrode 96 includes: a source electrode metal interconnect layer 92 and a source electrode metal layer 10;

[0126] The source electrode metal interconnect layer 92 is arranged on the same layer as the first interlayer dielectric layer 9 and is respectively connected to the N-type source region 5 and the P-type source region 6;

[0127] The source electrode metal layer 10 covers the second interlayer dielectric layer 94 and is respectively connected to the source electrode metal interconnect layer 92 connected to the N-type source region 5 and the source electrode metal interconnect layer 92 connected to the P-type source region 6.

[0128] In a possible implementation, the shapes of the N-type source region 5 and the P-type source region 6 include square, hexagonal or strip-shaped.

[0129] An embodiment of the present application provides a semiconductor device. The device manufactured by applying this method includes: a substrate; an N-type drift layer located on one side of the substrate; a P-type base region located on the side of the N-type drift layer away from the substrate; an N-type source region and a P-type source region located in the P-type base region; a gate trench located between the N-type source region and the P-type source region; a gate dielectric layer located at the bottom and sidewalls of the gate trench, and a gate layer filling the gate trench; a total interlayer dielectric layer located on the side of the P-type base region away from the substrate; the total interlayer dielectric layer separates the N-type source region and the P-type source region; source electrodes located between the total interlayer dielectric layers and connected to the N-type source region and the P-type source region respectively; a drain located on the side of the substrate away from the N-type drift layer. By separating the N-type source region and the P-type source region with the total interlayer dielectric layer in the present application, the electron current and the hole current can be detected respectively, so that when a failure occurs, it can be accurately determined whether there is a parasitic bipolar transistor conduction failure. At the same time, the present application replaces the conventional gate structure with a trench-type gate structure, which can significantly reduce the device size, increase the current density, make the gate capacitance smaller, reduce the Miller effect of the device caused by the gate capacitance, enhance the dynamic characteristics of the device, and greatly reduce the on-resistance.

[0130] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key point of each embodiment is to illustrate the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment.

[0131] The above description is only a preferred embodiment of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the protection of the technical solution of the present application.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; An N-type drift layer located on one side of the substrate; A P-type base region located on the side of the N-type drift layer away from the substrate; An N-type source region and a P-type source region located in the P-type base region; A gate trench located between the N-type source region and the P-type source region; A gate dielectric layer located at the bottom and sidewalls of the gate trench, and a gate layer filling the gate trench; A total interlayer dielectric layer located on the side of the P-type base region away from the substrate; The total interlayer dielectric layer isolates the N-type source region and the P-type source region; Source electrodes located between the total interlayer dielectric layers and respectively connected to the N-type source region and the P-type source region; A drain located on the side of the substrate away from the N-type drift layer.

2. The device according to claim 1, characterized in that, Further comprising: An N-type blocking layer located between the N-type drift layer and the substrate.

3. The device according to claim 1, characterized in that, The total interlayer dielectric layer includes: a first interlayer dielectric layer and a second interlayer dielectric layer; the total interlayer dielectric layer isolates the N-type source region and the P-type source region, including: The first interlayer dielectric layer is located on the side of the gate layer and the gate dielectric layer away from the substrate, and is located on the side of the junction of the N-type source region and the P-type source region away from the substrate; The second interlayer dielectric layer is located on the side of the P-type source region away from the substrate in the region where the N-type source region is connected, connects the first interlayer dielectric layer to cover the P-type source region and expose the N-type source region to isolate the N-type source region and the P-type source region; The second interlayer dielectric layer is located on the side of the N-type source region away from the substrate in the region where the P-type source region is connected, connects the first interlayer dielectric layer to cover the N-type source region and expose the P-type source region to isolate the N-type source region and the P-type source region.

4. The device according to claim 3, characterized in that, The source electrode includes: a source metal interconnect layer and a source metal layer; The source metal interconnect layer is disposed on the same layer as the first interlayer dielectric layer and is respectively connected to the N-type source region and the P-type source region; The source metal layer covers the second interlayer dielectric layer and is respectively connected to the source metal interconnect layer connected to the N-type source region and the source metal interconnect layer connected to the P-type source region.

5. The device according to claim 1, characterized in that, The shapes of the N-type source region and the P-type source region include square, hexagonal or strip-shaped.

6. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a substrate; Forming an N-type drift layer on one side of the substrate by an epitaxial process; Forming a P-type base region on the side of the N-type drift layer away from the substrate by an epitaxial or ion implantation process; Forming an N-type source region and a P-type source region in the P-type base region by a photolithography and ion implantation process; Forming a gate trench between the N-type source region and the P-type source region by a photolithography and etching process; Forming a gate dielectric layer at the bottom and sidewalls of the gate trench by a thermal oxidation or deposition process, and filling the gate trench to form a gate layer by a deposition, photolithography and etching process; Forming a total interlayer dielectric layer on the side of the P-type base region away from the substrate by a deposition, photolithography and etching process; The total interlayer dielectric layer isolates the N-type source region and the P-type source region; By using deposition, photolithography, and etching processes, source electrodes respectively connected to the N-type source region and the P-type source region are formed between the total interlayer dielectric layers. By using laser annealing, metal thickening, and deposition processes, a drain electrode is formed on the side of the substrate away from the N-type drift layer.

7. The method according to claim 6, characterized in that, After providing the substrate and before forming the N-type drift layer on one side of the substrate by using the epitaxial process, the following steps are further included: An N-type blocking layer is formed between the substrate and the N-type drift layer by using the epitaxial process.

8. The method according to claim 6, characterized in that, The source electrode includes a source metal interconnect layer and a source metal layer; the total interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer. The steps of forming the total interlayer dielectric layer on the side of the P-type base region away from the substrate by using deposition, photolithography, and etching processes include: An initial interlayer dielectric layer is formed on the sides of the gate layer, the gate dielectric layer, the N-type source region, and the P-type source region away from the substrate by using deposition, photolithography, and etching processes. Via holes are formed in the initial interlayer dielectric layer by using photolithography and etching processes to form the first interlayer dielectric layer on the sides of the gate layer and the gate dielectric layer away from the substrate, and at the junction of the N-type source region and the P-type source region away from the substrate; the source metal interconnect layer is arranged on the same layer as the first interlayer dielectric layer and is respectively connected to the N-type source region and the P-type source region. An intermediate interlayer dielectric layer is formed on the sides of the first interlayer dielectric layer and the source metal interconnect layer away from the substrate by using deposition, photolithography, and etching processes. N-type source via holes and P-type source via holes are formed in the intermediate interlayer dielectric layer by using photolithography and etching processes to respectively expose the N-type source region and the P-type source region, isolate the N-type source region and the P-type source region, and use the etched intermediate interlayer dielectric layer as the second interlayer dielectric layer.

9. The method according to claim 8, wherein, The steps of forming the source electrodes respectively connected to the N-type source region and the P-type source region between the total interlayer dielectric layers by using deposition, photolithography, and etching processes include: The source metal interconnect layer arranged on the same layer as the first interlayer dielectric layer is formed in the via holes by using deposition, photolithography, and etching processes and is respectively connected to the N-type source region and the P-type source region. The source metal layer covering the second interlayer dielectric layer and respectively connected to the source metal interconnect layer connected to the N-type source region and the source metal interconnect layer connected to the P-type source region is formed by using deposition, photolithography, and etching processes.

10. The method according to claim 8, wherein, The width of the first interlayer dielectric layer at the junction of the N-type source region and the P-type source region away from the substrate is greater than or equal to 1 μm.

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