3D IC MBIST test method based on intelligent algorithm

Abstract

The invention belongs to the technical field of testability design of integrated circuits, and discloses a 3D IC MBIST test method based on an intelligent algorithm, and the method comprises the steps: carrying out the isomorphic grouping through analyzing the space coordinates, hierarchical affiliation and multi-dimensional attributes of a memory; establishing a three-dimensional layout relationship based on the improved interlayer distance model; the hierarchical clustering algorithm is adopted to merge memory clusters according to spatial proximity, and a grouping architecture with the minimum controller number is constructed; a dynamic test scheduling model is established in combination with a multi-target simulated annealing algorithm, and test time is optimized under power consumption constraint through a temperature attenuation mechanism. According to the method, three-dimensional collaborative optimization is carried out on spatial layout, time sequence constraint and power consumption budget, the contradiction between area overhead and test efficiency of a traditional memory built-in self-test scheme in a 3D IC is solved, and lamination test challenges under the condition that the test temperature is limited are effectively handled; and the test economy and reliability of the heterogeneous integrated chip are obviously improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit testability design, and in particular relates to a 3D IC MBIST test method based on an intelligent algorithm. Background Art

[0002] With the increasing complexity of modern integrated circuit design, the widespread use of embedded memory has made memory testing costs account for a significant proportion of integrated circuit manufacturing costs. To meet this challenge, built-in self-test technology has become a mainstream solution. Its core mechanism is to generate test vectors and verify memory functions through a built-in MBIST controller. However, this technology will introduce additional chip area overhead due to auxiliary circuits such as controllers. This contradiction is particularly prominent in the design of three-dimensional integrated circuits (3D ICs). Since 3D ICs require pre-bond testing (Pre-bond) and post-bond testing before stacking, and each test stage is limited by power consumption, and post-stack testing is limited by the number of through-silicon vias (TSVs), traditional BIST solutions face a double dilemma in terms of test scheduling flexibility and resource optimization.

[0003] Built-In Self-Test (BIST) is a built-in test mechanism of integrated circuits that allows memory to perform self-test without relying on external test equipment. BIST can effectively improve the efficiency and reliability of memory production testing and is usually used in large-scale integrated circuits (such as DRAM, SRAM, etc.). The memory built-in self-test (BIST) process includes two key parts: memory grouping and scheduling. Memory grouping divides memory cells or modules into several groups according to function, structure or test requirements to improve test efficiency and parallelism. Each group is tested independently, and a suitable test method can be selected according to the characteristics of the memory cell; memory scheduling reasonably arranges the test order and execution timing of each group according to the priority of the test task and the constraints of hardware resources. In the scheduling process, it is necessary to comprehensively consider the test power consumption, temperature, parallel execution of the test, and resource management of the task to ensure that the test process is efficient and smooth. By optimizing grouping and scheduling, memory BIST can effectively shorten the test time, improve the test coverage, and reduce production costs.

[0004] DFT engineers need to balance the number of MBIST controllers and the complexity of the test network while meeting the test coverage. On the one hand, intelligent grouping is required to reduce the redundant deployment of the test circuit. On the other hand, a dynamic scheduling strategy needs to be constructed to reduce the test time under constraints, so as to achieve the optimal balance between test time and area overhead. This multi-objective optimization process is essentially a three-dimensional coordination of spatial layout, timing constraints, and power consumption budget. Although existing research has optimized the test time through memory grouping and test scheduling, the test of three-dimensional structured memories is constrained by test power consumption and has problems such as high test temperature, making it difficult to obtain an optimal grouping method and test order. Therefore, how to reduce the number of groups to reduce the area overhead and how to adjust the test order to reduce the test time are also difficult problems to be solved urgently. Summary of the Invention

[0005] To solve the above technical problems, the present invention provides a 3D IC MBIST test method based on an intelligent algorithm, which optimizes the memory test process of 3D ICs, reduces the test grouping, thereby reducing the circuit area overhead, and adjusts the test order to reduce the test time.

[0006] A 3D IC MBIST test method based on an intelligent algorithm according to the present invention includes the following steps: Step 1: Extract the spatial coordinate information of the memories and analyze the hierarchical attribution of each memory; Step 2: Extract the multi-dimensional attributes of each memory, and divide the memories into homogeneous sets based on the attribute consistency of the memories; Step 3: Calculate the inter-layer distance between each memory and other memories based on an improved inter-layer distance model; Step 4: Use the hierarchical clustering algorithm to group the memories based on the inter-layer distance of the memories and allocate shared BIST controllers; Step 5: Use the multi-objective simulated annealing algorithm to define the constraint conditions and optimization objective function of the memory test task, and solve to obtain the minimum test time.

[0007] Further, Step 1 is specifically as follows: Read in the memory design.v file and the memory physical location.def file, analyze the 3D IC physical layout file, obtain the memory coordinates and hierarchical attribution information, and model the three-dimensional distribution of the memories.

[0008] Further, Step 2 is specifically as follows: Read in the memory power domain.upf file, the clock domain.clk file, the address bit width test algorithm.lvlib file, read the memory constraints, and the TSV constraints.spec file, extract the multi-dimensional attributes of the memories; classify based on the multi-dimensional attributes of the memories to form a homogeneous memory set.

[0009] Further, in step 3, the improved interlayer distance model is as follows: , where θ is the interlayer distance conversion coefficient, , Z is the number of intervening layers; X i , Y i represents the spatial coordinates of memory i, and X j , Y j represents the spatial coordinates of memory j.

[0010] Further, step 4 is specifically as follows: Calculate the distances between all memories, and sequentially select two clusters with the smallest distances for merging; during each merging process, determine whether the total power consumption after merging exceeds the maximum power consumption requirement; if so, abandon the merging; if not, perform the merging operation and update the distances of the new clusters.

[0011] Further, in step 5, the objective function and constraints are defined as follows: Objective function: , where C is the minimized test time; Power consumption constraint: , the power consumption P of the memories under parallel testing shall not exceed the given maximum power consumption P max , Temperature constraint: , the temperature T of the memories under parallel testing shall not exceed the given maximum chip test temperature T max ; where n is the total number of memories.

[0012] Further, in step 5, the objective function is solved as follows: Step 5-1: Randomly generate a test schedule for the memories, and set the initial temperature , cooling rate and the maximum number of iterations ; Step 5-2: Randomly change the test order of the memories to generate a neighborhood solution, compare the test time of the new solution with that of the current solution. If the test time obtained from the new neighborhood solution is less than that of the current solution, accept the solution; otherwise, accept the solution with a certain probability. The probability calculation formula is as follows: , where is the test time of the neighborhood solution, is the test time of the current solution, is the current temperature; Step 5-3: For each new solution, check whether it satisfies the power consumption and temperature constraints; if the constraints are not satisfied, reject it; if the maximum number of iterations When the temperature T drops to the preset threshold, the algorithm terminates and outputs the optimal solution, that is, the solution that minimizes the test time under the power consumption and temperature constraints.

[0013] The beneficial effects of the present invention are as follows: In view of the special requirements of 3D ICs and heterogeneous integrated chips, the present invention establishes a three-dimensional layout relationship based on an improved interlayer distance model, calculates the interlayer distance of the memory, and uses a hierarchical clustering algorithm to merge memory clusters according to spatial proximity to construct a grouping architecture that minimizes the number of controllers; the present invention groups memories in combination with spatial distribution, reduces the deployment of MBIST controllers and test networks, thereby effectively reducing the chip area overhead, reducing the number of controllers and the complexity of the test circuit, being able to arrange test tasks more reasonably, reducing redundant tests, reducing the test time, and helping to save the cost of chip manufacturing. The present invention combines a multi-objective simulated annealing algorithm to establish a dynamic test scheduling model, optimizes the test time under power consumption constraints through a temperature decay mechanism, provides a flexible phased optimization method, enables the memory test process to be dynamically adjusted according to different constraint conditions in practical applications, and has strong adaptability and flexibility. The present invention can ensure that the test task is completed during the test process under the power consumption and temperature constraints through an accurate power consumption and temperature control mechanism, and avoids hardware damage or performance degradation caused by excessive power consumption and temperature. The method of the present invention innovatively performs three-dimensional collaborative optimization of spatial layout, timing constraints, and power consumption budget, supports adaptive test sequence adjustment and dynamic evaluation of neighborhood solutions, effectively copes with the stacked test challenges under the limited test temperature conditions, significantly improves the test economy and reliability of heterogeneous integrated chips, and is applicable to more complex integrated circuit designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic flowchart of the method of the present invention; Figure 2 is a memory test architecture diagram of an embodiment of the present invention based on the IEEE1687 protocol; Figure 3 is a schematic diagram of dividing a homogeneous set by reading multi-dimensional attributes; Figure 4 is a schematic diagram of the hierarchical clustering algorithm; Figure 5 is a schematic diagram of 3D IC memory grouping divided based on the hierarchical clustering algorithm; Figure 6 is a test scheduling optimization task definition diagram; Figure 7 is an MBIST test flowchart. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] To make the content of the present invention easier to be clearly understood, the following further detailed description of the present invention will be given according to specific embodiments in conjunction with the accompanying drawings.

[0016] As Figure 1 shown, a 3D IC MBIST test method based on an intelligent algorithm according to the present invention includes the following steps: Step 1: Read in the memory design.v file and the memory physical location.def file, parse the 3D IC physical layout file, extract the spatial coordinate information of the memory, and parse the hierarchical attribution of each memory; Step 2: Read in the memory power domain.upf file, the clock domain.clk file, the address bit width test algorithm.lvlib file, read the memory constraints, and the TSV constraints.spec file, extract the multi-dimensional attributes of each memory, including the power domain, the clock domain, the address bit width, and the test algorithm, etc.; according to the attribute consistency of the memory, divide the memory into homogeneous sets; memories with different power domains, clock domains, address bit widths, or test algorithms cannot be grouped into the same controller group; Step 3: Based on the improved inter-layer distance model, calculate the inter-layer distance between each memory and other memories; the improved inter-layer distance model is: , where θ is the inter-layer distance conversion coefficient, , Z is the number of intervening layers; X i , Y i represents the spatial coordinates of memory i, X j , Y j represents the spatial coordinates of memory j; Step 4: Adopt the hierarchical clustering algorithm (in a bottom-up manner) to group the memories, gradually merge similar memory clusters; based on the distance between the memories, select the most similar clusters for merging until the maximum power consumption requirement is met, group the memories and allocate shared BIST controllers; Step 5: Use the multi-objective simulated annealing algorithm to define the constraint conditions and the optimization objective function of the memory test task, and solve to obtain the minimum test time.

[0017] Among them, in Step 5, initialize the algorithm parameters, define the neighborhood structure and the acceptance criterion. Randomly generate the test schedule of the memory, set the initial temperature , the cooling rate and the maximum number of iterations ; generate a neighborhood solution by changing the test order of the memory, compare the test time of the new solution with the current solution, and select a better solution; for solutions that do not meet the power consumption and temperature constraints, reject the solution.

[0018] During each iteration, update the temperature according to the set cooling rate: , is the updated temperature, is the current temperature; if the maximum number of iterations is reached or the temperature T drops to a certain minimum value (i.e., the preset value), the algorithm terminates; output the optimal solution, that is, the solution that minimizes the test time under the constraints of power consumption and temperature.

[0019] The method of the present invention can effectively reduce the number of groups of 3D IC MBIST controllers, thereby reducing the chip area overhead, effectively optimizing the test scheduling, and reducing the test time under the constraints of power consumption and temperature.

[0020] The method of the present invention is based on the standard structure of memory built-in self-test of IEEE1687. As Figure 2 shown, the MBIST architecture consists of multiple key components, including Segment Insertion Bit (SIB), built-in self-test access port (BAP), Controller, and the connected Memory. They work together to complete the self-test task of the storage unit. The SIB is responsible for coordinating the work between components to ensure the smooth transmission of data and control signals; the BAP is responsible for generating test patterns and data, performing test tasks, and feeding back the test results to the controller; the controller is the core of the MBIST system, generating test addresses, data, and control signals for the storage unit and passing them to the memory; the memory receives these control signals, performs tests, and returns the output data to the controller for comparison and analysis. Multiple memories can share one MBIST controller, thereby improving the test efficiency and reducing the area and power consumption. Through this collaborative work, MBIST can effectively detect faults in the storage unit and improve the reliability and quality of the chip. In the existing design, a single MBIST controller can control multiple storage units, thereby optimizing the area and power consumption of the chip. Since the MBIST circuit is an auxiliary test circuit, theoretically, its use should be minimized as much as possible to save chip area and improve the design efficiency; however, how to effectively plan and group the storage units distributed at different positions on the chip and allocate them to different MBIST controllers is a complex design problem that requires comprehensive consideration of multiple factors, such as area, test power consumption, timing requirements, and the structural characteristics of the memory; memories with different parameters such as clock domain, power domain, and test algorithm cannot be tested using the same controller. As Figure 3 shown, the memory units of the 3D IC are divided according to these different parameters.

[0021] There are significant differences in structure, performance, and connection methods between three-dimensional integrated circuits and two-dimensional integrated circuits. In a two-dimensional integrated circuit, all circuit elements and memory cells are usually arranged in a planar manner on the same layer and connected through metal interconnections. In contrast, a 3D IC vertically stacks multiple chips or functional layers and uses TSV technology to achieve high-speed connections between different layers. TSV technology enables the memory cells in different layers to be directly connected through tiny vias that vertically penetrate the silicon wafer, thus achieving more efficient data transmission. In comparison, in a 2D IC, the memory and controller need to be interconnected through long metal lines, resulting in increased signal transmission delay and power consumption. In a 3D IC, since the memory cells are connected through TSVs, multiple memory layers can operate sharing the same controller for management. This not only reduces the number of control circuits but also decreases the chip area and power consumption, improving the overall system performance and response speed. However, it is necessary to define the distance between memories across different layers to avoid timing issues caused by excessive physical distance; thus, the distance between memory i and memory j is defined , where θ is the interlayer distance conversion coefficient (θ ≥ 1), and Z is the number of intervening layers (for example, if layer0 and layer1 differ by one layer, Z = 1); moreover, due to the multi-layer stacked design of three-dimensional stacked chips, the dense stacking between chips in each layer limits the heat dissipation channels, resulting in heat being more likely to accumulate inside the chip, thereby affecting the working stability and performance of the chip. To effectively control and manage the temperature of the chip and avoid test failures or damage caused by overheating, it is necessary to add a maximum test temperature limit to the memory scheduling

[0022] As Figure 4 shown, in the bottom-up hierarchical clustering process, each memory cell is initially regarded as an independent cluster, that is, each memory cell occupies a separate cluster. First, calculate the distances between all memory cells and select the two clusters with the smallest distance for merging; when merging, it is necessary to check the total power consumption of the newly formed cluster , if the total power consumption of the new cluster exceeds the power consumption constraint pre-bond power consumption, the merge is not allowed; if the power consumption of the merged cluster meets the constraint, then perform the merge operation and update the distance of the new cluster. Each time a merge occurs, record the two clusters being merged as well as the power consumption and distance after the merge, which helps to track the clustering process and the final clustering result. This process is continuously repeated until all memory cells are clustered into appropriate groups and the total power consumption of each group meets the power consumption constraint. The entire clustering process continues until the target clustering structure is reached and the power consumption limit is met. As Figure 5 shown, it is a schematic diagram of memory clustering and grouping. Memories of the same color belong to the same cluster and share the same controller

[0023] As Figure 6As shown in the figure, the horizontal direction of memories M1 - M10 is defined as the test time required for the memory test task, the vertical direction is the total test power consumption in the same test sequence, and the depth direction represents the test temperature in the same test sequence. All memories are three - dimensionalized. The horizontal, vertical, and depth directions respectively represent the test time, test power consumption, and the resulting test temperature required for testing this memory. Memories of the same color are those controlled by the same controller. First, define the objective function and constraints. Take the total time of the test process as the optimization objective, and the goal is to reduce the test time by reasonably arranging the test sequence of memories. The constraints are power consumption constraints. Each time a memory is tested, the power consumption should not exceed the set maximum power consumption limit and temperature constraints. The heat generated during the test process should not cause the chip temperature to exceed a certain preset temperature limit . Initialize the algorithm parameters , the cooling rate is used to control the rate of temperature drop. The cooling rate determines the convergence rate of the algorithm and the maximum number of iterations . Randomly generate a set of initial solutions, and then generate neighborhood solutions by randomly swapping the test sequences of two memories or adding other memories in a test cycle. The acceptance criterion for the new solution is based on the idea of simulated annealing. If the new solution is better than the current solution (i.e., the test time is shorter and the power consumption and temperature meet the constraints), then accept this solution; if the quality of the new solution is worse (i.e., the test time is longer), then accept the new solution with a certain probability, and this probability decreases as the temperature drops. The probability calculation formula is . For each new solution, check whether it meets the power consumption and temperature constraints. If the constraints are not met, this solution will be rejected; in each iteration, reduce the temperature T. Usually, the following formula is used to reduce the temperature: , and α usually takes values between 0.8 and 0.99. If the maximum number of iterations is reached, or when the temperature T drops to a certain minimum value, the algorithm terminates and outputs the optimal solution, that is, the solution that minimizes the test time under the condition of meeting the power consumption and temperature constraints. As Figure 7 shown, the test scheduling results are as follows: Controller 1: Step 1 (M1, M4, M8); Controller 2: Step 1 (M10); Controller 3: Step 1 (M2, M5, M3), Step 2 (M7); Controller 4: Step 1 (M6, M9).

[0024] From Figure 7 it can be seen that the method described in the present invention optimizes the memory test scheduling and effectively reduces the test time.

[0025] The above are only the preferred embodiments of the present invention and are not intended as a further limitation of the present invention. All equivalent changes made by using the content of the specification and drawings of the present invention are within the protection scope of the present invention.

Claims

1. A 3D IC MBIST test method based on an intelligent algorithm, characterized in that: The following steps are involved: Step 1: Extract the spatial coordinate information of the memory and analyze the hierarchical affiliation of each memory; Step 2: Extract the multi-dimensional attributes of each memory and divide the memory into homogeneous sets based on the consistency of the memory attributes; Step 3: Based on the improved inter-layer distance model, calculate the inter-layer distance between each memory and other memories; Step 4: Using a hierarchical clustering algorithm, the memories are grouped based on the distance between memory layers and a shared BIST controller is assigned; Step 5: Use a multi-objective simulated annealing algorithm to define the constraints of the memory test task and the optimization objective function, and solve them to obtain the minimum test time.

2. a kind of 3D IC MBIST method of testing based on intelligent algorithm according to claim 1, is characterized in that, Step 1 is as follows: read in the memory design .v file and the memory physical location .def file, parse the 3D IC physical layout file, obtain the memory coordinates and hierarchical attribution information, and model the three-dimensional distribution of the memory.

3. a kind of 3D IC MBIST method of testing based on intelligent algorithm according to claim 2, is characterized in that, Step 2 is as follows: Read the memory power domain .upf file, clock domain .clk file, address width test algorithm .lvlib file, read the memory constraints, TSV constraints .spec file, and extract the multi-dimensional attributes of the memory; classify the memory based on its multi-dimensional attributes to form a homogeneous memory set.

4. a kind of 3D IC MBIST method of testing based on intelligent algorithm according to claim 3, it is characterized in that, In step 3, the improved interlayer distance model is: ， Where θ is the inter-layer distance conversion coefficient, , Z is the number of interval layers; X i ,Y i represents the spatial coordinates of memory i, X j ,Y j Represents the spatial coordinates of memory j.

5. a kind of 3D IC MBIST method of testing based on intelligent algorithm according to claim 4, it is characterized in that, Step 4 is as follows: Calculate the distances between all memories, and select two clusters with the smallest distances to merge in turn; In each merging process, it is determined whether the total power consumption after merging exceeds the maximum power consumption requirement; if so, the merging is abandoned; if not, the merging operation is performed and the distance of the new cluster is updated.

6. a kind of 3D IC MBIST method of testing based on intelligent algorithm according to claim 5, it is characterized in that, In step 5, the objective function and constraints are defined as follows: Objective function: , C is the minimum test time; Power Constraints: , the power consumption P of the memory tested in parallel shall not exceed the given maximum power consumption P max , Temperature constraints: , the temperature T of the memory tested in parallel shall not exceed the given maximum chip test temperature T max ; Where n is the total number of memories.

7. a kind of 3D IC MBIST method of testing based on intelligent algorithm according to claim 6, is characterized in that, In step 5, the objective function is solved, specifically: Step 5-1: Randomly generate memory test schedule and set initial temperature , cooling rate and the maximum number of iterations ; Step 5-2: Randomly change the test order of the memory to generate a neighborhood solution, compare the test time of the new solution with the test time of the current solution, and accept the solution if the test time of the new neighborhood solution is less than the test time of the current solution; otherwise, accept the solution with a certain probability. The probability calculation formula is as follows: ， in, is the test time of the neighborhood solution, is the test time of the current solution, is the current temperature; Step 5-3: For each new solution, check whether it meets the power consumption and temperature constraints; if the constraints are not met, reject; if the maximum number of iterations is reached , or when the temperature T drops to a preset threshold, the algorithm terminates and outputs the optimal solution, that is, the solution that minimizes the test time while satisfying the power consumption and temperature constraints.

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