Test method and system for chip simulation model

Abstract

The invention relates to the technical field of chip design, in particular to a test method and system for a chip simulation model. The method comprises the following steps: acquiring chip data, and performing chip circuit logic analysis to obtain circuit logic data; performing signal transmission simulation based on the circuit logic data to obtain signal transmission data; constructing a chip simulation model according to the circuit logic data and the signal transmission data; performing particle bombardment on the chip simulation model to obtain particle data; performing energy spectrum classification based on the particle data to obtain proton data and heavy ion data; performing single event upset fault analysis on the chip simulation model according to the proton data to obtain single event upset data; and performing multi-particle upset fault analysis on the chip simulation model according to the heavy ion data to obtain multi-particle upset fault data. The reliability of the chip in the radiation environment is evaluated and optimized based on the chip design technology, so that the radiation resistance of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and particularly to a test method and system for a chip simulation model. Background Art

[0002] Traditional test methods and systems for chip simulation models have some drawbacks. They usually focus on single particle effects (such as single event upsets), ignoring the influence of multi-particle interaction effects (MPIU), resulting in an inability to comprehensively evaluate the behavior of chips in complex radiation environments. The particle trajectory simulation of traditional methods is relatively simple, lacking an accurate modeling of the electromagnetic interaction between particles, so there are large errors in the prediction of multi-particle upsets and interaction effects. Traditional simulation tools often rely on simplified irradiation models and fail to fully consider the variability of actual radiation environments such as irradiation dose and particle energy distribution, resulting in test results lacking authenticity and accuracy. Traditional test methods inadequately consider the integration of chip redundancy design and error correction mechanisms, unable to quickly respond and effectively repair when the chip is affected by radiation, and lacking the ability to dynamically adjust redundancy design and correction strategies. Summary of the Invention

[0003] Based on this, it is necessary for the present invention to provide a test method and system for a chip simulation model to solve at least one of the above technical problems.

[0004] To achieve the above object, a test method for a chip simulation model includes the following steps:

[0005] Step S1: Obtain chip data, perform chip circuit logic analysis to obtain circuit logic data; perform signal transmission simulation based on the circuit logic data to obtain signal transmission data; construct a chip simulation model according to the circuit logic data and the signal transmission data;

[0006] Step S2: Bombard the chip simulation model with particles to obtain particle data; perform energy spectrum classification based on the particle data to obtain proton data and heavy ion data;

[0007] Step S3: Perform single event upset fault analysis on the chip simulation model according to the proton data to obtain single event upset data; perform multi-particle upset fault analysis on the chip simulation model according to the heavy ion data to obtain multi-particle upset fault data;

[0008] Step S4: Evaluate the chip radiation reliability according to the single event upset data and the multi-particle upset fault data to obtain the chip radiation reliability; upload the chip radiation reliability to the chip simulation model and perform radiation hardening testing to generate radiation hardening test data.

[0009] By acquiring chip data and performing circuit logic analysis, the present invention can accurately capture the circuit design characteristics of the chip, thereby laying a solid foundation for the subsequent construction of the simulation model. This process can avoid the deficiency in the understanding of circuit logic in traditional simulation methods and improve the reliability of subsequent simulation results. On this basis, the introduction of signal transmission simulation can comprehensively analyze the propagation process of signals inside the chip, making the simulation model closer to the actual operating state and helping to reveal signal transmission delay or distortion problems ignored in traditional methods. Then, the simulation model constructed based on circuit logic and signal transmission data can combine the circuit characteristics of the chip with the actual operating environment, enhancing the accuracy and comprehensiveness of the simulation model and providing a more accurate physical model for subsequent particle irradiation simulation. For particle bombardment and energy spectrum classification, particle data can be accurately obtained and classified according to their different energies and properties, which helps to conduct more detailed analysis for different radiation sources. This classification method makes up for the overly simplified irradiation model in traditional simulation methods and can take into account the different effects of different particle types (such as protons and heavy ions) on the chip, thereby providing more accurate input data for multi-particle upset fault analysis. Further, through single-particle and multi-particle upset fault analysis, the effects of different types of particles on the chip can be comprehensively evaluated. In particular, the introduction of multi-particle interaction effect (MPIU) solves the defect that traditional simulation methods ignore multi-particle effects, making the simulation results more realistic and operable. Through chip radiation reliability assessment, the overall performance of the chip in a radiation environment can be systematically evaluated, and the reliability of the chip under complex radiation conditions can be comprehensively understood. This assessment method effectively avoids the neglect of redundant design and repair mechanisms in traditional testing methods and provides a scientific basis and feedback for radiation hardening design. Finally, through the implementation of radiation hardening testing, the chip can be optimized specifically, the redundant design and repair strategy can be adjusted quickly, and real-time response can be provided when affected by radiation, thereby effectively improving the radiation resistance of the chip and enhancing its stability and reliability in practical applications.

[0010] Preferably, step S1 is specifically as follows:

[0011] Step S11: Acquire chip data and perform extraction of circuit principle features to obtain circuit principle data;

[0012] Step S12: Detect logic gate relationships based on the circuit principle data to obtain logic gate relationship data;

[0013] Step S13: Generate a truth table according to the logic gate relationship data to obtain a logic truth table;

[0014] Step S14: Verify logic units based on the logic truth table to generate logic unit verification data;

[0015] Step S15: Perform circuit logic repair on the circuit principle data according to the logic unit verification data to generate circuit logic data;

[0016] Step S16: Conduct signal transmission simulation based on the circuit logic data to obtain signal transmission data;

[0017] Step S17: Construct a chip simulation model according to the circuit logic data and the signal transmission data.

[0018] Through obtaining chip data and performing circuit principle feature extraction, the present invention can accurately capture the basic structure and working principle of the chip circuit, providing a solid foundation for subsequent simulation and testing. This step ensures that all details of the chip design are precisely understood, thus avoiding circuit characteristics overlooked in traditional methods. Then, based on the circuit principle data, detecting the logic gate relationship helps analyze the connections between various logic units in the circuit, ensuring that the behavior and input-output relationships of each logic gate are fully captured, thereby improving the accuracy and reliability of the simulation model. By generating the logic truth table, the output behavior of the circuit under different input conditions can be accurately recorded, providing an all-round prediction of the chip's performance under various working conditions. Further, through logic unit verification, it is possible to check and verify whether the circuit logic meets the predetermined design criteria, which not only improves the authenticity of the simulation model but also reduces subsequent problems caused by design defects. Combining the logic unit verification data for circuit logic repair can effectively correct potential errors in the circuit design, thereby ensuring the integrity and reliability of the circuit logic and avoiding errors overlooked in traditional methods. Next, through signal transmission simulation, the propagation process of signals in the circuit and their performance under different conditions can be deeply analyzed, ensuring that the chip's performance meets the requirements during actual use. This process can reveal problems such as signal interference, delay, or loss, which are often overlooked in traditional simulations. Finally, the chip simulation model constructed based on the circuit logic data and the signal transmission data will provide a more realistic and comprehensive circuit performance for subsequent particle irradiation simulation, thereby improving the prediction accuracy of multi-particle effects (MPIU) and better evaluating the reliability of the chip in a complex radiation environment.

[0019] Preferably, step S16 is specifically as follows:

[0020] Step S161: Extract the logic gate connection relationship features based on the circuit logic data to obtain the logic gate connection relationship data;

[0021] Step S162: Determine the signal propagation path according to the logic gate connection relationship data to obtain the signal propagation path data;

[0022] Step S163: Identify the longest path according to the signal propagation path data to obtain the longest path data;

[0023] Step S164: Evaluate the propagation delay of the longest path data to obtain propagation delay data;

[0024] Step S165: Adjust the wiring of the longest path data based on the propagation delay data to obtain wiring adjustment data;

[0025] Step S166: Insert registers into the longest path data based on the propagation delay data to obtain register data;

[0026] Step S167: Perform signal transmission simulation according to the wiring adjustment data and the register data to obtain signal transmission data.

[0027] Through the extraction of the logical gate connection relationship features based on the circuit logic data, the present invention can accurately capture the relationship between the logical gates in the circuit, thereby providing a clear basis for the subsequent identification of the signal propagation path and ensuring that the signal flow path is fully understood. This step helps to identify the key links in the circuit structure and avoid missing important signal transmission paths. Then, through the determination of the signal propagation path, it is helpful to comprehensively analyze the flow direction and influence of the signal in the circuit, identify potential bottlenecks or interference sources, and optimize the subsequent chip design and simulation process. Further, through the identification of the longest path, the most critical path in the signal propagation can be found, which helps to understand the most vulnerable part of the entire circuit and provide a direction for the optimized design. Based on the longest path data, the propagation delay evaluation can effectively measure the delay situation of the signal transmission in the circuit, reveal potential signal delays or performance bottlenecks, which is crucial for ensuring the stability of the chip under high load conditions. At this time, based on the propagation delay data, the wiring adjustment can optimize the signal transmission path and reduce unnecessary delays, thereby improving the overall performance and response speed of the chip. Through register insertion, the performance stability of the circuit can be further enhanced, ensuring that the signal propagation is not affected by time limitations and preventing data loss or errors caused by excessive delays. Finally, through signal transmission simulation, it can be comprehensively verified whether all optimized designs can work properly under actual conditions, ensuring the stability of signal transmission in a radiation or complex environment and achieving higher simulation accuracy.

[0028] Preferably, the particle bombardment in step S2 includes:

[0029] Set the particle type and particle energy level of the chip simulation model;

[0030] Analyze the particle flow according to the particle energy level to obtain particle flow data;

[0031] Calculate the impact frequency according to the particle flow data to obtain the particle impact frequency;

[0032] Upload the particle impact frequency to the chip simulation model and run the particle bombardment module to obtain particle data.

[0033] In the present invention, by reasonably setting the particle energy level, it is possible to ensure that the simulation results are consistent with the actual application environment. Based on the set energy level, particle flux analysis can be carried out to simulate the particle distribution of different types of radiation sources, thereby obtaining accurate particle flux data. These data can be used to calculate the number of particles hitting the chip per unit time, and then the impact frequency can be obtained. The impact frequency is one of the key parameters for evaluating the reliability of the chip. It can characterize the cumulative damage that may occur to the chip under long-term radiation exposure. Especially in a high-energy radiation environment, the cumulative effect of particle bombardment may lead to a decline in circuit performance or even failure. After uploading the calculated impact frequency to the simulation model, running the particle bombardment module can further obtain detailed particle interaction data, including particle penetration depth, charge deposition distribution, etc. These data are crucial for evaluating the radiation resistance of the internal circuits of the chip and can also be used to optimize the circuit layout and improve the anti-interference ability.

[0034] Preferably, the energy spectrum classification in step S2 includes:

[0035] Extract the energy spectrum distribution data of the particle data;

[0036] Based on the energy spectrum distribution data, screen the particle data for high-energy particles to determine the high-energy particle data;

[0037] Identify the positively charged particles in the high-energy particle data to obtain the positively charged particle data;

[0038] Simulate the application of a magnetic field to the positively charged particle data and analyze the movement trajectory to obtain the positively charged particle trajectory data;

[0039] Based on the positively charged particle trajectory data, identify the spiral trajectory to obtain the spiral trajectory data;

[0040] Determine the protons in the particle data according to the spiral trajectory data to generate proton data;

[0041] Based on the positively charged particle trajectory data, analyze the scattering effect to obtain the scattering effect data;

[0042] Determine the heavy ions in the particle data according to the scattering effect data to generate heavy ion data.

[0043] The present invention helps to obtain the comprehensive distribution characteristics of particle energy by extracting the energy spectrum distribution data of particle data, providing a necessary basis for subsequent particle screening and simulation. Based on the energy spectrum distribution data, high-energy particle screening can accurately distinguish particles with higher energy, which have a greater impact on the chip, so they need special attention in the simulation. Further identification of positively charged particles among high-energy particles can ensure that only those particles with strong interaction forces are selected for subsequent simulation, improving the accuracy of analysis. By simulating the application of a magnetic field to the positively charged particle data and analyzing its motion trajectory, the actual motion path of the particle can be obtained, thus more realistically restoring its behavior in the actual environment. This process helps to accurately predict the motion of particles in a complex magnetic field environment, providing a more accurate reference for the anti-radiation design of the chip. Further identification of the helical trajectory can reveal the complex trajectory behavior of particles in the magnetic field, providing more powerful data support for the analysis of multi-particle effects. Determining protons based on the helical trajectory data can classify particles more precisely, ensuring that proton-like particles can be accurately identified and affect the construction of the chip model. Finally, the analysis of the scattering effect based on positively charged particles can further reveal the interaction between particles and the internal structure of the chip, obtaining heavy ion data, thus providing an in-depth understanding of the multi-particle interaction effect. Through the combined effect of these steps, the chip simulation model can more comprehensively and accurately simulate the complex effects in the radiation environment, thus improving the radiation reliability assessment and fault prediction capabilities of the chip.

[0044] Preferably, the single-event upset fault analysis in step S3 includes:

[0045] Input proton data into the chip simulation model and perform chip-proton interaction simulation to obtain chip-proton interaction data;

[0046] Identify the impact point from the chip-proton interaction data to obtain the impact point;

[0047] Based on the impact point, perform chip memory bit flip analysis to obtain memory bit flip data;

[0048] Based on the impact point, perform chip flip-flop timing error analysis to obtain flip-flop timing error data;

[0049] According to the memory bit flip data and the flip-flop timing error data, identify the hot spot area from the chip-proton interaction data to obtain the hot spot area;

[0050] Perform single-event upset fault identification on the hot spot area to obtain single-event upset data.

[0051] The present invention provides specific data support for the reaction of a chip in a radiation environment by inputting proton data into a chip simulation model and performing chip-proton interaction simulation. Through this process, the actual impact of protons on the internal structure of the chip can be effectively simulated, and then chip-proton interaction data can be generated. By identifying the impact points of these data, the key positions of particle-chip interaction can be accurately found, providing important clues for subsequent fault analysis. Based on the impact points, chip memory bit flip analysis can be carried out to timely detect the anomalies of memory cells caused by particle impacts, thereby identifying potential chip fault sources. At the same time, based on the impact points, chip flip-flop timing error analysis can help reveal the timing errors caused by radiation and predict the timing problems of the chip in a harsh environment. By combining the memory bit flip data with the flip-flop timing error data, hot spot regions of the chip-proton interaction data can be identified, thereby revealing the regions of the chip that are most vulnerable to radiation. By identifying single-event upset faults in these hot spot regions, the parts that are most vulnerable to radiation can be accurately found, providing a basis for chip redundancy design and optimization of the fault tolerance mechanism, and ultimately improving the stability and reliability of the chip in a complex radiation environment. Through this comprehensive analysis and simulation, the radiation resistance of the chip in a radiation environment can be more comprehensively and accurately evaluated, and an effective optimization scheme for chip design can be provided.

[0052] Preferably, the multi-particle upset fault analysis in step S3 includes:

[0053] Inputting heavy ion data into the chip simulation model and performing Monte Carlo multi-particle interaction simulation to obtain multi-particle interaction data;

[0054] Performing electromagnetic interaction analysis on the multi-particle interaction data to obtain multi-particle electromagnetic interaction data;

[0055] Performing multi-particle electromagnetic trajectory identification based on the electromagnetic interaction data to obtain multi-particle electromagnetic trajectory data;

[0056] Recording the incident positions on the chip simulation model based on the multi-particle electromagnetic trajectory data to generate particle incident position data;

[0057] Performing collective flip analysis on the chip simulation model based on the particle incident position data to obtain multi-particle upset fault data.

[0058] After inputting heavy ion data into the chip simulation model and performing Monte Carlo multi-particle interaction simulations, the present invention can obtain multi-particle interaction data, which provides more comprehensive simulation results for the behavior of the chip in a complex radiation environment. Conducting electromagnetic interaction analysis on these multi-particle interaction data helps to reveal the electromagnetic interactions between particles, accurately simulate the interaction effects of multi-particles inside the chip, thereby improving the accuracy and credibility of the simulation model. Through electromagnetic interaction data for multi-particle electromagnetic trajectory recognition, the movement trajectories of particles inside the chip can be further extracted, providing accurate particle path information for subsequent analysis. Based on these trajectory data, recording the incident positions of the chip simulation model can detail the incident positions of each particle, and then analyze the influence of radiation effects on different regions of the chip. Finally, collective upset analysis based on the particle incident position data can identify upset faults caused by multi-particle interactions, further revealing the potential threats of multi-particle interaction effects to the reliability of the chip. This process enables a more comprehensive evaluation of the radiation resistance of the chip and provides a scientific basis for optimizing the chip redundancy design and error repair mechanism, thereby enhancing the anti-interference ability and stability of the chip in a radiation environment.

[0059] Preferably, step S4 is specifically as follows:

[0060] Step S41: Evaluate the radiation reliability of the chip based on the single-event upset data to obtain the radiation reliability of the single-event upset chip;

[0061] Step S42: Evaluate the radiation reliability of the chip based on the multi-particle upset fault data to obtain the radiation reliability of the multi-particle upset chip;

[0062] Step S43: Integrate the radiation reliability of the single-event upset chip and the radiation reliability of the particle upset chip to obtain the radiation reliability of the chip;

[0063] Step S44: Upload the radiation reliability of the chip to the chip simulation model and perform radiation hardening tests to generate radiation hardening test data.

[0064] By evaluating the radiation reliability of the chip based on single-event upset data, the present invention can accurately quantify the impact of single-event upsets on chip performance, providing basic reliability data for the chip's performance in a radiation environment. Subsequently, by evaluating the radiation reliability of the chip based on multi-event upset fault data, the deficiencies of single-event effects can be supplemented, taking into account the potential impact of multi-particle interaction effects on the chip, ensuring a more comprehensive stability analysis of the chip in a complex radiation environment. This process further helps to reveal the vulnerability of the chip under actual conditions of multi-particle interaction. By integrating the radiation reliability of the single-event upset chip and the multi-event upset chip, a comprehensive chip radiation reliability evaluation result can be obtained, providing a scientific basis for the long-term stable operation of the chip in a high-radiation environment. Finally, uploading the comprehensively obtained chip radiation reliability to the chip simulation model and performing radiation hardening tests can verify whether the chip can effectively cope with various radiation effects in an actual radiation environment, thereby providing feedback on the chip hardening strategy. This process not only enhances the reliability evaluation of the chip in a complex radiation environment but also provides guidance for further optimizing the redundancy design and error repair mechanism in chip design.

[0065] Preferably, step S44 is specifically as follows:

[0066] Step S441: Upload the chip radiation reliability to the chip simulation model and perform chip redundancy design to obtain chip redundancy data;

[0067] Step S442: Perform integrated error detection on the chip redundancy data to obtain integrated error data;

[0068] Step S443: Make corrections based on the integrated error data to obtain corrected data;

[0069] Step S444: Set the irradiation dose for the chip simulation model to obtain irradiation dose data;

[0070] Step S445: Upload the irradiation dose data and the corrected data to the chip simulation model and perform radiation hardening tests to generate radiation hardening test data.

[0071] By uploading the chip radiation reliability to the chip simulation model and performing redundant design, the present invention helps to provide higher fault tolerance for chip design, ensuring that the chip can maintain normal functions even in a high-radiation environment. Then, by performing integrated error detection on the redundant data of the chip, errors existing in the redundant design can be detected in a timely manner, and the negative impact of radiation on the chip performance can be effectively reduced. Based on the integrated error data for correction, the chip is provided with the ability to dynamically adjust the redundant design, ensuring that the chip can adapt and respond quickly in different radiation scenarios, thereby avoiding the occurrence of major failures. By setting the irradiation dose for the chip simulation model, the performance of the chip under different radiation environments can be simulated, accurately capturing the impact of the irradiation dose on the chip functions, and providing data support for further hardening strategies. Finally, uploading the irradiation dose data and the correction data to the chip simulation model and performing radiation hardening tests can verify the radiation resistance of the chip in the actual radiation environment, optimize its design, and ultimately generate reliable radiation hardening test data, providing more scientific hardening strategies and design schemes. The implementation of this process significantly improves the survivability and long-term stability of the chip in a complex radiation environment, and can effectively avoid the limitations of ignoring the multi-particle interaction effect and error repair ability in traditional testing methods.

[0072] Preferably, this specification also provides a test system for a chip simulation model, which is used to execute the test method for the chip simulation model as described above. The test system for the chip simulation model includes:

[0073] A chip simulation model construction module, including obtaining chip data, performing chip circuit logic analysis to obtain circuit logic data; performing signal transmission simulation based on the circuit logic data to obtain signal transmission data; constructing a chip simulation model according to the circuit logic data and the signal transmission data;

[0074] A particle bombardment module, including bombarding the chip simulation model with particles to obtain particle data; performing energy spectrum classification based on the particle data to obtain proton data and heavy ion data;

[0075] A fault analysis module, including performing single-event upset fault analysis on the chip simulation model according to the proton data to obtain single-event upset data; performing multi-event upset fault analysis on the chip simulation model according to the heavy ion data to obtain multi-event upset fault data;

[0076] A radiation hardening test module, including evaluating the chip radiation reliability according to the single-event upset data and the multi-event upset fault data to obtain the chip radiation reliability; uploading the chip radiation reliability to the chip simulation model, and performing radiation hardening tests to generate radiation hardening test data. Description of the Drawings

[0077] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non - restrictive embodiments read in conjunction with the accompanying drawings:

[0078] Figure 1 It is a schematic flowchart of the steps of the test method for the chip simulation model of the present invention;

[0079] Figure 2 It is a schematic flowchart of the detailed steps of step S1 in the present invention;

[0080] Figure 3 It is a schematic flowchart of the detailed steps of step S16 in the present invention;

[0081] The realization of the object of the present invention, functional characteristics, and advantages will be further described in conjunction with the embodiments with reference to the drawings. Detailed Embodiments

[0082] The technical method of the present invention patent will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments in the present invention without creative efforts belong to the scope of protection of the present invention.

[0083] In addition, the drawings are only schematic diagrams of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor methods and / or microcontroller methods.

[0084] It should be understood that although terms such as "first", "second", etc. may be used here to describe each unit, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, the first unit can be called the second unit, and similarly the second unit can be called the first unit. The term "and / or" used here includes any and all combinations of one or more of the listed associated items.

[0085] To achieve the above object, please refer to Figures 1 to 3 , the present invention provides a test method for a chip simulation model, and the method includes the following steps:

[0086] Step S1: Obtain chip data, perform chip circuit logic analysis to obtain circuit logic data; perform signal transmission simulation based on the circuit logic data to obtain signal transmission data; construct a chip simulation model according to the circuit logic data and the signal transmission data;

[0087] In this embodiment, the original circuit data, including circuit schematic diagrams, gate circuit information, register configurations, etc., is extracted from the chip through a dedicated hardware interface tool. Use circuit design tools (such as Cadence or Altera tools) to perform circuit logic analysis on the obtained data to determine the working principle of each logic unit in the circuit and its connection relationship. During the circuit logic analysis process, the input-output signal relationship of each logic gate needs to be focused on, and the circuit behavior modeling is completed using gate-level simulation techniques (such as Verilog or VHDL simulation) to obtain circuit logic data. According to the circuit logic data, signal transmission simulation is then carried out. Use simulation tools such as Spice to simulate the propagation of signals in the circuit according to the circuit topology and the parameters of each logic unit, focusing on factors such as signal delay, impedance matching, and noise interference. The signal transmission data obtained from the simulation results mainly includes the signal transmission delay, amplitude change, and its impact on each component in the circuit. Finally, based on the circuit logic data and the signal transmission data, a complete simulation model of the chip is constructed. This step combines the results of logic analysis and transmission simulation, and generates a logical behavior model of the chip by mapping the input-output behavior of the circuit into the model.

[0088] Step S2: Bombard the chip simulation model with particles to obtain particle data; perform energy spectrum classification based on the particle data to obtain proton data and heavy ion data;

[0089] In this embodiment, to obtain data on the solar activity cycle, solar activity cycle information can be extracted from meteorological or astronomical databases (such as NOAA). Then, based on the solar activity cycle, especially the peak period of solar activity, the radiation intensity during that period is statistically analyzed, and this data can be obtained through dedicated radiation monitoring equipment (such as the Space Weather Prediction Center). On this basis, according to the radiation intensity, the types and energy levels of particles are set, and the two main particle types are set as high-energy protons and heavy ions. The setting of the particle energy level follows the relationship between the radiation intensity and the solar activity cycle, and the standard energy levels are protons of 1 - 10 MeV and heavy ions of 10 - 100 MeV respectively. Subsequently, the particle flow is analyzed through a particle flow analysis tool (such as Geant4 simulation software), and the flow direction and frequency of the particles are simulated. Based on the particle flow data, the frequency of each particle hitting the chip is calculated. This frequency is calculated according to the solar radiation intensity and the flux model, and the result is provided in the form of the hitting frequency. Finally, the calculated hitting frequency is uploaded to the chip simulation model, and the particle bombardment module is run to simulate the interaction between the particles and the chip, obtain particle data, and record the collision and interaction between the particles and the chip.

[0090] Step S3: Perform single-event upset fault analysis on the chip simulation model according to the proton data to obtain single-event upset data; perform multi-event upset fault analysis on the chip simulation model according to the heavy ion data to obtain multi-event upset fault data;

[0091] In this embodiment, the data obtained from the proton particle stream is input into the chip simulation model. Chip simulation software (such as SPICE, VHDL simulation tools) is used to perform the interaction simulation between the chip and the proton particles, and the interaction data between the proton and the chip is obtained. This process generates chip-proton interaction data according to the energy of the proton, the incident angle, and the circuit characteristics of the chip (such as storage units, trigger timing, etc.). Through this data, the storage bit flips at the proton impact point are further identified, and the resulting trigger timing errors are analyzed. Combining the incident path and velocity of the proton, the potential "hot spot" areas in the chip, that is, the positions vulnerable to protons, are identified. Finally, based on this data, the single event upset faults are identified, the positions and types of the faults are recorded, and the single event upset data is obtained. For the analysis of heavy ion data, after the heavy ion particle stream is input into the chip simulation model, the Monte Carlo multi-particle interaction simulation is performed to simulate the influence of multiple particles on the chip. In this simulation process, the electromagnetic trajectories of the heavy ions and the electromagnetic interactions between multiple particles are analyzed in detail. The multi-particle interaction data is tracked through the electromagnetic interaction model, the trajectories of different particles in the circuit are identified, and the multi-particle electromagnetic trajectory data is recorded. Subsequently, based on these trajectory data, the multi-particle collective flip analysis is further performed, and the results of the combined action of multiple particles in the chip are recorded to obtain the multi-particle flip fault data.

[0092] Step S4: Evaluate the radiation reliability of the chip according to the single event upset data and the multi-particle flip fault data to obtain the chip radiation reliability; upload the chip radiation reliability to the chip simulation model and perform the radiation hardening test to generate the radiation hardening test data.

[0093] In this embodiment, based on the data obtained from the single event upset fault analysis, the radiation reliability is evaluated. The evaluation criteria are based on the fault occurrence frequency, fault severity, and the circuit area where the faults occur. For example, for the circuit faults caused by single event upsets, the flip rate of each storage bit is calculated through the model to determine the radiation reliability of the single event upset. Then, combining the multi-particle flip fault data, the influence of the multi-particle flip faults on the circuit reliability is evaluated to obtain the radiation reliability of the chip in a multi-particle environment. After the radiation reliability evaluation is completed, the chip is hardened using radiation hardening design tools (such as hardened circuit design tools). According to the evaluation results, the radiation tolerance of the chip is improved by modifying the redundant design of the chip and increasing the fault tolerance. When performing the radiation hardening test, the chip is simulated using the set radiation dose data, and the performance of the chip in this environment is detected. Finally, the radiation hardening test data is recorded to detect whether the chip meets the expected radiation hardening standard.

[0094] Preferably, step S1 is specifically:

[0095] Step S11: Obtain chip data and perform circuit principle feature extraction to obtain circuit principle data;

[0096] In this embodiment, the original circuit data is extracted from the chip through a dedicated hardware interface, including information such as the circuit schematic diagram, parameters of each circuit component, and interconnection relationship. These data are usually stored in chip design files, such as GDSII or LEF file formats, or exported through design software such as EAGLE or Allegro. By using circuit analysis tools (such as Cadence Virtuoso or Mentor Graphics) to read and analyze the circuit design of the chip, the electrical parameters (such as resistance, capacitance, gain, etc.) of each circuit component and its connection relationship are extracted. The circuit principle feature extraction includes basic information such as the types of logic gates, the topological structure of the connections, and current and voltage. All the extracted data is organized into circuit principle data in a standard format for subsequent processing.

[0097] Step S12: Perform logic gate relationship detection based on the circuit principle data to obtain logic gate relationship data;

[0098] In this embodiment, according to the circuit principle data, a circuit logic analysis tool (such as Xilinx Vivado, the RTL compilation tool of Cadence Design Systems) is used to detect the relationships of the logic gates in the circuit. This process includes identifying each logic gate (such as AND gate, OR gate, NOT gate, XOR gate, etc.) in the circuit and its input and output signals, determining the functions of the logic gates, and identifying the signal flow between different logic gates. To this end, a standard input-output threshold needs to be set first, usually set to 0V for low level and 3.3V for high level. Through logic analysis simulation, the relationship between the output of each logic gate in the circuit and the input of other logic gates is obtained, generating connection relationship data between the logic gates, and finally forming logic gate relationship data, which includes the input and output signals of each gate, the electrical connections between the gates, and the logic states.

[0099] Step S13: Generate a truth table according to the logic gate relationship data to obtain a logic truth table;

[0100] In this embodiment, according to the logic gate relationship data obtained in step S12, a logic truth table of the chip circuit is generated by using a truth table generation tool (such as a Boolean Algebra analysis tool or a Verilog / VHDL simulator). Specifically, first, the inputs and outputs of each logic gate are analyzed, all input combinations are obtained through the combination rules of logic gates, and the output results under each combination are calculated. The generation of the truth table requires listing all permutations and combinations of the inputs. Assuming there are n input signals in a circuit, the number of rows in the truth table will be 2^n, and each row represents the output state under a certain input combination. Based on the logic gate connection relationship in the circuit principle data, the truth table is automatically generated, the output results corresponding to each group of inputs are recorded, and finally the complete logic truth table data is obtained.

[0101] Step S14: Based on the logic truth table, perform logic unit verification to generate logic unit verification data;

[0102] In this embodiment, the generated logic truth table is used to verify each logic unit in the circuit. This step can be carried out by using an automated verification tool (such as simulation tools like ModelSim, VCS, etc.). The verification process includes comparing different combinations of input signals with the truth table to detect whether the output of the logic gate is consistent with the expected result. The verification of each logic unit requires setting specific test vectors, which are input combinations extracted from the truth table, to verify whether each unit works according to the design intention. During the verification process, by comparing the simulation results with the theoretical results, it is judged whether there are logic errors or inconsistencies. The generated verification data includes the input and output results under each test vector, as well as a mark indicating whether the verification is passed, and finally the logic unit verification data is obtained.

[0103] Step S15: According to the logic unit verification data, perform circuit logic repair on the circuit principle data to generate circuit logic data;

[0104] In this embodiment, according to the errors or inconsistencies recorded in the verification data, the circuit logic is adjusted and repaired. For example, if the output of a certain logic gate does not match the expected result, then check the logic relationship of its input signals, correct the connection of this part in the circuit or change the type of its gate circuit. During the repair process, circuit design tools (such as Cadence Virtuoso, Synopsys Design Compiler, etc.) will automatically recalculate the circuit behavior according to the corrected logic gate relationship, and update the connection method and parameters of each component in the circuit. After the repair is completed, new circuit logic data is generated, including the repaired circuit logic relationship, and the entire circuit is re-verified to ensure that the repaired circuit can work properly according to the expected function.

[0105] Step S16: Perform signal transmission simulation based on the circuit logic data to obtain signal transmission data;

[0106] In this embodiment, a circuit simulation tool (such as SPICE, LTspice, Spectre, etc.) is used to perform signal transmission simulation according to the repaired circuit logic data. First, the waveform and frequency of the input signal are set to simulate the influence of different input signals on each component of the circuit. During the simulation process, the signal delay, transmission rate, signal attenuation, noise influence, etc. in the circuit are mainly analyzed. According to the connection wires and component parameters in the circuit, the simulation of signal propagation in the circuit is carried out, and the time delay, amplitude, frequency response, etc. when the signal passes through each logic gate and component are calculated. Through the signal transmission simulation, detailed data on the signal propagation in the circuit are obtained, including the voltage change and time response data of each node. These data will be used for subsequent chip performance analysis and optimization.

[0107] Step S17: Construct a chip simulation model according to the circuit logic data and the signal transmission data.

[0108] In this embodiment, first, according to the repaired circuit logic data obtained in step S15 and the signal transmission data obtained in step S16, a complete chip simulation model is constructed by using a simulation modeling tool (such as Cadence Virtuoso, Synopsys HSPICE, etc.). This simulation model will include the structure of the circuit, the electrical characteristics of the components, the connection relationship between the logic gates, and the detailed parameters of signal transmission. By combining the simulation results of circuit logic and signal transmission in the simulation environment, a complete simulation model that can reflect the actual behavior of the chip is constructed. This model can be used for subsequent performance evaluation, fault diagnosis, and optimization design.

[0109] Preferably, step S16 is specifically:

[0110] Step S161: Extract the characteristics of the connection relationship of the logic gates based on the circuit logic data to obtain the connection relationship data of the logic gates;

[0111] In this embodiment, according to the connection information of each logic gate in the circuit logic data, circuit design software (such as Cadence Virtuoso or Synopsys Design Compiler) is used to parse the logic gates in the circuit and extract the connection relationships between them. This process includes identifying the input and output signals of each logic gate, analyzing the electrical connections between different logic gates, and determining which signals are transmitted through which logic gates. By extracting all the electrical connection information in the circuit design tool, the connection relationship data of each logic gate is constructed. The connection relationship data contains detailed information such as the input and output ports of each logic gate, the ID of the logic gate it is connected to, the signal transmission direction, and the topological structure of the signal line. To ensure the accuracy of the data, it is necessary to accurately calibrate the connections of each logic gate. Usually, the input and output signal voltage standards are set, such as 0V for low level and 3.3V for high level. The finally obtained logic gate connection relationship data provides a basis for the subsequent steps.

[0112] Step S162: Determine the signal propagation path according to the logic gate connection relationship data to obtain the signal propagation path data;

[0113] In this embodiment, using the logic gate connection relationship data, the signal propagation path is determined through a signal propagation analysis algorithm. This process includes tracking each signal in the circuit and identifying the transmission path of the signal from the input end to the output end. The determination of the signal propagation path is usually carried out through path search algorithms in graph theory, such as depth-first search (DFS) or breadth-first search (BFS). First, the starting point of the signal is found in the circuit diagram according to the input port of the signal, and then the signal connection relationship is used to gradually trace to each intermediate node and terminal node. During this process, all the logic gates and their connected electrical parameters (such as propagation delay, signal attenuation, etc.) need to be recorded and used as the characteristics of the signal propagation path. Each signal path data contains information such as the logic gates passed through, the signal transmission order, and the path length. The signal propagation path data is used to describe the flow process of the signal in the circuit and provides a basis for the subsequent delay calculation and wiring adjustment steps.

[0114] Step S163: Identify the longest path according to the signal propagation path data to obtain the longest path data;

[0115] In this embodiment, according to the signal propagation path data, the longest path in the circuit is identified through a path analysis algorithm (such as Dijkstra algorithm or Bellman-Ford algorithm). The longest path refers to the path with the longest signal propagation time among the paths that the signal passes through from the input end to the output end. When calculating the longest path, the electrical parameters (such as delay, impedance, etc.) of each logic gate and connection line in the circuit need to be considered, and by comparing the transmission delays of each path one by one, the path with the longest delay is identified. During the calculation process, a threshold standard for the transmission delay needs to be set. Usually, this threshold is based on the common signal transmission delay range in the circuit (for example, between 10 ns and 50 ns). The longest path data includes information such as the starting point, ending point of signal propagation, the logic gates passed through, the delay of each gate, and its cumulative total delay. These data provide a basis for subsequent delay evaluation and wiring optimization.

[0116] Step S164: Perform propagation delay evaluation on the longest path data to obtain propagation delay data;

[0117] In this embodiment, this process obtains the propagation delay data of the entire path by calculating the propagation delay of the signal in each logic gate and its connection line in the path. Delay evaluation is usually performed using a circuit simulation tool (such as SPICE simulator or HSPICE). During the evaluation process, first, the delay parameters of each connected component (such as gate circuits, transmission lines, etc.) in the circuit are set, and these parameters can be obtained from circuit model parameters (such as capacitance, inductance, load, etc.) and process parameters (such as line width, line length, etc.). During the evaluation process, the delay of each logic gate is determined by its electrical characteristics, such as drive current, load capacitance, etc. For each signal path, the delay of each component is calculated in sequence, and finally, the total delay of the entire path is obtained. The delay data will include the start time, propagation time, total delay, etc. of each path, and further optimization is carried out based on these data.

[0118] Step S165: Perform wiring adjustment on the longest path data based on the propagation delay data to obtain wiring adjustment data;

[0119] In this embodiment, the purpose of wiring adjustment is to optimize the delay of signal transmission and ensure that the circuit can work properly within the specified clock cycle. During the adjustment process, first, the paths with larger delays are identified according to the delay data, and the delay is reduced by changing the layout of the signal lines or adding additional signal amplifiers or drivers. For example, the transmission delay can be reduced by shortening the length of long cables, adding buffer circuits, or optimizing the impedance matching of the signal channels. When performing wiring adjustment, a threshold for adjustment needs to be set according to the delay calculation results of each path. For example, paths with a delay greater than a certain specific value (such as 100 ns) need to be adjusted. The finally obtained wiring adjustment data will record the adjustment scheme for each path, including the adjusted components, the changed connection methods, and the new delay values.

[0120] Step S166: Based on the propagation delay data, perform register insertion on the longest path data to obtain register data;

[0121] In this embodiment, according to the delay data of the signal propagation path, register insertion is performed on the longest path. The purpose of register insertion is to reduce the delay and enhance the signal stability by inserting flip-flops or registers. First, according to the delay data of each path, the paths with excessive delay are identified, especially those paths whose delay exceeds the system clock cycle. Adding registers to these paths can effectively segment the signal transmission, thereby reducing the delay of each segment of the path and avoiding timing errors caused by excessive delay. The insertion position of the register is usually to select a suitable point on the path with a longer delay. After inserting the register, the path is divided into two segments, and the signal is synchronized between the two segments. The register data includes the node position of each inserted register, the type of the register, and its control signals, etc., and finally forms the complete register insertion data.

[0122] Step S167: According to the wiring adjustment data and the register data, perform signal transmission simulation to obtain signal transmission data.

[0123] In this embodiment, using the wiring adjustment data and the register data, signal transmission simulation is performed through a circuit simulation tool. First, the wiring adjustment data obtained in step S165 and the register data obtained in step S166 are input into the simulation model for a complete signal transmission simulation. During the simulation process, the input signal propagates through the adjusted wiring path and the path with inserted registers. The simulation tool (such as SPICE or Cadence simulator) calculates the voltage change of each node, the delay of the signal, the quality of the waveform, etc. The finally obtained signal transmission data includes parameters such as the transmission time, waveform, and signal quality of each signal, which are used to analyze the performance of the circuit and provide data support for subsequent optimization.

[0124] Preferably, the particle bombardment in step S2 includes:

[0125] Set the particle type and particle energy level of the chip simulation model;

[0126] In this embodiment, it is necessary to determine the particle type and particle energy level in order to accurately simulate the impact of the radiation environment on the chip. The particle types include protons, heavy ions, etc., corresponding to different radiation sources, such as particle accelerators. The setting of the particle energy level needs to be based on the experimental environment or actual application scenario. For example, the energy level of protons is usually in the range of 1 MeV to 100 MeV, while the energy of heavy ions can reach several hundred MeV to the GeV level. The acquisition of energy parameters can refer to radiation test standards, such as NASA's radiation test specifications or JEDEC's Single Event Effect (SEE) test standards. During the simulation process, the Monte Carlo method or SRIM (Stopping and Range of Ions in Matter) software is used to calculate the penetration depth and energy deposition of particles in the chip material. For different particle types, it is necessary to calculate the energy loss in the silicon-based material separately, and combine the process node of the chip (such as 28 nm, 16 nm or 7 nm) to determine the impact of the particle energy level on different circuit elements.

[0127] Perform particle flux analysis based on the particle energy level to obtain particle flux data;

[0128] In this embodiment, according to the particle type and energy level, a particle flux analysis tool (such as Geant4, SRIM, etc.) is used to perform particle flux analysis. Through the simulation model, the particle type and energy parameters are input to simulate the propagation process of particles on and inside the chip surface. The key to particle flux analysis is to calculate the penetration depth, attenuation effect and interaction with materials of particles in different materials (such as silicon, metal, etc.). During the analysis process, specific material parameters of the chip need to be set, such as the thickness of the chip, the type of surface coating, etc. Particle flux data usually includes information such as particle distribution density, flux, penetration depth, etc., and these data will provide an important basis for calculating the particle impact frequency.

[0129] Calculate the impact frequency based on the particle flux data to obtain the particle impact frequency;

[0130] In this embodiment, the particle flux data is used to calculate the particle impact frequency. The particle impact frequency refers to the number of times particles impact the chip surface and its internal electronic structure per unit time. First, through information such as particle flux and particle energy in the particle flux data, combined with the surface characteristics of the chip (such as area, material thickness, etc.), the total number of particle impacts is calculated. Specifically, the geometric relationship between the particle flux density and the chip surface contact can be used to obtain the number of impacts. For example, when the particle flux density is a certain value, according to the area of the chip, combined with the speed and energy of the particles, the impact frequency per unit time is calculated. This process involves simulating the interaction between particles and the chip surface to obtain accurate impact frequency data.

[0131] Upload the particle impact frequency to the chip simulation model and run the particle bombardment module to obtain particle data.

[0132] In this embodiment, the chip simulation model is usually created using circuit simulation tools (such as Cadence, Synopsys, etc.) and combined with a particle flow analysis module to simulate particle bombardment. When uploading the particle impact frequency, it needs to be specified as an input parameter to the physical simulation module of the chip. When running the particle bombardment module, the simulation tool will simulate the interaction between particles and the chip material, including particle scattering, damage, energy transfer, etc. According to the simulation results, the data on the impact of particles on the chip is obtained, usually with energy loss, scattering angle, damage area, etc. as the main output parameters. Finally, the obtained particle data can be used to further evaluate the radiation hardness of the chip or optimize the process.

[0133] Preferably, the energy spectrum classification in step S2 includes:

[0134] Extract the energy spectrum distribution data of the particle data;

[0135] In this embodiment, the particle flow data contains the energy information of each particle type. By statistically analyzing and classifying these data, the energy spectrum distribution is obtained. Specifically, an energy interval (such as 1 MeV to 100 MeV) is set and the number of particles in each energy interval is counted. Use data processing software (such as Matlab, NumPy library in Python) to group the data and calculate the number of particles in each energy interval, thereby obtaining the energy spectrum distribution data. The division standard of the energy interval can refer to physical literature or experimental data, and the number of particles in each interval is set as a fixed step (such as every 5 MeV as an interval). The obtained energy spectrum data can be visualized using a histogram or a curve graph for further analysis of the energy distribution of particles.

[0136] Based on the energy spectrum distribution data, high-energy particle screening is performed on the particle data to determine the high-energy particle data;

[0137] In this embodiment, when performing high-energy particle screening based on the energy spectrum distribution data, an energy screening threshold is set. For example, particles with an energy greater than 50 MeV are defined as high-energy particles. By screening the energy spectrum distribution data, the particles with an energy higher than the set threshold are selected to form the high-energy particle data. In actual operation, a programming language (such as Python, Matlab) is used to implement the screening function, traversing each particle data to determine whether its energy is greater than the set 50 MeV threshold. If so, the data of this particle is added to the high-energy particle data set. Through this process, high-energy particles can be distinguished from low-energy particles, laying a foundation for subsequent particle type analysis.

[0138] Perform positive charge particle identification on high-energy particle data to obtain positive charge particle data;

[0139] In this embodiment, when performing positive charge particle identification on high-energy particle data, screening is carried out based on the charge number of the particles. Through the physical characteristics of the particle types, identification can be performed according to their charge characteristics (such as protons, electrons, etc.). In specific implementation, first, use the particle type information (such as protons, electrons, alpha particles, etc.) in the high-energy particle data to screen out the positively charged particles. For each particle, judge whether its charge number is positive (for example, the proton charge is +1). If the particle charge is positive, classify it as a positive charge particle and store its relevant data, including particle energy, type, velocity, etc. Through this method, the obtained set of positive charge particle data can provide basic data for subsequent magnetic field simulation and trajectory analysis.

[0140] Perform magnetic field application simulation on the positive charge particle data and analyze the motion trajectory to obtain positive charge particle trajectory data;

[0141] In this embodiment, establish a magnetic field model. Usually, a uniform magnetic field or a non-uniform magnetic field model is used, and the magnetic field strength and direction are set according to actual application requirements. For example, set the magnetic field strength to 0.5T and the direction to be perpendicular to the particle motion direction. Use physical simulation software (such as Geant4, COMSOL) to perform magnetic field simulation, input the initial state (such as velocity, direction, energy, etc.) of the positive charge particle into the simulation system, and simulate the motion trajectory of the particle in the magnetic field. During the simulation process, calculate the influence of the magnetic field force on the particle motion, calculate the particle force according to the Lorentz force formula (F = q(v×B)), and then obtain the motion trajectory of the particle in the magnetic field. By analyzing the trajectory of the particle, data such as the motion path, velocity change, and trajectory curvature of each particle can be obtained, and finally, the trajectory data of the positive charge particle is generated.

[0142] Perform helical trajectory identification based on the positive charge particle trajectory data to obtain helical trajectory data;

[0143] In this embodiment, during the process of identifying the spiral trajectory based on the positive charge particle trajectory data, it is first necessary to extract the position information in the particle trajectory to obtain the three-dimensional coordinates of the particle at different time steps. By analyzing the differences between two adjacent positions, the direction of particle movement, that is, the tangent direction, can be determined. To capture the geometric characteristics of particle movement, it is also necessary to calculate the angle between adjacent tangents, and then determine whether the particle has a periodic rotation behavior. If the angle between adjacent tangents changes significantly, it can be inferred that the particle is performing a rotational motion. Next, by analyzing the angular changes of the particle trajectory in detail, it is judged whether there is continuous rotation, and it is observed whether these rotations form a spiral trajectory. Specifically, the threshold for the change in rotation angle is usually set to 15° to 25°, that is, when the angular change between adjacent positions exceeds this range, it can be determined as a spiral trajectory. If the particle trajectory shows consistent rotation characteristics in multiple periods, and these rotations present a spiral shape in the plane, it can be confirmed that the trajectory is a spiral trajectory. After confirming the spiral trajectory, it is also necessary to calculate the rotation period and the trajectory length. The rotation period can be obtained by analyzing the periodic changes in the rotational motion in the particle trajectory. The common period threshold is 50 to 200 time steps, and the specific value depends on the motion characteristics of the particle. The trajectory length is calculated by accumulating the spatial distances between each position point during the particle movement. Usually, a minimum trajectory length threshold of 10 meters to 50 meters is set to ensure that the trajectory can form a complete spiral shape. Finally, this information, including the rotation period, trajectory length, etc., will be stored and used for subsequent analysis and applications.

[0144] Determine protons from the particle data according to the spiral trajectory data to generate proton data;

[0145] In this embodiment, the mass and charge characteristics of the particles in the spiral trajectory data are checked. A proton is a particle with a positive charge and a mass of 1.67×10^-27 kg. By judging the mass and charge amount of the particle, if it conforms to the physical parameters of a proton, the particle is identified as a proton. During the implementation process, combined with the parameters of the proton model, based on the characteristics of the particle velocity, trajectory radius, rotation period, etc. in the spiral trajectory data, it is further determined whether it is a proton particle. All particle data that meet the conditions will be classified as proton data to generate a proton data set, including the velocity, position, trajectory information, etc. of each proton.

[0146] Conduct scattering effect analysis based on the positive charge particle trajectory data to obtain scattering effect data;

[0147] In this embodiment, the propagation of simulated particles in different substances is carried out, and the scattering probability of the particles and the atomic nuclei of the substances is calculated. The Monte Carlo method is used to simulate the particle trajectories multiple times, and the scattering angles and the energies of the particles after scattering are recorded each time the particles interact with the substances. During implementation, a scattering threshold is set. If the collision angle of the particle and the atomic nucleus is greater than a certain set value, it is considered that scattering has occurred. By gradually analyzing the particle trajectories, data such as the energy loss and angle change of each particle during the scattering process are obtained, and finally scattering effect data is generated, including information such as the trajectory change and energy change of the particles during the scattering process.

[0148] Based on the scattering effect data, the particle data is determined for heavy ions, and heavy ion data is generated.

[0149] In this embodiment, by analyzing the energy loss and trajectory change in the scattering effect data and combining the physical characteristics of heavy ions (such as mass, energy loss rate, etc.), particle type identification is carried out. Heavy ions have a large mass and a low speed, and generally have a greater energy loss compared with electrons and protons. During implementation, according to the energy loss rate of the particles in the scattering effect data, if the energy loss of the particles is large and the degree of trajectory bending is small, then the particle is considered to be a heavy ion. Finally, the particles that meet the conditions are classified as heavy ion data, and a corresponding heavy ion data set is generated, including information such as the mass, energy, and trajectory of the particles.

[0150] Preferably, the single-event upset fault analysis in step S3 includes:

[0151] Input the proton data into the chip simulation model, and perform chip-proton interaction simulation to obtain chip-proton interaction data;

[0152] In this embodiment, it is necessary to obtain the physical parameters of protons, such as energy, incident angle, and the particle number density of the proton beam. These parameters can be obtained through particle accelerator experiments or queried through existing databases. In the chip simulation model, the initial conditions of the protons are set, including the speed, mass, angle of the protons, and the calculation interval for each time step. The simulation model uses the Monte Carlo method to simulate the interaction between protons and the chip, and calculates the penetration path of the protons in the chip. Through numerical integration, it is simulated that the protons collide with silicon atoms in the chip, and the energy transfer and particle trajectory change after each collision are calculated. The simulation results are output as chip-proton interaction data, including the energy loss, particle trajectory, and secondary particle generation information of the protons inside the chip.

[0153] Identify the impact point from the chip-proton interaction data to obtain the impact point;

[0154] In this embodiment, the chip structure penetrated by protons is meshed. The size of each grid cell is set to 1mm×1mm, and the intersection points of protons with the chip surface or internal structure are extracted through simulation data. For each collision, the relative position relationship between the proton incident position and the chip surface or structure is calculated, and by judging whether the proton energy has decayed sufficiently at this point, it is determined whether an effective impact point is generated. The impact point is defined as the collision position where the energy is greater than a set threshold (such as 10keV), and the area meeting this condition is recorded as an impact point. If multiple proton impacts occur at one position, this position is recorded as a repeated impact point. The impact points will ultimately be saved as a data set, including the coordinates and corresponding energy values of each effective impact point.

[0155] Based on the impact points, chip storage bit flip analysis is performed to obtain storage bit flip data;

[0156] In this embodiment, according to the chip structure diagram, the physical positions of each storage unit are extracted, and these storage units are matched with the impact points. When an impact point falls on a certain storage unit, the storage bit of this storage unit is flipped, and the flipping probability is related to the size and position of the impact point energy and the sensitivity of this storage unit (such as the incident energy density with a threshold of 50keV / cm 2 . If the impact point energy is greater than the set flip threshold, it is considered that the storage bit of this storage unit has been flipped. The flip data is recorded as the state change of each storage unit (from 0 to 1 or from 1 to 0), and a timestamp and position will be marked. The storage bit flip data will be stored as a structured data set, including the state of each storage unit and the specific time when the flip occurs.

[0157] Based on the impact points, chip trigger timing error analysis is performed to obtain trigger timing error data;

[0158] In this embodiment, the chip trigger timing error analysis is implemented by identifying the spatial relationship between the impact points and the triggers. The timing error of the trigger is caused by voltage fluctuations induced by proton collisions, usually occurring near the rising edge or falling edge of the clock signal. According to the chip design, the physical positions and timing characteristics of each trigger are extracted (for example, the clock frequency is 2GHz). Then, the energy of the impact point is compared with the sensitivity of the trigger (such as the energy threshold of 10keV / cm 2 to determine whether the impact is strong enough to affect the timing of the trigger. If the energy of an impact point exceeds the timing error threshold and its position spatially coincides with the trigger, it is recorded that the trigger has a timing error. The specific data of the timing error includes the moment of the error trigger, the position of the relevant trigger, the error type (such as rising edge error or falling edge error), and the original timing data of the trigger.

[0159] Identify hotspots in the chip-proton interaction data based on stored bit flips and trigger timing error data, resulting in hotspots;

[0160] In this embodiment, map the stored bit flip data and trigger timing error data to the physical regions of the chip and calculate the occurrence frequencies of flips and errors in each region. A hotspot is a region where flips and timing errors frequently occur within the same area. These regions typically appear at specific locations on the chip (such as near the chip edge or the processing core part) because these regions are more affected by the proton flux density and energy distribution, resulting in a concentration of flip and error events. Based on a set threshold (for example, a region with more than 5 flips and more than 10 timing errors), divide the physical regions of the chip into blocks and mark the hotspots. The identification result of each hotspot includes the coordinate range of the region, the total number of flip and timing error events, and the energy distribution characteristics of the region.

[0161] Identify single-event upset (SEU) faults in the hotspots, resulting in SEU data.

[0162] In this embodiment, refine the memory cells and triggers within each hotspot according to their physical positions and compare the flip data of each region to determine whether each flip is caused by a single particle. Based on the energy, position of the proton impact point, and the characteristics of the chip, determine whether each flip meets the criteria for an SEU fault. If the flips in a hotspot are frequent and concentrated, and the occurrence times of each flip are close, it can be inferred that there is an SEU fault in this region. The SEU data record includes the occurrence location, time, fault type (such as stored bit flip or trigger timing error), and the energy characteristics of the proton incidence for each fault. The SEU fault data is finally stored in a structured data format for subsequent analysis and fault troubleshooting.

[0163] Preferably, the multi-particle flip fault analysis in step S3 includes:

[0164] Input the heavy ion data into the chip simulation model and perform Monte Carlo multi-particle interaction simulation to obtain multi-particle interaction data;

[0165] In this embodiment, the physical parameters of heavy ions are obtained, including particle energy, velocity, mass, particle density, etc. These parameters can be obtained through particle accelerator experiments or queried from existing databases. The initial incident conditions of heavy ions, such as incident angle, number of particles, etc., need to be set according to the simulation requirements. These parameters are input into the chip simulation model, and the model uses the Monte Carlo method to perform multi-particle interaction simulations. The Monte Carlo method simulates the propagation path of particles in the chip and the interaction process with material atoms through random sampling. The model calculates the events of particle collisions with silicon atoms when each heavy ion penetrates the chip, and records the energy loss and position generated by each collision. Through multiple simulations, multi-particle interaction data is generated, and the data contains the interaction details between heavy ions and the chip material, such as the energy loss, scattering angle, penetration depth, etc. generated by each particle.

[0166] Perform electromagnetic interaction analysis on the multi-particle interaction data to obtain multi-particle electromagnetic interaction data;

[0167] In this embodiment, information such as the path, energy loss, and incident angle of heavy ion particles is extracted and analyzed in combination with the electromagnetic characteristics of the chip. By using an electromagnetic field solver (such as the finite element analysis method or the boundary element method), the electromagnetic effects generated by each particle in the chip are calculated, especially the electric and magnetic fields generated during the penetration of heavy ions. In order to accurately describe the electromagnetic effects, the electrical properties of the chip (such as dielectric constant, conductivity) need to be obtained through experiments or material databases. During the electromagnetic interaction analysis process, special attention is paid to the interactions between particles and electrons in the chip, and these interactions lead to phenomena such as charge excitation and recombination. Finally, the obtained electromagnetic interaction data contains information such as the electromagnetic field strength, magnetic field direction, and field source distribution generated during the penetration of each particle, and these data provide the basis for subsequent electromagnetic interference analysis.

[0168] Perform multi-particle electromagnetic trajectory recognition based on the electromagnetic interaction data to obtain multi-particle electromagnetic trajectory data;

[0169] In this embodiment, an algorithm for electromagnetic trajectory recognition is set, and using the known electromagnetic field strength and information such as particle mass and charge, the trajectory of each particle under the action of electromagnetic force is calculated. This process uses the particle motion equation, combined with the intensity of the electromagnetic field, and uses the Euler method or the fourth-order Runge-Kutta method for numerical integration. By repeatedly calculating the trajectory of particles in the electromagnetic field, the actual movement path of each particle inside the chip is obtained, and the specific position where it penetrates the chip is determined. For each particle, the electromagnetic trajectory data records the time, position of its movement, and the process of interaction with the electric and magnetic fields, and the trajectory data includes the complete path of each particle from the incident point to the penetration point. If a certain trajectory is curved or deviates from the original path, it means that the particle has undergone a significant shift under the action of the electromagnetic field, and this information will be specially marked.

[0170] Record the incident positions for the multi-particle electromagnetic trajectory data on the chip simulation model to generate particle incident position data;

[0171] In this embodiment, the multi-particle electromagnetic trajectory data records the incident points by analyzing the initial incident positions of the particles. When each particle enters the chip from the outside, its incident position needs to be aligned with the coordinate system of the chip model to obtain the three-dimensional coordinates of the incident point. By calculating the starting positions of each particle's trajectory and storing the incident point data according to the geometric structure of the chip model. The incident position data is recorded as a set of three-dimensional coordinates, which includes the position where the particle hits the chip surface, the incident angle of the particle, and the angle with the normal of the chip surface. The calculation of the incident angle is based on the angle between the incident direction of the particle and the normal of the chip surface, and the data accuracy of the incident position needs to reach 0.1 mm. The incident position of each particle will generate corresponding records in the corresponding coordinate system of the chip model, providing a basis for subsequent flip analysis.

[0172] Perform a collective flip analysis on the chip simulation model based on the particle incident position data to obtain multi-particle flip failure data.

[0173] In this embodiment, by spatially matching the incident position of each particle with the chip storage unit, it is judged whether the particle hits the storage unit. If the incident point is located in the storage unit area, the particle will cause a storage bit flip. The flip analysis depends on the sensitivity parameters of the chip storage unit, such as the energy flip threshold of the storage unit (usually set to 50 keV / cm 2 ). If the energy density at the particle impact point exceeds this threshold, the storage bit of the storage unit flips. The collective flip analysis calculates the flip probability of each storage unit according to the incident data of multiple particles and identifies collective flip events, that is, flip failures caused by multiple particles in the same area. The collective flip data record includes the position where the flip occurs, the frequency, the type of storage unit affected, the time of the flip, etc. This data will help identify high-risk areas in the chip and provide a basis for subsequent fault troubleshooting.

[0174] Preferably, step S4 is specifically as follows:

[0175] Step S41: Evaluate the radiation reliability of the chip according to the single-particle flip data to obtain the single-particle flip chip radiation reliability;

[0176] In this embodiment, it is obtained from the chip simulation model, and this data records information such as the interaction events, incident positions, energies, etc. of each particle with the chip material. When evaluating the radiation reliability of the chip, it is necessary to calculate the impact of each single-particle flip on the chip stability. First, determine the flip threshold of the storage unit, which is determined by the electrical characteristics of the chip design and is usually set to 50 keV / cm2 Then, based on the single-event upset data, analyze the upset probability generated by each particle impact on the storage unit. Specifically, by comparing the energy density of the particle with the sensitivity parameter of the storage unit, calculate the probability of the storage bit being upset. Further, based on the upset probability of each storage unit, use the weighted average method to evaluate the radiation reliability of the overall chip, and obtain the radiation reliability of the chip under single-event upset conditions. During the calculation, the occurrence rates of all upset events are weighted according to the type, quantity, and distribution of the storage units, and finally a comprehensive radiation reliability value is obtained.

[0177] Step S42: Evaluate the radiation reliability of the chip according to the multi-event upset fault data to obtain the radiation reliability of the multi-event upset chip;

[0178] In this embodiment, the multi-event upset fault data is analyzed based on the influence of multiple particles on the storage units in the same area. When evaluating the radiation reliability of the chip due to multi-event upset, it is necessary to calculate the collective upset probability of the particle population on the storage units. First, identify the affected area of each storage unit in the multi-event upset data. For each storage unit, calculate the probability of it experiencing a multi-event upset under given conditions, and this process comprehensively considers the energy distribution, incident angle, and number of particles of the multiple particles. Calculate the upset occurrence frequency of the storage unit by using the weighted average method for the upset probabilities of different particle populations. On this basis, use the overall design rules and fault tolerance capabilities of the chip to calculate the overall radiation reliability of the chip. The influence of multi-event upset is different from that of single-event upset, and more collective effects need to be considered, so the interaction effect between particles is added during the calculation. The finally obtained radiation reliability evaluation value can reflect the vulnerability of the chip under multi-event upset conditions.

[0179] Step S43: Integrate the radiation reliability of the single-event upset chip and the radiation reliability of the multi-event upset chip to obtain the radiation reliability of the chip;

[0180] In this embodiment, the radiation reliability of single-event upset and the radiation reliability of multi-event upset are respectively set as two independent parameters. According to the working environment, radiation conditions, and external factors of the chip, determine the importance weights of these two parameters. For example, in some high-radiation environments, the influence of multi-event upset is more significant, so a higher weight is given to the radiation reliability of multi-event upset. Then, combine the two reliability values according to the weighted average method to obtain a comprehensive radiation reliability value. This value reflects the overall radiation reliability of the chip under different particle upset conditions. During the integration, considering that different types of faults have different impacts on the chip functions, different weights need to be set for different fault types. For example, single-event upset has a greater impact on low-power storage units, while multi-event upset poses a greater risk to high-frequency logic units.

[0181] Step S44: Upload the chip radiation reliability to the chip simulation model and perform radiation hardening tests to generate radiation hardening test data.

[0182] In this embodiment, the comprehensive radiation reliability value needs to be input into the chip simulation software. This data serves as the input to the model and affects the performance of the chip in the radiation environment during the simulation. When uploading, it is necessary to ensure that the simulation model is consistent with the actual hardware design, and all relevant physical parameters such as chip material characteristics, electrical parameters, and storage unit characteristics should be accurately imported. In the simulation, radiation hardening tests are performed based on the radiation reliability value. This test simulates the reaction of the chip under different radiation intensities and radiation types (such as heavy ion or neutron radiation). During the test, the chip simulation model will simulate the impact of radiation on storage units, logic circuits, and other key functional units. During the test, special attention is paid to whether the chip experiences critical failures or performance degradation in a high-radiation environment. The test results record the reliability data of the chip under different radiation conditions, such as the number of flips and the performance degradation situation. These data will serve as the basis for chip hardening design and future optimization. After the test is completed, detailed radiation hardening test data will be generated, including information such as the chip performance, fault types, and fault distributions under each radiation condition.

[0183] Preferably, step S44 is specifically as follows:

[0184] Step S441: Upload the chip radiation reliability to the chip simulation model and perform chip redundancy design to obtain chip redundancy data;

[0185] In this embodiment, the uploaded radiation reliability data includes the comprehensive evaluation value of single-event upset and multiple-event upset. Based on this data, chip redundancy design is performed. First, determine the key modules of the chip, including storage units, logic circuits, and communication interfaces. Then, according to the radiation reliability of each module, apply redundancy design to high-risk modules. For example, if the upset probability of a certain storage unit is relatively high (such as exceeding 0.5%), redundant backup units are designed near this unit. Redundancy design can be achieved by increasing the number of storage bits, replicating storage units, or through a bit error correction mechanism. The parameter settings of the redundancy design include the redundancy factor (such as 2× redundancy or 3× redundancy), and the physical location of the redundant module to ensure that it does not interact with the main module. Finally, after completing the chip redundancy design, chip redundancy data is generated, which includes the specific content and structural layout of the redundancy design for each module.

[0186] Step S442: Perform integrated error detection on the chip redundancy data to obtain integrated error data;

[0187] In this embodiment, a fault tolerance threshold is set for each redundant module. For example, the maximum number of flips that each redundant storage unit can tolerate (such as 10 flips) is set. Next, through simulation tests, the operating conditions of the redundant modules in various radiation environments are simulated to check whether the redundant modules perform backup as expected. The following aspects are mainly checked: 1) Whether the redundant module can successfully take over the task when the main module fails; 2) Whether the redundant module can effectively handle errors and avoid system crashes; 3) Whether there is mutual interference between redundant modules. By testing each function of the redundant module one by one, the types of errors that occur are detected and recorded, such as storage unit flips or logic circuit failures. Finally, integrated error data is obtained, including the error types, occurrence frequencies, and influence ranges of the redundant modules.

[0188] Step S443: Perform correction based on the integrated error data to obtain corrected data;

[0189] In this embodiment, the errors in each redundant module are classified to determine which errors are caused by design defects of the redundant module and which are caused by other factors (such as changes in the radiation environment). For design defects, such as resource conflicts or hardware failures between redundant modules, corrections are made by adjusting the structure of the redundant module. The correction methods include: 1) Adding more redundant modules; 2) Adjusting the physical layout of the redundant module to ensure that different redundant units do not interfere with each other; 3) Introducing more fault tolerance mechanisms, such as using error correction code (ECC) technology. After correction, re-simulation tests are used to verify whether the correction is effective, and the error types and occurrence frequencies of the redundant module are re-recorded. Through this process, corrected data is finally obtained, which includes all the corrected redundant module configurations, structural adjustments, and corrected performance indicators of the redundant module.

[0190] Step S444: Set the irradiation dose for the chip simulation model to obtain irradiation dose data;

[0191] In this embodiment, according to the working environment of the chip and the expected radiation level, the initial irradiation dose size is determined. For example, set 1×10 14The rad is used as the reference irradiation dose. Then, in the simulation model, adjustments are made according to different working conditions, such as factors like the chip operating temperature, the expected radiation type (such as neutrons, protons, or heavy ions). Each radiation type has a different impact on the chip. Therefore, the irradiation dose should be allocated according to the radiation type and the sensitivity of the chip material to ensure that the simulation model can truly simulate the actual radiation environment. For example, when the chip is in a space environment, due to the relatively strong space radiation, a higher irradiation dose needs to be set, usually dynamically adjusted according to time, radiation type, and environmental changes. In addition, the chip design includes radiation shielding measures, and these shielding materials will reduce the impact of radiation on the chip. Therefore, the shielding effect should be taken into account when setting the irradiation dose. The redundant system design will also affect the irradiation dose, and different modules bear different irradiation amounts. Therefore, the irradiation dose should be reasonably allocated to ensure the effectiveness of the redundant design.

[0192] Step S445: Upload the irradiation dose data and the correction data to the chip simulation model, and perform a radiation hardening test to generate radiation hardening test data.

[0193] In this embodiment, the irradiation dose data and the correction data are uploaded to the chip simulation model. After uploading, a radiation hardening test is carried out. During the test, the simulation model simulates the working state of the chip under the set irradiation dose, taking into account the effects of all redundant designs and correction measures. During the test, a specific radiation environment simulation tool is used to apply the irradiation dose to each chip module, including the storage unit, logic circuit, and interface module. The focus of the radiation hardening test is to evaluate the effectiveness of the redundant design and the correction data in a high-radiation environment, and observe whether the chip can maintain stable operation under various radiation conditions. During the simulation process, information such as the fault type, fault time point, and module performance change of each module is recorded. Finally, radiation hardening test data is generated, including the performance of the chip under different irradiation doses and different radiation types, and the test results will provide a basis for further optimization of the hardening design.

[0194] Preferably, this specification also provides a test system for a chip simulation model, which is used to execute the test method of the chip simulation model as described above. The test system for the chip simulation model includes:

[0195] A chip simulation model construction module, including obtaining chip data, performing chip circuit logic analysis to obtain circuit logic data; performing signal transmission simulation based on the circuit logic data to obtain signal transmission data; constructing a chip simulation model according to the circuit logic data and the signal transmission data;

[0196] A particle bombardment module, including bombarding the chip simulation model with particles to obtain particle data; performing energy spectrum classification based on the particle data to obtain proton data and heavy ion data;

[0197] A fault analysis module, including performing single-event upset fault analysis on a chip simulation model according to proton data to obtain single-event upset data; performing multi-event upset fault analysis on the chip simulation model according to heavy ion data to obtain multi-event upset fault data;

[0198] A radiation hardening test module, including evaluating the radiation reliability of a chip according to the single-event upset data and the multi-event upset fault data to obtain the chip radiation reliability; uploading the chip radiation reliability to the chip simulation model, and performing a radiation hardening test to generate radiation hardening test data.

[0199] Therefore, from any perspective, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the application documents are intended to be encompassed within the present invention.

[0200] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features invented herein.

Claims

1. A chip simulation model testing method, characterized in that: The following steps are involved: Step S1: Obtain chip data and perform chip circuit logic analysis to obtain circuit logic data; Perform signal transmission simulation based on circuit logic data to obtain signal transmission data; Build a chip simulation model based on circuit logic data and signal transmission data; Step S2: bombarding the chip simulation model with particles to obtain particle data; performing energy spectrum classification based on the particle data to obtain proton data and heavy ion data; Step S3: performing single-event upset fault analysis on the chip simulation model according to the proton data to obtain single-event upset data; Perform multi-particle upset fault analysis on the chip simulation model based on heavy ion data to obtain multi-particle upset fault data; Step S4: performing chip radiation reliability evaluation according to the single-particle upset data and the multiple-particle upset failure data to obtain the chip radiation reliability; Upload the chip radiation reliability to the chip simulation model, perform radiation hardening test, and generate radiation hardening test data.

2. The chip simulation model testing method according to claim 1, characterized in that: Step S1 is specifically as follows: Step S11: acquiring chip data and performing circuit principle feature extraction to obtain circuit principle data; Step S12: Perform logic gate relationship detection based on circuit principle data to obtain logic gate relationship data; Step S13: generating a truth table according to the logic gate relationship data to obtain a logic truth table; Step S14: Performing logic unit verification based on the logic truth table to generate logic unit verification data; Step S15: performing circuit logic repair on the circuit principle data according to the logic unit verification data to generate circuit logic data; Step S16: performing signal transmission simulation based on the circuit logic data to obtain signal transmission data; Step S17: constructing a chip simulation model according to the circuit logic data and the signal transmission data.

3. The chip simulation model testing method according to claim 2, characterized in that: Step S16 is specifically as follows: Step S161: extracting logic gate connection relationship features based on circuit logic data, thereby obtaining logic gate connection relationship data; Step S162: determining a signal propagation path according to the logic gate connection relationship data to obtain signal propagation path data; Step S163: identifying the longest path according to the signal propagation path data to obtain the longest path data; Step S164: Evaluate the propagation delay of the longest path data to obtain propagation delay data; Step S165: performing wiring adjustment on the longest path data based on the propagation delay data to obtain wiring adjustment data; Step S166: performing register insertion on the longest path data based on the propagation delay data to obtain register data; Step S167: Perform signal transmission simulation according to the wiring adjustment data and the register data to obtain signal transmission data.

4. The chip simulation model testing method according to claim 1, characterized in that: The particle bombardment in step S2 includes: Set the particle type and particle energy level of the chip simulation model; Perform particle flow analysis according to particle energy levels to obtain particle flow data; Calculate the impact frequency according to the particle flow data to obtain the particle impact frequency; Upload the particle impact frequency to the chip simulation model and run the particle bombardment module to obtain particle data.

5. The chip simulation model testing method according to claim 1, characterized in that: The energy spectrum classification in step S2 includes: Extract energy spectrum distribution data of particle data; Perform high-energy particle screening on particle data based on energy spectrum distribution data to determine high-energy particle data; Perform positive charge particle identification on high energy particle data to obtain positive charge particle data; Perform magnetic field simulation on the positively charged particle data and analyze the motion trajectory to obtain the positively charged particle trajectory data; Perform spiral trajectory recognition based on the positive charge particle trajectory data to obtain spiral trajectory data; Proton determination is performed on the particle data according to the spiral trajectory data to generate proton data; Perform scattering effect analysis based on positive charge particle trajectory data to obtain scattering effect data; The particle data is subjected to heavy ion determination based on the scattering effect data to generate heavy ion data.

6. The chip simulation model testing method according to claim 1, characterized in that: The single event upset fault analysis in step S3 includes: Inputting the proton data into the chip simulation model and performing chip-proton interaction simulation to obtain chip-proton interaction data; Performing impact point identification on the chip-proton interaction data to obtain the impact point; Perform chip storage bit flip analysis based on the impact point to obtain storage bit flip data; Perform chip trigger timing error analysis based on the impact point to obtain trigger timing error data; Hot spot areas are identified on chip-proton interaction data according to storage bit flip data and trigger timing error data to obtain hot spot areas; Single-event upset fault identification is performed on the hot spot area to obtain single-event upset data.

7. The chip simulation model testing method according to claim 1, characterized in that: The multi-event upset fault analysis in step S3 includes: The heavy ion data is input into the chip simulation model, and the Monte Carlo multi-particle interaction simulation is performed to obtain the multi-particle interaction data; Performing electromagnetic interaction analysis on multi-particle interaction data to obtain multi-particle electromagnetic interaction data; Perform multi-particle electromagnetic trajectory identification according to electromagnetic interaction data to obtain multi-particle electromagnetic trajectory data; Record the incident positions of the multi-particle electromagnetic trajectory data on the chip simulation model to generate particle incident position data; The chip simulation model is collectively flipped and analyzed according to the particle incident position data to obtain multi-particle flip fault data.

8. The chip simulation model testing method according to claim 1, characterized in that: Step S4 is specifically as follows: Step S41: performing chip radiation reliability evaluation according to the single event upset data to obtain the single event upset chip radiation reliability; Step S42: performing chip radiation reliability evaluation according to the multiple event upset failure data to obtain the multiple event upset chip radiation reliability; Step S43: integrating the single event upset chip radiation reliability and the particle upset chip radiation reliability to obtain the chip radiation reliability; Step S44: Upload the chip radiation reliability to the chip simulation model, and perform a radiation hardening test to generate radiation hardening test data.

9. The chip simulation model testing method according to claim 8, characterized in that: Step S44 is specifically as follows: Step S441: Upload the chip radiation reliability to the chip simulation model, and perform chip redundancy design to obtain chip redundancy data; Step S442: performing integrated error detection on the chip redundant data to obtain integrated error data; Step S443: performing correction based on the integrated error data to obtain corrected data; Step S444: setting the irradiation dose for the chip simulation model to obtain irradiation dose data; Step S445: uploading the radiation dose data and the correction data to the chip simulation model, and performing a radiation hardening test to generate radiation hardening test data.

10. A chip simulation model testing system, characterized in that: A chip simulation model testing method according to claim 1, wherein the chip simulation model testing system comprises: The chip simulation model building module includes acquiring chip data, performing chip circuit logic analysis, and obtaining circuit logic data; performing signal transmission simulation based on the circuit logic data to obtain signal transmission data; and building a chip simulation model based on the circuit logic data and the signal transmission data; The particle bombardment module includes bombarding the chip simulation model with particles to obtain particle data; performing energy spectrum classification based on the particle data to obtain proton data and heavy ion data; The fault analysis module includes performing single particle upset fault analysis on the chip simulation model according to the proton data to obtain single particle upset data; performing multi-particle upset fault analysis on the chip simulation model according to the heavy ion data to obtain multi-particle upset fault data; The radiation hardening test module includes evaluating the chip radiation reliability based on the single particle upset data and the multiple particle upset failure data to obtain the chip radiation reliability; uploading the chip radiation reliability to the chip simulation model, and performing the radiation hardening test to generate the radiation hardening test data.

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