Load transient enhancement circuit of voltage mode DCDC converter

Abstract

The embodiment of the invention discloses a load transient enhancement circuit of a voltage mode DCDC converter, which is characterized in that a traditional 3-type compensation network is improved, a zero-point adjustable compensation network is generated by a compensation transconductance amplifier to carry out loop compensation, and then zero-point adjustment is carried out by detecting output voltage. When the output voltage exceeds the threshold due to the overshoot current, the transconductance can be increased through the change of the tail current, so that the zero point moves to the low frequency, the bandwidth can be increased, and the transient response capability is improved. According to the embodiment of the invention, a zero point adjustable compensation network is generated by adding a feedback path to compensate the loop, and the adjustable zero point is adjusted by detecting the output voltage. And when the load jumps, the bandwidth is increased to low frequency through zero point shift, so that the load response capability is enhanced, and the overshoot of the output voltage is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated circuit technology, and particularly to a load transient enhancement circuit for a voltage-mode DCDC converter. Background Art

[0002] A voltage-mode DCDC converter is a device widely used in the field of power management. Common topological structures include Buck, Buck-boost, and boost structures. The output-stage LC filter of a voltage-mode DCDC converter generates double poles, and a compensation network needs to be added for stability compensation. The most typical compensation network is a type-3 compensation network. The type-3 analog compensation network generates two fixed zeros to compensate for the two poles generated by the LC. The disadvantage is that the load transient response of the voltage-mode DCDC converter is slow, resulting in a large overshoot of the output voltage. A general solution is to sample the inductor current and add a current loop to adjust the system. However, sampling the inductor current requires using a sampling resistor for sampling, which increases the system power consumption. Moreover, after adding the current loop, subharmonic oscillations will occur when the duty cycle of the PWM-mode DCDC exceeds 50%, and at this time, harmonic compensation is required, which increases the complexity and power consumption of the system. Summary of the Invention

[0003] Therefore, the embodiments of the present invention provide a load transient enhancement circuit for a voltage-mode DCDC converter to solve the technical problems that the existing method of adjusting the voltage-mode DCDC converter by adding a current loop increases the circuit power consumption and complexity and requires harmonic compensation.

[0004] To achieve the above object, the embodiments of the present invention provide the following technical solutions:

[0005] According to the first aspect of the embodiments of the present invention, a load transient enhancement circuit for a voltage-mode DCDC converter is provided. The load transient enhancement circuit is composed of a power supply, a Buck power stage, a control loop compensation circuit, a load transient enhancement circuit, and a PWM circuit;

[0006] The control loop compensation circuit is composed of a fixed zero compensation circuit and a zero adjustable compensation circuit. The fixed zero compensation circuit is a voltage-dividing network, and the zero adjustable compensation circuit consists of 2 feedback paths;

[0007] The Buck power stage is connected in parallel with the power supply. The output end of the Buck power stage is connected to the comparator and the voltage-dividing circuit of the load transient enhancement circuit. The operational transconductance amplifier of the first feedback path is connected to the variable operational transconductance amplifier of the second feedback path. The operational transconductance amplifiers of the two feedback paths generate a zero adjustable compensation network for loop compensation. The AND gate of the load transient enhancement circuit is connected to the PMOS transistor of the second feedback path;

[0008] The comparator of the load transient enhancement circuit is connected to the output end. The comparator and the AND gate together control the on / off of the PMOS transistor, thereby making the variable zero point larger and shifting it towards the low frequency, increasing the unity gain bandwidth, and enhancing the transient response ability.

[0009] The PWM circuit is connected to the PMOS transistor of the Buck power stage and also to the output end of the feedback path. The output voltage output by the two feedback paths controls the on / off of the PMOS transistor of the Buck power stage by controlling the PWM circuit.

[0010] Further, the Buck power stage is composed of a first control transistor, two resistors, an inductor, a diode, and a capacitor, and includes:

[0011] The first control transistor is connected in series with the inductor L. The first control transistor and the inductor L are also connected to the negative pole of the diode D1. The other end of the inductor L is respectively connected to the resistor R ESR and the resistor R LOAD The other end of the resistor R ESR is connected to the capacitor C0. The other end of the capacitor C0 is connected to the resistor R LOAD and is connected.

[0012] Further, the Buck power stage is composed of a first control transistor, two resistors, an inductor, a diode, and a capacitor, and includes:

[0013] The first control transistor end of the Buck power stage is respectively connected to the positive pole of the voltage source and the SR latch. The positive pole of the diode D1 and the other end of the capacitor C0 are respectively connected to the negative pole of the voltage source. At the same time, the negative pole of the voltage source is grounded.

[0014] Further, the voltage dividing network is composed of three resistors and a capacitor, and specifically includes:

[0015] The resistor R1 is connected in series with the resistor R2. The other end of the resistor R1 is grounded. The resistor R3 is connected in series with the capacitor C3, and the resistor R3 and the capacitor C3 are connected in parallel with the resistor R2. The end of the resistor R2 and the capacitor C3 far from the ground is connected to the inductor L, the resistor R ESR and the resistor R LOAD The end of the resistor R1 far from the ground is respectively connected to the VFB end of the first operational transconductance amplifier of the first feedback path and the VFB end of the variable operational transconductance amplifier of the second feedback path.

[0016] Further, the first feedback path is composed of two-stage operational transconductance amplifiers, and specifically includes:

[0017] The first operational transconductance amplifier and the second operational transconductance amplifier are connected in series. The output terminal of the second operational transconductance amplifier is connected to the output impedance resistor ro2, and the other end of the output impedance resistor ro2 is grounded. The output terminal of the first operational transconductance amplifier is respectively connected to the compensation capacitor C1 and the output impedance resistor ro1, and the other ends of the compensation capacitor C1 and the output impedance resistor ro1 are grounded.

[0018] Further, the second feedback path is composed of a variable operational transconductance amplifier, a first current mirror, a second current mirror, and a second control transistor, and specifically includes:

[0019] The output terminal of the variable operational transconductance amplifier is connected to the output terminal of the first operational transconductance amplifier. The first current mirror and the second current mirror provide the input-stage bias current for the variable operational transconductance amplifier. One end of the second current mirror is connected to the output terminal of the AND gate of the second control transistor and the load transient enhancement circuit. The VFB terminal of the variable operational transconductance amplifier is connected to the end of the resistor R1 away from the ground in the voltage division circuit; the second control transistor is connected to the second current mirror and the variable operational transconductance amplifier.

[0020] Further, the load transient enhancement circuit is composed of a 2-way multiplexer, a comparator, an AND gate, and a threshold signal, and specifically includes:

[0021] The two input terminals of the AND gate are respectively connected to the control terminal c of the 2-way multiplexer, and at the same time, the input terminals of the AND gate are also respectively connected to the output terminals of the two comparators. The positive input terminal of the first comparator is connected to the output terminal of the first multiplexer. The negative input terminal of the first comparator is respectively connected to one end of the resistor R of the Buck power stage and the positive input terminal of the second comparator. The negative input terminal of the first comparator is also connected to the resistor R2 and one end of the capacitor C3 in the voltage division circuit. The negative input terminal of the second comparator is connected to the control terminal of the second multiplexer. LOAD One end of the resistor and the positive input terminal of the second comparator. The negative input terminal of the first comparator is also connected to the resistor R2 and one end of the capacitor C3 in the voltage division circuit. The negative input terminal of the second comparator is connected to the control terminal of the second multiplexer.

[0022] Further, the output terminal of the AND gate is connected to the second controller, and the second controller is a PMOS transistor.

[0023] Further, the first input terminal of the first comparator inputs the threshold signal VOH, the second input terminal inputs the threshold signal VOHHYS, the first input terminal of the second comparator inputs the threshold signal VOL, and the second input terminal inputs the threshold signal VOLHYS.

[0024] Further, the PWM circuit is composed of an SR latch, a pulse width modulator, and an oscillator, and specifically includes:

[0025] The SR latch is connected to the first control transistor of the Buck power stage and also to the output of the pulse width modulator. The input of the pulse width modulator is connected to the output of the tunable operational transconductance amplifier and the oscillator respectively, and the oscillator is also connected to the SR latch.

[0026] The embodiments of the present invention have the following advantages:

[0027] The load transient enhancement circuit of the embodiments of the present invention consists of a power supply, a Buck power stage, a control loop compensation circuit, a load transient enhancement circuit and a PWM circuit; the control loop compensation circuit consists of a fixed zero compensation circuit and a zero adjustable compensation circuit. The fixed zero compensation circuit is a voltage division network, and the zero adjustable compensation circuit consists of 2 feedback paths; the Buck power stage is connected in parallel with the power supply, and the output of the Buck power stage is connected to the comparator and the voltage division circuit of the load transient enhancement circuit. The operational transconductance amplifier of the first feedback path is connected to the variable operational transconductance amplifier of the second feedback path. The operational transconductance amplifiers of the two feedback paths generate a zero adjustable compensation network for loop compensation. The AND gate of the load transient enhancement circuit is connected to the PMOS transistor of the second feedback path; the comparator of the load transient enhancement circuit is connected to the output. The comparator and the AND gate together control the on and off of the PMOS transistor, thereby making the variable zero larger and moving towards the low frequency, increasing the unity gain bandwidth and enhancing the transient response ability; the PWM circuit is connected to the PMOS transistor of the Buck power stage and also to the output of the feedback path. The output voltages output by the two feedback paths control the on and off of the PMOS transistor of the Buck power stage by controlling the PWM circuit. The embodiments of the present invention generate a zero adjustable compensation network by adding a feedback path to compensate the loop, and adjust the adjustable zero by detecting the output voltage. When the load jumps, the bandwidth is increased by moving the zero to the low frequency, thereby enhancing the load response ability of the system and reducing the output voltage overshoot. Description of the Drawings

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only exemplary. For those of ordinary skill in the art, other implementation drawings can be obtained based on the provided drawings without creative efforts.

[0029] The structures, ratios, sizes, etc. shown in this specification are only used to cooperate with the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the conditions for the implementation of the present invention. Therefore, they do not have substantial technical significance. Any modification of the structure, change in the ratio relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention.

[0030] Figure 1 It is a schematic diagram of the structure of an existing voltage-mode DCDC converter;

[0031] Figure 2 It is a schematic diagram of the structure of a load transient enhancement circuit of a voltage-mode DCDC converter provided by an embodiment of the present invention. Specific embodiments

[0032] The following specific embodiments illustrate the implementation manners of the present invention. Those familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0033] The voltage-mode DCDC converter is a device widely used in the field of power management. Common topological structures include Buck, Buck-boost, and boost structures. The output-stage LC filter of the voltage-mode DCDC converter will generate double poles, and a compensation network needs to be added for stability compensation. The most typical compensation network is the type-3 compensation network. Please refer to Figure 1 , the type-3 analog compensation network generates two fixed zeros to compensate for the two poles generated by LC. The disadvantage is that the load transient response of the voltage-mode DCDC converter is slow, resulting in a large overshoot of the output voltage.

[0034] The existing method is to sample the inductor current and then add a current loop to adjust the system. The disadvantages of adding a current loop are: 1) Sampling the inductor current requires using a sampling resistor for sampling, which increases the power consumption of the system; 2) After adding a current loop, subharmonic oscillations will occur when the duty cycle of the PWM-mode DCDC exceeds 50%, and harmonic compensation is required, which increases the complexity and power consumption of the system.

[0035] In order to solve the technical problems of increasing circuit power consumption and complexity and requiring harmonic compensation in the above method of adjusting the voltage-mode DCDC converter by adding a current loop.

[0036] Refer to Figure 2, an embodiment of the present invention discloses a load transient enhancement circuit for a voltage-mode DCDC converter, which improves the traditional type-3 compensation network. A compensation transconductance amplifier is used to generate a zero-point adjustable compensation network for loop compensation, and then the zero point is adjusted by detecting the output voltage. When an overshoot current causes the output voltage to exceed the threshold, the transconductance can be increased by changing the tail current, so that the zero point moves to a lower frequency, which can increase the bandwidth and thus improve the transient response ability.

[0037] The load transient enhancement circuit consists of a power supply, a Buck power stage, a control loop compensation circuit, a load transient enhancement circuit, and a PWM circuit;

[0038] The control loop compensation circuit consists of a fixed zero-point compensation circuit and a zero-point adjustable compensation circuit. The fixed zero-point compensation circuit is a voltage-dividing network, and the zero-point adjustable compensation circuit consists of two feedback paths;

[0039] The Buck power stage is connected in parallel with the power supply. The output end of the Buck power stage is connected to the comparator and the voltage-dividing circuit of the load transient enhancement circuit. The operational transconductance amplifier of the first feedback path is connected to the variable operational transconductance amplifier of the second feedback path. The operational transconductance amplifiers of the two feedback paths generate a zero-point adjustable compensation network for loop compensation. The AND gate of the load transient enhancement circuit is connected to the PMOS transistor of the second feedback path;

[0040] The comparator of the load transient enhancement circuit is connected to the output end. The comparator and the AND gate jointly control the on-off of the PMOS transistor, thereby making the variable zero point larger and moving to a lower frequency, increasing the unity-gain bandwidth, and enhancing the transient response ability;

[0041] The PWM circuit is connected to the PMOS transistor of the Buck power stage and also to the output end of the feedback path. The output voltages output by the two feedback paths control the on-off of the PMOS transistor of the Buck power stage by controlling the PWM circuit.

[0042] When the load transient enhancement circuit proposed in the embodiment of the present invention switches between light and heavy loads at the output, when the output voltage exceeds the preset threshold voltage, the loop bandwidth is adjusted through the zero-point adjustable compensation network.

[0043] Further, the Buck power stage consists of a first control transistor, two resistors, an inductor, a diode, and a capacitor, including: the first control transistor is connected in series with the inductor L, the first control transistor and the inductor L are also connected to the negative pole of the diode D1, and the other end of the inductor L is respectively connected to the resistor R ESR and the resistor R LOAD is connected, the other end of the resistor R ESR is connected to the capacitor C0, and the other end of the capacitor C0 is connected to the resistor R LOADare connected.

[0044] Further, the Buck power stage is composed of a first control transistor, two resistors, an inductor, a diode, and a capacitor, and includes: the first control transistor terminal of the Buck power stage is respectively connected to the positive pole of the voltage source and the SR latch, the positive pole of diode D1 and the other end of capacitor C0 are respectively connected to the negative pole of the voltage source, and at the same time, the negative pole of the voltage source is grounded.

[0045] Further, the voltage dividing network is composed of three resistors and a capacitor, and specifically includes: resistor R1 is in series with resistor R2, the other end of resistor R1 is grounded, resistor R3 is in series with capacitor C3 and resistor R3 and capacitor C3 are in parallel with resistor R2, and the end of resistor R2 and capacitor C3 far from the ground is connected to the inductor L of the Buck power stage, resistor R ESR and resistor R LOAD and one end of resistor R. The end of resistor R1 far from the ground is respectively connected to the VFB terminal of the first operational transconductance amplifier of the first feedback path and the VFB terminal of the variable operational transconductance amplifier of the second feedback path.

[0046] The transfer function of the fixed zero compensation network is as follows:

[0047]

[0048] From the above formula, it can be obtained that:

[0049]

[0050] where z1 represents the fixed zero.

[0051] Further, the first feedback path is composed of two - stage operational transconductance amplifiers, and specifically includes: the first operational transconductance amplifier and the second operational transconductance amplifier are in series, the output terminal of the second operational transconductance amplifier is connected to the output impedance resistor ro2, the other end of the output impedance resistor ro2 is grounded, the output terminal of the first operational transconductance amplifier is respectively connected to the compensation capacitor C1 and the output impedance resistor ro1, and the other ends of the compensation capacitor C1 and the output impedance resistor ro1 are grounded.

[0052] Feedback path 1 is composed of two - stage operational transconductance amplifiers G1 and G2. gm1 and gm2 are the transconductances of the two - stage operational transconductance amplifiers Gm1 and Gm2 respectively, r o 1 and r o 2 are the output impedances of the two - stage operational transconductance amplifiers Gm1 and Gm2 respectively, and C1 is the compensation capacitor of the first - stage operational transconductance amplifier.

[0053] Further, the second feedback path is composed of a variable operational transconductance amplifier, a first current mirror, a second current mirror, and a second control transistor, specifically including: the output end of the variable operational transconductance amplifier is connected to the output end of the first operational transconductance amplifier, the first current mirror and the second current mirror provide input-stage bias current for the variable operational transconductance amplifier, one end of the second current mirror is connected to the output end of the AND gate of the second control transistor and the load transient enhancement circuit, the VFB end of the variable operational transconductance amplifier is connected to the end of the resistor R1 away from the ground in the voltage division circuit; the second control transistor is connected to the second current mirror and the variable operational transconductance amplifier.

[0054] Feedback path 2 consists of a variable operational transconductance amplifier Gmx, a current mirror I1, a current mirror I2, and a control transistor PM2.

[0055] The current mirror I1 and the current mirror I2 provide input-stage bias current for the operational transconductance amplifier Gmx, and the provided currents are I C and I X .

[0056] The relationship between the transconductance g mx of the operational transconductance amplifier Gmx, the current IC, and the current IX is:

[0057]

[0058] where β is a coefficient related to the CMOS process, W / L is the aspect ratio of the input-stage device of the operational transconductance amplifier Gmx, and the value of a is controlled by the gate voltage of PM2.

[0059] When the gate voltage of PM2 is high, a = 0, and when the gate voltage of PM2 is low, a = 1.

[0060] The transfer function of the zero-adjustable compensation network is as follows:

[0061]

[0062] From the above formula, it can be obtained that:

[0063]

[0064] The absolute value of the variable zero z X becomes larger or smaller as g mx increases, that is, the variable zero z X moves towards low frequency.

[0065] The transfer function of the entire control loop is as follows:

[0066]

[0067] The two zeros z1 and z generated by the control loopX Compensate for the two poles generated by the power stage.

[0068] Further, the load transient enhancement circuit consists of a 2-way multiplexer, a comparator, an AND gate, and threshold signals, specifically including: The two input terminals of the AND gate are respectively connected to the control terminal c of the 2-way multiplexer. At the same time, the input terminals of the AND gate are also respectively connected to the output terminals of two comparators. The positive input terminal of the first comparator is connected to the output terminal of the first multiplexer. The negative input terminal of the first comparator is respectively connected to the R of the Buck power stage LOAD One end of the resistor and the positive input terminal of the second comparator are connected. The negative input terminal of the first comparator is also connected to one end of the resistor R2 and the capacitor C3 of the voltage dividing circuit. The negative input terminal of the second comparator is connected to the control terminal of the second multiplexer.

[0069] Further, the output terminal of the AND gate is connected to the second controller, and the second controller is a PMOS transistor.

[0070] Further, the first input terminal of the first comparator inputs the threshold signal VOH, the second input terminal inputs the threshold signal VOHHYS, the first input terminal of the second comparator inputs the threshold signal VOL, and the second input terminal inputs the threshold signal VOLHYS.

[0071] The load transient enhancement circuit consists of 2-way multiplexers MUX1 and MUX2, comparators COMP1 and COMP2, an AND gate AND2, and a PMOS transistor PM2, and threshold signals VOH, VOHHYS, VOL, and VOLHYS. The threshold signals VOH and VOHHYS are the overvoltage threshold and the overvoltage threshold hysteresis respectively, and the threshold signals VOL and VOLHYS are the undervoltage threshold and the undervoltage threshold hysteresis respectively.

[0072] The 2-way multiplexer MUX1 or MUX2 includes input terminals 1 and 2, output terminal 3, and control terminal c. When a high level is input to the control terminal c, the output terminal 3 is connected to the input terminal 1; when a low level is input to the control terminal c, the output terminal 3 is connected to the input terminal 2.

[0073] When the output voltage is lower than VOH and higher than VOL, COMP1 and COMP2 both output a high level, the AND gate AND2 outputs a high level, and PM2 is turned off. At this time, the transconductance g mx :

[0074]

[0075] At this time, the variable zero point z X Is at the set frequency, and the system operates normally.

[0076] When the output voltage is higher than VOH, COMP1 outputs a low level, the AND gate AND2 outputs a low level, and PM2 is turned on. At this time, the transconductance gmx :

[0077]

[0078] Variable zero point z X With g mx As g increases, it moves towards lower frequencies, the loop bandwidth increases, and the transient response is enhanced. The overvoltage threshold hysteresis VOHHYS is lower than VOH. When VOUT is less than VOHHYS and then increases from small to large, VOUT is compared with VOH. When VOUT is greater than VOH and then decreases from large to small, VOUT is compared with VOHHYS. This can prevent the repeated switching of COMP1 due to the change of VOUT near VOH;

[0079] When the output voltage is lower than VOL, the output of COMP1 is at 0 level, the output of AND gate AND2 is at 0 level, and PM2 is turned on. At this time, the transconductance g mx :

[0080]

[0081] Variable zero point z X With g mx As g increases, it moves towards lower frequencies, the loop bandwidth increases, and the transient response is enhanced. The undervoltage threshold hysteresis VOLHYS is higher than VOL.

[0082] When VOUT is greater than VOLHYS and then decreases from large to small, VOUT is compared with VOL. When VOUT is less than VOL and then increases from small to large, VOUT is compared with VOLHYS. This can prevent the repeated switching of COMP2 due to the change of VOUT near VOL.

[0083] Therefore, during load transient jumps, when the output voltage exceeds the overvoltage or is lower than the undervoltage threshold, the variable zero point z X With g mx As g increases, it moves towards lower frequencies, the unity gain bandwidth increases, and the transient response ability is enhanced.

[0084] Furthermore, the PWM circuit is composed of an SR latch, a pulse width modulator, and an oscillator, and specifically includes: the SR latch is connected to the first control transistor of the Buck power stage, and is also connected to the output end of the pulse width modulator. The input end of the pulse width modulator is respectively connected to the output end of the adjustable operational transconductance amplifier and the oscillator, and the oscillator is also connected to the SR latch.

[0085] In the embodiments of the present invention, by improving the traditional type-3 compensation network, a zero-point adjustable compensation network is generated by a compensation transconductance amplifier for loop compensation, and then the zero point is adjusted by detecting the output voltage. When an overshoot current causes the output voltage to exceed the threshold, the transconductance can be increased by changing the tail current, so that the zero point moves towards the low frequency, which can increase the bandwidth and thus improve the transient response ability. In the embodiments of the present invention, a zero-point adjustable compensation network is generated by adding a feedback path to compensate the loop, and the adjustable zero point is adjusted by detecting the output voltage. When the load jumps, the zero point moves towards the low frequency to increase the bandwidth, thereby enhancing the load response ability and reducing the output voltage overshoot.

[0086] Although the present invention has been described in detail above with general descriptions and specific embodiments, based on the present invention, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of protection required by the present invention.

Claims

1. A load transient enhancement circuit for a voltage-mode DCDC converter, characterized in that: The load transient enhancement circuit is composed of a power supply, a Buck power stage, a control loop compensation circuit, a load transient enhancement circuit and a PWM circuit; The control loop compensation circuit is composed of a fixed zero point compensation circuit and a zero point adjustable compensation circuit, the fixed zero point compensation circuit is a voltage divider network, and the zero point adjustable compensation circuit is composed of two feedback paths; The Buck power stage is connected in parallel with the power supply, the output end of the Buck power stage is connected to the comparator and the voltage divider circuit of the load transient enhancement circuit, the operational transconductance amplifier of the first feedback path is connected to the variable operational transconductance amplifier of the second feedback path, the operational transconductance amplifiers of the two feedback paths generate a zero-point adjustable compensation network for loop compensation, and the AND gate of the load transient enhancement circuit is connected to the PMOS tube of the second feedback path; The comparator of the load transient enhancement circuit is connected to the output end, and the comparator and the AND gate together control the on and off of the PMOS tube, thereby making the variable zero point larger and moving toward the low frequency, increasing the unit gain bandwidth, and enhancing the transient response capability; The PWM circuit is connected to the PMOS tube of the Buck power stage and is also connected to the output end of the feedback path. The output voltages output by the two feedback paths control the on and off of the PMOS tube of the Buck power stage by controlling the PWM circuit.

2. The load transient enhancement circuit of a voltage-mode DCDC converter according to claim 1, characterized in that: The Buck power stage is composed of a first control tube and two resistors, an inductor, a diode and a capacitor, and specifically includes: The first control tube is connected in series with the inductor L. The first control tube and the inductor L are also connected to the cathode of the diode D1. The other end of the inductor L is connected to the resistor R ESR and resistor R LOAD connected, the resistor R ESR The other end of the capacitor C0 is connected to the resistor R LOAD are connected.

3. The load transient enhancement circuit of a voltage-mode DCDC converter as claimed in claim 2, characterized in that: The Buck power stage is composed of a first control tube and two resistors, an inductor, a diode and a capacitor, including: The first control tube end of the Buck power stage is connected to the positive electrode of the voltage source and the SR latch respectively, the positive electrode of the diode D1 and the other end of the capacitor C0 are connected to the negative electrode of the voltage source respectively, and the negative electrode of the voltage source is grounded.

4. The load transient enhancement circuit of a voltage-mode DCDC converter as claimed in claim 3, characterized in that: The voltage divider network is composed of three resistors and one capacitor, specifically including: Resistor R1 is connected in series with resistor R2, the other end of resistor R1 is grounded, resistor R3 is connected in series with capacitor C3, and resistor R3, capacitor C3 and resistor R2 are connected in parallel, and the end of resistor R2 and capacitor C3 away from ground is connected to the inductor L of the Buck power stage, resistor R ESR and resistor R LOAD One end of the resistor R1 is connected to the VFB end of the first operational transconductance amplifier of the first feedback path and the VFB end of the variable operational transconductance amplifier of the second feedback path respectively.

5. A load transient enhancement circuit for a voltage-mode DCDC converter as claimed in claim 4, characterized in that: The first feedback path is composed of a two-stage operational transconductance amplifier, specifically comprising: The first operational transconductance amplifier and the second operational transconductance amplifier are connected in series, the output end of the second operational transconductance amplifier is connected to the output impedance resistor ro2, the other end of the output impedance resistor ro2 is grounded, and the output end of the first operational transconductance amplifier is respectively connected to the compensation capacitor C1 and the output impedance resistor ro1, and the other ends of the compensation capacitor C1 and the output impedance resistor ro1 are grounded.

6. A load transient enhancement circuit for a voltage-mode DCDC converter as claimed in claim 5, characterized in that: The second feedback path is composed of a variable operational transconductance amplifier, a first current mirror, a second current mirror and a second control tube, and specifically includes: The output end of the variable operational transconductance amplifier is connected to the output end of the first operational transconductance amplifier, the first current mirror and the second current mirror provide input stage bias current for the variable operational transconductance amplifier, one end of the second current mirror is connected to the second control tube and the AND gate output end of the load transient enhancement circuit, the VFB end of the variable operational transconductance amplifier is connected to the end of the resistor R1 in the voltage divider circuit away from the ground; the second control tube is connected to the second current mirror and the variable operational transconductance amplifier.

7. A load transient enhancement circuit for a voltage-mode DCDC converter as claimed in claim 6, characterized in that: The load transient enhancement circuit is composed of a 2-way multiplexer, a comparator, an AND gate and a threshold signal, and specifically includes: The two input ends of the AND gate are connected to the control end c of the 2-way multiplexer respectively, and the input ends of the AND gate are also connected to the output ends of the two comparators respectively, the positive input end of the first comparator is connected to the output end of the first multiplexer, and the negative input end of the first comparator is connected to the R of the Buck power stage respectively. LOAD One end of the resistor is connected to the positive input end of the second comparator, the negative input end of the first comparator is also connected to the resistor R2 and one end of the capacitor C3 of the voltage divider circuit, and the negative input end of the second comparator is connected to the control end of the second multiplexer.

8. A load transient enhancement circuit for a voltage-mode DCDC converter as claimed in claim 7, characterized in that: The output end of the AND gate is connected to the second controller, and the second controller is a PMOS tube.

9. A load transient enhancement circuit for a voltage-mode DCDC converter as claimed in claim 8, characterized in that: The first comparator receives a threshold signal VOH at its first input terminal and a threshold signal VOHHYS at its second input terminal. The second comparator receives a threshold signal VOL at its first input terminal and a threshold signal VOLHYS at its second input terminal.

10. A load transient enhancement circuit for a voltage-mode DCDC converter as claimed in claim 9, characterized in that: The PWM circuit is composed of an SR latch, a pulse width modulator and an oscillator, and specifically includes: The SR latch is connected to the first control tube of the Buck power stage and is also connected to the output end of the pulse width modulator. The input end of the pulse width modulator is respectively connected to the output end of the adjustable operational transconductance amplifier and the oscillator. The oscillator is also connected to the SR latch.

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