Control method of power switch module and related circuit

Abstract

The invention discloses a circuit which comprises a logic circuit and a power switch module, and the power switch module comprises a plurality of switches, a voltage detection circuit and a control circuit. Each switch of the plurality of switches comprises a control end, a first end and a second end, the first end is coupled to a supply voltage, and the second end is coupled to the logic circuit; and the plurality of switches comprise a first switch and a plurality of second switches, and the control end of the first switch receives a power supply enabling signal. The voltage detection circuit is used for detecting whether a voltage of the second end of the first switch is higher than a reference voltage so as to generate a detection result. The control circuit is used for generating an output power enable signal to the plurality of second switches according to the detection result.

Description

Technical Field

[0001] The present invention relates to a control method for a power switch module in a chip. Background Art

[0002] In a general chip, a power switch module is usually provided to connect a supply voltage to a logic circuit when the logic circuit of the chip needs to be powered on. And in order to provide sufficient current to the logic circuit, the power switch module includes multiple switches. However, when the power switch module receives a power enable signal and turns on to connect the supply voltage to the logic circuit, a large amount of rush current may flow through the power switch module from the supply voltage into the logic circuit in a short time, resulting in a large voltage drop of the supply voltage instantaneously. Since the supply voltage may be supplied to other chips or circuits simultaneously, the instantaneous voltage drop of the supply voltage will affect the operation of other chips or circuits.

[0003] To solve the above problem of the instantaneous voltage drop of the supply voltage, prior art would set delay circuits between multiple switches in the power switch module. However, setting these delay circuits not only increases the chip area, but also greatly increases the design cost for the determination and calibration operations of the delay amount of each delay circuit. Summary of the Invention

[0004] Therefore, one of the objectives of the present invention is to propose a control method for a power switch module, which can control the turn-on time of multiple switches included in the power switch module to effectively reduce the rush current and avoid a large instantaneous voltage drop of the supply voltage, so as to solve the problems described in the prior art.

[0005] In an embodiment of the present invention, a circuit is disclosed, which includes a logic circuit and a power switch module. The power switch module includes multiple switches, a voltage detection circuit and a control circuit. Each of the multiple switches includes a control terminal, a first terminal and a second terminal. The first terminal is coupled to a supply voltage, and the second terminal is coupled to the logic circuit. And the multiple switches include a first switch and multiple second switches, and the control terminal of the first switch receives a power enable signal. The voltage detection circuit is coupled to a first switch among the multiple switches and is used to detect whether a voltage at the second terminal of the first switch is higher than a reference voltage to generate a detection result. The control circuit is coupled to the voltage detection circuit and is used to generate an output power enable signal to the multiple second switches according to the detection result.

[0006] In one embodiment of the present invention, a control method for a power switch module is disclosed. The power switch module includes a plurality of switches, each switch including a control terminal, a first terminal, and a second terminal. The first terminal is coupled to a supply voltage, and the second terminal is coupled to a logic circuit. The plurality of switches includes a first switch and a plurality of second switches, and the control method includes: inputting a power enable signal to the control terminal of the first switch; detecting whether a voltage at the second terminal of the first switch is higher than a reference voltage to generate a detection result; and generating an output power enable signal to the plurality of second switches according to the detection result. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 6 is a schematic diagram of a circuit in a chip according to a first embodiment of the present invention.

[0008] Figure 2 FIG. 10 is a schematic diagram of a switch according to an embodiment of the present invention.

[0009] Figure 3 FIG. 14 is a timing diagram of a plurality of signals and inrush current according to an embodiment of the present invention.

[0010] Figure 4 FIG. 18 is a schematic diagram of a circuit in a chip according to a second embodiment of the present invention.

[0011] Figure 5 FIG. 22 is a schematic diagram of a switch according to an embodiment of the present invention.

[0012] Figure 6 FIG. 26 is a flowchart of a control method for a power switch module according to an embodiment of the present invention.

[0013]

REFERENCE SIGNS

[0014] 100: Circuit

[0015] 102: Buffer

[0016] 110: Power switch module

[0017] 112: Voltage detection circuit

[0018] 114: Control circuit

[0019] 120: Logic circuit

[0020] 200: Switch

[0021] 210, 220: Inverters 400: Circuit

[0022] 402: Buffer

[0023] 410: Power switch module

[0024] 412: Voltage detection circuit

[0025] 414: Control circuit

[0026] 420: Logic circuit

[0027] DS: Detection result

[0028] MN1: N-type transistor

[0029] MP1: P-type transistor

[0030] N1~N4: Terminals

[0031] P_en: Power enable signal

[0032] P_en’: Output power enable signal

[0033] SW1~SWN: Switches

[0034] Vcc: Supply voltage

[0035] Vin: Voltage

[0036] Vref: Reference voltage Detailed implementation manners

[0037] Figure 1 It is a schematic diagram of a circuit 100 in a chip according to a first embodiment of the present invention. As Figure 1 shown, the circuit 100 includes a buffer 102, a power switch module 110, and a logic circuit 120. The power switch module 110 includes a plurality of switches SW1~SWN, a voltage detection circuit 112, and a control circuit 114. In this embodiment, the logic circuit 120 is a core circuit of the chip or a circuit module with a specific function, and the power switch module 110 is used to selectively connect a supply voltage Vcc to a logic circuit 120, where the logic circuit 120 can be regarded as an equivalent capacitor from the perspective of power supply.

[0038] In the operation of the power switch module 110, assuming that the logic circuit 120 is not operating at the beginning, for example, in a sleep mode, a power enable signal P_en received by the power switch module 110 will have a first voltage level, for example, a low voltage level corresponding to the logical value "0", so that the plurality of switches SW1~SWN are in an unenabled state. At this time, the logic circuit 120 is not connected to the supply voltage Vcc through the power switch module 110.

[0039] Next, when the logic circuit 120 needs to be powered on for operation, for example, when it needs to enter the normal mode from the sleep mode, the power enable signal P_en will switch from the first voltage level to a second voltage level, for example, a high voltage level corresponding to the logical value "1". At this time, the switch SW1 will conduct to connect the supply voltage Vcc to the logic circuit 120.

[0040] Figure 2 FIG. 4 is a schematic diagram of a switch 200 according to an embodiment of the present invention, where the switch 200 can be used to implement Figure 1 at least a part of the switches SW1 to SWN shown. As Figure 2 shown, the switch 200 includes two inverters 210, 220, a P-type transistor MP1, and four terminals N1 to N4. The terminal N1 is used as an input terminal, the terminal N3 is coupled to the supply voltage Vcc, the terminal N4 is coupled to the logic circuit 120, and the terminal N2 can be designed as an output terminal or a floating terminal according to the design. The signal from the terminal N1 is processed by the inverters 210, 220 to generate an output signal to the terminal N2. The P-type transistor MP1 includes a control terminal, a first terminal, and a second terminal, where the control terminal is connected to the output terminal of the inverter 210, the first terminal is connected to the terminal N3, and the second terminal is connected to the terminal N4. Taking the switch SW1 as an example, the inverter 210 receives the power enable signal P_en through the buffer 102 to generate an inverted power enable signal, and the control terminal of the P-type transistor MP1 receives the inverted power enable signal to determine whether to conduct. Referring to Figure 3 , since the power enable signal P_en starts to enable the switch SW1, the voltage level of the voltage Vin of the second terminal of the P-type transistor MP1 will gradually increase due to the current from the supply voltage Vcc. The voltage Vin can also be regarded as the voltage value of the upper plate of the equivalent capacitor of the logic circuit 120. It should be noted that at this time, the remaining switches SW2 to SWN are all in the disabled state, and since only the switch SW1 is conducting at this time, the inrush current is not high, and the rising speed of the voltage Vin will be relatively gentle.

[0041] It should be noted that Figure 2 the use of two inverters 210, 220 and P-type transistors to implement the switches SW1 to SWN shown is only for illustrative purposes and is not a limitation of the present invention. In other embodiments, the switches SW1 to SWN can be implemented using any other suitable switches.

[0042] The voltage detection circuit 112 detects the level of the voltage Vin to determine whether the voltage Vin is higher than a reference voltage Vref to generate a detection result DS. In one embodiment, the reference voltage Vref can be obtained by dividing the supply voltage Vcc through a voltage dividing circuit, and the reference voltage Vref can be any suitable value lower than the supply voltage Vcc, such as 0.75*Vcc, 0.8*Vcc, 0.85*Vcc, and so on. In another embodiment, the reference voltage Vref is lower than the supply voltage Vcc, and when the voltage Vin is equal to or greater than the reference voltage Vref, the P-type transistors in the switches SW1 to SWN operate in the resistive region rather than the saturation region.

[0043] In one embodiment, the voltage detection circuit 112 can be a comparator, and the voltage detection circuit 112 compares the voltage Vin with the reference voltage Vref to generate the detection result DS. In this embodiment, if the voltage Vin is lower than the reference voltage Vref, the detection result DS is a low voltage level corresponding to the logical value "0"; and if the voltage Vin is higher than the reference voltage Vref, the detection result DS is a high voltage level corresponding to the logical value "1", but the present invention is not limited thereto.

[0044] Next, the control circuit 114 receives at least the detection result DS to generate an output power enable signal P_en' to the switches SW2 to SWN. In one embodiment, if the detection result DS indicates that the voltage Vin is lower than the reference voltage Vref, the output power enable signal P_en' causes the switches SW2 to SWN to be in an unenabled state; and if the detection result DS indicates that the voltage Vin is higher than the reference voltage Vref, the output power enable signal P_en' is enabled to turn on the switches SW2 to SWN. In another embodiment, in order to prevent the power switch module 110 from malfunctioning due to unstable voltage during operation, the control circuit 114 generates the output power enable signal P_en' to the switches SW2 to SWN according to the power enable signal P_en and the detection result DS. For example, only when the detection result DS indicates that the voltage Vin is higher than the reference voltage Vref, and the power enable signal P_en has a voltage level (e.g., a high voltage level corresponding to the logical value "1") for enabling the power switch module 110, the output power enable signal P_en' will enable the switches SW2 to SWN. It should be noted that the power enable signal P_en received by the control circuit 114 can be from Figure 2 the terminal N1 or the terminal N4 of the switch 200 shown.

[0045] In Figure 1In an embodiment, the control circuit 114 is implemented by an AND gate, but this feature is not a limitation of the present invention. Specifically, as long as the detection result DS indicates that the voltage Vin is higher than the reference voltage Vref and the power enable signal P_en has a voltage level for enabling the power switch module 110, the control circuit 114 can output the power enable signal P_en' to turn on the switches SW2 to SWN, and the control circuit 114 can be implemented using other different logic circuits.

[0046] In addition, when the switches SW2 to SWN are turned on, the voltage Vin already has a relatively high voltage level (i.e., the voltage Vin is higher than the reference voltage Vref). Therefore, since there is a small voltage difference between the first end and the second end of each of the switches SW2 to SWN, the switches SW2 to SWN will operate in the resistive region because the drain-to-source voltage (Vds) is less than the critical value and have a small current amount.

[0047] As described in the above embodiment, also referring to Figure 3 , when the power enable signal P_en starts to enable the power switch module 110, at the beginning, only the switch SW1 will be turned on to charge the equivalent capacitance of the logic circuit 120, so there will be a low inrush current amount, and the rising speed of the voltage Vin will be relatively gentle. In addition, when the level of the voltage Vin is higher than the reference voltage Vref, the control circuit 114 will enable the remaining switches SW2 to SWN to charge the equivalent capacitance of the logic circuit 120, and since the switches SW2 to SWN will have a small current amount because they operate in the resistive region, it is possible to further avoid the situation where the supply voltage Vcc has a large instantaneous voltage drop caused by a large inrush current.

[0048] Figure 4 FIG. is a schematic diagram of a circuit 400 in a chip according to a second embodiment of the present invention. As Figure 4 shown, the circuit 400 includes a buffer 402, a power switch module 410, and a logic circuit 420. The power switch module 410 includes a plurality of switches SW1 to SWN, a voltage detection circuit 412, and a control circuit 414. In this embodiment, from the perspective of power, the logic circuit 420 can be regarded as an equivalent capacitance.

[0049] Figure 5 FIG. is a schematic diagram of a switch 500 according to an embodiment of the present invention, where the switch 500 can be used to implement Figure 4 shown, at least a part of the switches SW1 to SWN. As Figure 5As shown, the switch 500 includes two buffers 510, 520, an N-type transistor MN1, and four terminals N1 to N4. Among them, terminal N1 serves as an input terminal, terminal N3 is coupled to the logic circuit 120, terminal N4 is coupled to a reference terminal, and terminal N2 can be used as an output terminal or a floating contact according to the design. The signal from terminal N1 is processed by buffers 510 and 520 to generate an output signal to terminal N2. The N-type transistor MN1 includes a control terminal, a first terminal, and a second terminal, where the control terminal is connected to the output terminal of buffer 510, the first terminal is connected to terminal N3, and the second terminal is connected to terminal N4. Taking switch SW1 as an example, buffer 510 receives the power enable signal P_en to control the control terminal of N-type transistor MN1 to determine whether to turn on N-type transistor MN1.

[0050] Figure 4 、 Figure 5 The operation of the embodiment of Figure 1 、 Figure 2 For the embodiment of, those of ordinary skill in the art should be able to understand its operation after reading the above embodiments, so the details are not described here.

[0051] Figure 6 FIG. is a flowchart of a control method for the power switch modules 110 and 410 according to an embodiment of the present invention. Referring to the content described in the above embodiments, the flow of the control method is as follows.

[0052] Step 600: Provide a power switch module, where the power switch module includes a plurality of switches, each switch includes a control terminal, a first terminal, and a second terminal, the first terminal is coupled to a supply voltage, and the second terminal is coupled to a logic circuit; and the plurality of switches includes a first switch and a plurality of second switches.

[0053] Step 602: Input a power enable signal to the control terminal of the first switch.

[0054] Step 604: Detect whether a voltage at the second terminal of the first switch is higher than a reference voltage to generate a detection result.

[0055] Step 606: Generate an output power enable signal to the plurality of second switches according to the detection result.

[0056] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A circuit comprising: a logic circuit; and A power switch module is coupled to the logic circuit, wherein the power switch module includes: A plurality of switches, each of which comprises a control terminal, a first terminal and a second terminal, the first terminal is coupled to a supply voltage, and the second terminal is coupled to the logic circuit; and the plurality of switches comprises a first switch and a plurality of second switches, the control terminal of the first switch receives a power enable signal; a voltage detection circuit coupled to the first switch among the plurality of switches, for detecting whether a voltage at the second end of the first switch is higher than a reference voltage to generate a detection result; and A control circuit is coupled to the voltage detection circuit and is used to generate an output power enabling signal to the plurality of second switches according to the detection result.

2. The circuit as described in claim 1, wherein when the detection result indicates that the voltage at the second end of the first switch is lower than the reference voltage, the multiple second switches are in an unenabled state; and when the detection result indicates that the voltage at the second end of the first switch is higher than the reference voltage, the control circuit generates the output power enable signal to enable the multiple second switches. 3 . The circuit of claim 1 , wherein the control circuit generates the output power enable signal to the plurality of second switches according to the detection result and the power enable signal.

4. The circuit as described in claim 3, wherein the control circuit will generate the output power enable signal to enable the plurality of second switches only when the detection result indicates that the voltage at the second end of the first switch is higher than the reference voltage and the power enable signal has a voltage level for enabling the first switch.

5. The circuit as claimed in claim 3, wherein the control circuit is an AND gate.

6. The circuit of claim 1, wherein each of the plurality of switches comprises a transistor; and the reference voltage is lower than the supply voltage, and when the voltage is equal to or greater than the reference voltage, the transistors in the plurality of second switches operate in a resistance region.

7. A control method of a power switch module, wherein the power switch module comprises a plurality of switches, each switch comprises a control terminal, a first terminal and a second terminal, the first terminal is coupled to a supply voltage, and the second terminal is coupled to a logic circuit; and the plurality of switches comprises a first switch and a plurality of second switches, and the control method comprises: Inputting a power enable signal to the control end of the first switch; detecting whether a voltage at the second end of the first switch is higher than a reference voltage to generate a detection result; and An output power enabling signal is generated to the plurality of second switches according to the detection result.

8. The control method as claimed in claim 7, wherein the step of generating the output power enable signal to the plurality of second switches according to the detection result comprises: When the detection result indicates that the voltage at the second end of the first switch is lower than the reference voltage, the plurality of second switches are in a disabled state; and When the detection result indicates that the voltage at the second end of the first switch is higher than the reference voltage, the output power enable signal is generated to enable the plurality of second switches.

9. The control method as claimed in claim 7, wherein the step of generating the output power enable signal to the plurality of second switches according to the detection result comprises: The output power enable signal is generated to the plurality of second switches according to the detection result and the power enable signal.

10. The control method as claimed in claim 9, wherein the step of generating the output power enable signal to the plurality of second switches according to the detection result and the power enable signal comprises: The output power enable signal is generated to enable the plurality of second switches only when the detection result indicates that the voltage at the second end of the first switch is higher than the reference voltage and the power enable signal has a voltage level for enabling the first switch.

11. The control method as claimed in claim 7, wherein each of the plurality of switches comprises a transistor; and the reference voltage is lower than the supply voltage, and when the voltage is equal to or greater than the reference voltage, the transistors of the plurality of second switches all operate in a resistance region.

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