Hashing method, hash calculation system, electronic equipment and storage medium

Abstract

The invention provides a hash method, a hash calculation system, electronic equipment and a storage medium, and the method comprises the steps: filling data, and obtaining a to-be-compressed message; inputting the to-be-compressed message and the first group of message words into a first pipeline structure for compression to obtain a first compressed message; inputting the first compressed message into a second pipeline structure; and compressing the second compressed message output by the nth parallel computing unit based on the (n + 1) th message word output by the nth parallel computing unit, and generating an (n + 2) th message word based on the (n + 1) th message word for the (n + 2) th parallel computing unit to compress. Thus, when the compression function module carries out compression, the message word extension module carries out extension calculation of a next message word at the same time to form parallel calculation of the compression function and message word extension, the compression function module and / or the parallel calculation unit are / is connected through the register to form pipeline calculation, and the compression efficiency and the throughput rate of the compression process are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of compression technology, and in particular, to a hashing method, a hashing calculation system, an electronic device, and a storage medium. Background Art

[0002] As the cornerstone of the information age, servers carry a large amount of sensitive information and critical applications, and their security is crucial for the robustness of the entire information system. Cryptography is a key area of research in information security and an important solution for ensuring information security. As an important part of cryptography, the hash algorithm is widely used in scenarios such as message authentication, digital signatures, and blockchain computing. Summary of the Invention

[0003] The present disclosure provides a hashing method, a hashing calculation system, an electronic device, and a storage medium to at least solve the above technical problems existing in the prior art.

[0004] According to a first aspect of the present disclosure, a hashing method is provided, the method comprising:

[0005] Padding the data to obtain a message to be compressed;

[0006] Inputting the message to be compressed and a first set of message words into a first pipeline structure composed of at least one compression function module and at least one register for compression to obtain a first compressed message;

[0007] Inputting the first compressed message into a second pipeline structure; the second pipeline structure includes at least one parallel computing unit, at least one register bank, and a compression function module, the register bank is disposed between any two parallel computing units, and any one parallel computing unit includes a message word expansion module and a compression function module;

[0008] Compressing the second compressed message output by the nth parallel computing unit based on the (n + 1)th message word output by the nth parallel computing unit, and generating the (n + 2)th message word based on the (n + 1)th message word for use by the (n + 2)th parallel computing unit for compression.

[0009] In the above solution, the padding the data to obtain a message to be compressed includes:

[0010] Adding a first character, at least one second character, and at least one third character for representing the data length at the end of the data;

[0011] Wherein, the number of the at least one third character is a first preset value; the number of the at least one second character is determined based on a second preset value and the first preset value.

[0012] In the above solution, the first pipeline structure includes at least one compression function module, and a register is set between any two compression function modules. Compressing the message to be compressed and the first set of message words by inputting them into the first pipeline structure composed of at least one compression function module and at least one register to obtain a first compressed message, including:

[0013] Input the message to be compressed and the first set of message words into the first pipeline structure;

[0014] Each compression function module compresses based on the message to be compressed and the first set of message words, and transmits the compressed data to the next compression function module for compression based on the register, and determines that the output of the last compression function module in the first pipeline structure is the first compressed message.

[0015] In the above solution, inputting the first compressed message into the second pipeline structure includes:

[0016] Input the first compressed message into the second pipeline structure through the register between the first pipeline structure and the second pipeline structure.

[0017] In the above solution, before compressing the second compressed message output by the nth parallel computing unit based on the (n + 1)th message word output by the nth parallel computing unit, the method further includes outputting the (n + 1)th message word based on the nth parallel computing unit, specifically including:

[0018] Set a first register and a second register in the message word expansion module included in the nth parallel computing unit;

[0019] Perform message word expansion operations based on the first register and the second register respectively to obtain a first sub-message word and a second sub-message word;

[0020] Determine the (n + 1)th message word based on the first sub-message word and the second sub-message word.

[0021] In the above solution, performing message word expansion operations based on the first register and the second register respectively to obtain a first word message word and a second sub-message word includes:

[0022] The first register determines a first sub-message word based on the first message word and the second message word in the current set of message words;

[0023] The second register determines a second sub-message word based on the third message word and the fourth message word in the current set of message words;

[0024] Among them, the first message word is the first message word in the current group of message words, the second message word is the second message word in the current group of message words; the third message word is the ninth message word in the current group of message words, and the fourth message word is the 14th message word in the current group of message words.

[0025] In the above solution, determining the (n + 1)-th message word based on the first sub-message word and the second sub-message word includes:

[0026] Adding the first sub-message word and the second sub-message word to obtain the (n + 1)-th message word.

[0027] In the above solution, after obtaining the (n + 1)-th message word, the method further includes:

[0028] Replacing the last message word in the current group of message words based on the (n + 1)-th message word, shifting all the message words in the current group of message words to the left by the first number of bits, and compressing the second compressed message output by the n-th parallel computing unit based on the shifted current group of message words.

[0029] In the above solution, compressing the second compressed message output by the n-th parallel computing unit based on the (n + 1)-th message word output by the n-th parallel computing unit includes:

[0030] Determining the compression function path among the input register, the intermediate register, and the output register included in the n-th parallel computing unit;

[0031] Compressing the second compressed message based on the compression function path among the input register, the intermediate register, and the output register.

[0032] In the above solution, determining the compression function path among the input register, the intermediate register, and the output register included in the n-th parallel computing unit includes:

[0033] Determining the compression function path between the input register and the intermediate register;

[0034] Determining the compression function path between the intermediate register and the output register;

[0035] Based on the compression function path between the input register and the intermediate register, and the compression function path between the intermediate register and the output register, determining the compression function path among the input register, the intermediate register, and the output register.

[0036] In the above solution, determining the compression function path between the input register and the intermediate register includes:

[0037] Determine the input of the sixth sub-register in the intermediate register based on the outputs of the third, fourth, and fifth sub-registers in the input register;

[0038] Determine the input of the tenth sub-register in the intermediate register based on the outputs of the seventh, eighth, and ninth sub-registers in the input register;

[0039] Determine the input of the twelfth sub-register in the intermediate register based on the output of the eleventh sub-register in the input register.

[0040] In the above solution, the method for determining the compression function path between the intermediate register and the output register includes:

[0041] Determine the input of the thirteenth sub-register in the output register based on the inputs of the sixth, tenth, and twelfth sub-registers in the intermediate register;

[0042] Determine the input of the fifteenth sub-register in the output register based on the inputs of the fourteenth, tenth, and twelfth sub-registers in the intermediate register.

[0043] According to a second aspect of the present disclosure, there is provided a hashing calculation system, the system including a first pipeline structure and a second pipeline structure;

[0044] The first pipeline structure includes at least one compression function module and at least one register, and one register is provided between any two compression function modules;

[0045] The second pipeline structure includes at least one parallel computing unit and at least one register, and one register is provided between any two parallel computing units;

[0046] Each parallel computing unit includes a message word expansion module and a compression function module;

[0047] The first pipeline structure is used to compress the message to be compressed to obtain a first compressed message;

[0048] The second pipeline structure is used to compress the first compressed message to obtain a third compressed message, specifically including compressing the second compressed message output by the nth parallel computing unit based on the (n + 1)th message word output by the nth parallel computing unit, and generating the (n + 2)th message word based on the (n + 1)th message word for use by the (n + 2)th parallel computing unit for compression.

[0049] In the above solution, the message word expansion module in the nth parallel computing unit is used for:

[0050] Perform message word expansion operations based on the first register and the second register respectively to obtain a first sub-message word and a second sub-message word;

[0051] Determine the (n + 1)-th message word based on the first sub-message word and the second sub-message word.

[0052] In the above solution, the message word expansion module includes a first register and a second register;

[0053] The first register is used to determine a first sub-message word based on a first message word and a second message word in the current group of message words;

[0054] The second register is used to determine a second sub-message word based on a third message word and a fourth message word in the current group of message words;

[0055] Wherein, the first message word is the first message word in the current group of message words, the second message word is the second message word in the current group of message words; the third message word is the ninth message word in the current group of message words, and the fourth message word is the 14th message word in the current group of message words.

[0056] In the above solution, the compression function module in the n-th parallel computing unit is used to:

[0057] Determine the compression function path among the input register, the intermediate register and the output register included in the n-th parallel computing unit;

[0058] Compress the second compressed message based on the compression function path among the input register, the intermediate register and the output register.

[0059] In the above solution, the compression function module in the n-th parallel computing unit is used to:

[0060] Determine the compression function path between the input register and the intermediate register;

[0061] Determine the compression function path between the intermediate register and the output register;

[0062] Based on the compression function path between the input register and the intermediate register and the compression function path between the intermediate register and the output register, determine the compression function path among the input register, the intermediate register and the output register.

[0063] According to the third aspect of the present disclosure, there is provided an electronic device, including:

[0064] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method described in the present disclosure.

[0065] According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the method described in the present disclosure.

[0066] According to a fifth aspect of the present disclosure, there is provided a computer program product including a computer program which, when executed by a processor, implements the method described in the present disclosure.

[0067] The hashing method of the present disclosure obtains a message to be compressed by padding data; inputs the message to be compressed and a first set of message words into a first pipeline structure composed of at least one compression function module and at least one register for compression to obtain a first compressed message; inputs the first compressed message into a second pipeline structure; the second pipeline structure includes at least one parallel computing unit and at least one register bank, the register bank is disposed between any two parallel computing units, and any parallel computing unit includes a message word expansion module and a compression function module; based on the (n + 1)-th message word output by the n-th parallel computing unit, compresses the second compressed message output by the n-th parallel computing unit, and generates the (n + 2)-th message word based on the (n + 1)-th message word for use by the (n + 2)-th parallel computing unit for compression. In this way, through the parallel computing unit, while the compression function module performs compression, the message word expansion module simultaneously performs the expansion calculation of the next message word, constituting the parallel calculation of the compression function and the message word expansion, and connecting the compression function module and / or the parallel computing unit through registers to constitute a pipeline calculation, thereby improving the compression efficiency and the throughput rate of the compression process.

[0068] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary but non-limiting manner, wherein:

[0070] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0071] Figure 1Shows a first alternative flowchart of the hashing method provided by an embodiment of the present disclosure;

[0072] Figure 2 Shows a second alternative flowchart of the hashing method provided by an embodiment of the present disclosure;

[0073] Figure 3 Shows a third alternative flowchart of the hashing method provided by an embodiment of the present disclosure;

[0074] Figure 4 Shows a data filling schematic diagram provided by an embodiment of the present disclosure;

[0075] Figure 5 Shows a schematic structural diagram of a message expansion module provided by an embodiment of the present disclosure;

[0076] Figure 6 Shows a schematic structural diagram of a compression function module provided by an embodiment of the present disclosure;

[0077] Figure 7 Shows an alternative schematic structural diagram of a hashing calculation system provided by an embodiment of the present disclosure;

[0078] Figure 8 Shows an alternative schematic structural diagram of a high-speed pipeline calculation module provided by an embodiment of the present disclosure;

[0079] Figure 9 Shows a schematic composition structure diagram of an electronic device according to an embodiment of the present disclosure. Detailed implementation manners

[0080] To make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present disclosure.

[0081] In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0082] In the following description, the terms "first / second" involved are only used to distinguish similar objects, and do not represent a specific order for the objects. It can be understood that "first / second" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0083] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used in this disclosure are for the purpose of describing embodiments of this disclosure only and are not intended to limit this disclosure.

[0084] It should be understood that in various embodiments of this disclosure, the magnitude of the sequence numbers of each implementation process does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this disclosure.

[0085] In the current hash algorithm solutions for ensuring information security, most of the hash algorithms are implemented by software. This algorithm is mainly applied to aspects such as file integrity verification and digital signature verification to prevent data tampering and identity forgery.

[0086] However, the hash algorithm implemented by software has limitations in its processing ability, which makes the encryption and decryption speed relatively slow. Especially when facing a large amount of data processing tasks or high-frequency encryption and decryption operations, the performance bottleneck will be extremely prominent. In addition, the software implementation method is more vulnerable to software vulnerabilities and attacks, and situations such as cache side-channel attacks and memory overflow attacks may occur.

[0087] In view of the defects in the related art, the embodiments of this disclosure provide a compression algorithm and a compression computing system based on hardware (hash hardware accelerator), adopting a pipeline architecture, which can solve the speed bottleneck of the hash module for large-scale data streams in the prior art. In addition, the embodiments of this disclosure also optimize the paths of the compression function module and the message word expansion module in the hash hardware accelerator to solve the problem of limited operating frequency. Combining the above technologies, the compression algorithm and the compression computing system provided by the embodiments of this disclosure greatly improve the performance of hash hardware compression.

[0088] Figure 1 The first optional flowchart of the hashing method provided by the embodiments of this disclosure is shown, and will be described according to each step.

[0089] Step S101, fill the data to obtain the message to be compressed.

[0090] In some embodiments, the carrier (hereinafter referred to as the carrier) for implementing the hashing method fills the data, adds at least one third character representing the data length after the data, and pads the data so that the length of the message to be compressed after padding meets the requirements of the hash operation.

[0091] In some embodiments, the carrier may be a computer program, an electronic circuit, a database, a mobile application, an electronic device, a cloud computing platform, a distributed system, an artificial intelligence framework, a mathematical model, an automation tool, a microcontroller, etc., which are software or hardware capable of implementing algorithms and method flows.

[0092] Step S102: Input the message to be compressed and the first set of message words into a first pipeline structure composed of at least one compression function module and at least one register for compression to obtain a first compressed message.

[0093] In some embodiments, the first pipeline structure includes at least one compression function module and at least one register; a register is arranged between any two compression function modules to form a pipeline structure.

[0094] In some embodiments, the at least one compression function module compresses the message to be compressed based on the first set of message words and transmits it to the next compression function module through a register. The number of compression function modules is the same as the number of message words in the first set of message words. The compression function modules sequentially use the message words in the order of the first set of message words to compress the message transmitted by the previous compression function module through a register; the output of the last compression function module in the first pipeline structure is the first compressed message.

[0095] Among them, the first set of message groups (16 32-bit) is the message to be compressed (512-bit).

[0096] Step S103: Input the first compressed message into a second pipeline structure.

[0097] In some embodiments, a register is arranged between the first pipeline structure and the second pipeline structure, and the first compressed message is input into the second pipeline structure based on the register.

[0098] In some embodiments, the second pipeline structure includes at least one parallel computing unit, at least one register, and a compression function module. Each parallel computing unit includes a message word expansion module and a compression function module; a register is arranged between the compression function modules included in any two parallel computing units to form a pipeline structure by multiple parallel computing units; a compression function module is arranged after the last parallel computing unit, and the last parallel computing unit is connected to the compression function module through a register.

[0099] Step S104: Compress the second compressed message output by the nth parallel computing unit based on the (n + 1)th message word output by the nth parallel computing unit, and generate the (n + 2)th message word based on the (n + 1)th message word for use by the (n + 2)th parallel computing unit for compression.

[0100] In some embodiments, the compression function module and the message word expansion module in the parallel computing unit run in parallel. The compression function module compresses the compressed message output by the compression function module in the previous parallel computing unit based on the message word output by the message word expansion module in the previous parallel computing unit, and transmits the compressed compressed message to the compression function module in the next parallel computing unit through a register; the message word expansion module expands the message word and transmits the message word to the compression function module in the next parallel computing unit for use by the compression function module for compression.

[0101] In this way, through the hashing method provided by the embodiments of the present disclosure, between parallel computing units or through parallel computing units by the compression function module, while the compression function module performs compression, the message word expansion module simultaneously performs the expansion calculation of the next message word, constituting the parallel computing of the compression function and the message word expansion. Connecting the compression function module and / or the parallel computing unit through a register constitutes a pipeline calculation, improving the compression efficiency and the throughput rate of the compression process.

[0102] Figure 2 Fig. 2 shows a second optional flowchart of the hashing method provided by the embodiments of the present disclosure, and will be described according to each step.

[0103] Step S201: Pad the data to obtain the message to be compressed.

[0104] In some embodiments, the carrier compresses the data based on a hashing algorithm. Since the message length processed by the hashing function in each round is 512 bt, the carrier first pads the data to obtain the message to be compressed, and the message length of the message to be compressed is a multiple of 512 bit.

[0105] Specifically, when implementing, the carrier adds a first character, at least one second character, and at least one third character for characterizing the data length at the end of the data. Wherein, the first character is 1, and the second character is 0; the number of the at least one third character is a first preset value, and the meaning of the at least one third character is the length of the data; the number of the second characters is determined based on a second preset value, the first preset value, and the length of the data, and the second preset value may be 512. The first preset value may be 64.

[0106] Specifically, add the number 1 and several 0s at the end of the data until the length of the data modulo 512 is 448, and add 64 bits of length at the end of the message to represent the number of bits of the data.

[0107] For example, if the data length is 512p + q, then the number of the second characters is 512 - 1 - 64 - q. p is a positive integer, and q is an integer greater than or equal to 0.

[0108] Step S202: Compress the message to be compressed based on the first set of message words and the first pipeline structure to obtain a first compressed message.

[0109] In some embodiments, there are a total of 64 message words, namely W0 to W 63 , and the first set of message words includes W0 to W 15 , which is composed of the message to be compressed (512bit). The carrier inputs the message to be compressed and the first set of message words into the first pipeline structure; each compression function module compresses based on the message to be compressed and the first set of message words, and transfers the compressed data to the next compression function module for compression based on registers. It is determined that the output of the last compression function module (R 14 ) in the first pipeline structure is the first compressed message.

[0110] Specifically, the first pipeline structure may include 15 compression function modules (R0 to R 14 ) and 14 registers. When each compression function module performs compression, it correspondingly uses the message words in the first set of message words; for example, the first compression function module uses message word W0, the second compression function module uses message word W1, and so on.

[0111] Specifically, the first compression function module R0 in the first pipeline structure compresses the first compressed message based on W0 to obtain compressed message 0, and transfers compressed message 0 to the second compression function module R1 through a register. The second compression function module compresses compressed message 0 based on W1 to obtain compressed message 1, and so on, until the fifteenth compression function module R 14 compresses compressed message 14 based on W 14 to obtain the first compressed message.

[0112] Step S203: Compress the first compressed message based on the current set of message words and the second pipeline structure to obtain a third compressed message.

[0113] In some embodiments, a register is provided between the first pipeline structure and the second pipeline structure for transmitting the first compressed message.

[0114] In some embodiments, the current set of message words may be a message word group composed of at least one message word being used for compression. Usually, each group of message words includes 16 message words; when the first message word in the group is used up, the message words are shifted left by 32 bits, that is, the first message word is deleted, and the subsequent message words are sequentially migrated to the registers of the previous message words, and a new message word is added to the last register in the group after migration; the new message word may be the message word generated by the previous parallel computing unit; it may also be the message word at the corresponding position in all the pre-stored message words.

[0115] In some embodiments, the second pipeline structure includes 48 parallel computing units, at least 48 registers, and 1 compression function module; each parallel computing unit includes 1 message word expansion module and 1 compression function module; between the compression function modules in any two parallel computing units, they are connected by registers. For example, there is a register between the compression function module of the k-th parallel computing unit and the compression function module of the k + 1-th parallel computing unit, and the compression function module of the last parallel computing unit is connected to the compression function module through a register, and the second pipeline structure is formed by at least one register.

[0116] In some embodiments, the message word expansion module and the compression function module included in each parallel computing unit operate in parallel. The message word expansion module determines the message word to be used when the next parallel computing unit performs compression; the compression function module compresses the compressed message output by the previous parallel computing unit based on the message word output by the message word expansion module of the previous parallel computing unit, and determines the output of the last compression function module in the second pipeline structure as the third compressed message.

[0117] For example, for the s-th parallel computing unit, it receives the message word W s generated by the message word expansion module in the s - 1-th parallel computing unit, and the compressed information s - 1 output by the s - 1-th parallel computing unit. Based on the message word W s , it compresses the compressed information s - 1 to obtain the compressed information s; meanwhile, the message word expansion module in the s-th parallel computing unit generates the message word W s+1 , and outputs it to the s + 1-th parallel computing unit for use by the compression function module of the s + 1-th parallel computing unit for compression.

[0118] In some alternative embodiments, the carrier may further add the third compressed message to the initial variables a - h to obtain the final hash value.

[0119] Through the parallel computing unit, while the compression function module performs compression, the message word expansion module simultaneously performs the expansion calculation of the next message word, forming a parallel pipeline calculation of the compression function and the message word expansion, which improves the compression efficiency and the throughput rate of the compression process.

[0120] The message word expansion module and the compression function module together constitute a high-speed pipelined parallel computing unit. Since the hash function needs to perform R rounds of iterative calculations to compute the hash value, R compression function modules are constructed. Each compression function module is connected by registers to form a high-speed pipelined calculation of R rounds of the compression function (i.e., the first pipeline structure). Since the calculation of the compression function depends on the message words output by the message word expansion, and the first 16 message words do not need to be calculated and are only obtained from the message block to be compressed, R - 16 message word expansion calculation modules are constructed. When performing the i-th round of compression function calculation, the (i + 1)-th message word expansion calculation is performed to form a parallel pipeline calculation of the compression function and the message word expansion (i.e., the second pipeline structure).

[0121] Although the pipelined computing architecture is adopted to improve the throughput of the hash computing system, the computing path inside the compression function is relatively long. Generally speaking, the longer the computing path, the lower the processing frequency and the longer the required time. That is, the length of the current computing path inside the compression function severely limits the improvement of the accelerator operating frequency. Therefore, the hash algorithm or hash computing system provided by the embodiments of the present disclosure optimizes the path of the compression function module, inserts intermediate registers inside the compression function module, and the compression function that originally needed to be calculated in one cycle is obtained through 2 clock cycles of calculation, so as to achieve the purpose of path optimization. That is, the prior art requires 2t time for processing, while the embodiments of the present disclosure only require t time for processing.

[0122] Figure 3 The third optional flowchart of the hash method provided by the embodiments of the present disclosure is shown, and will be described according to each step.

[0123] Step S301: Pad the data to obtain the message to be compressed.

[0124] The specific step flow of step S301 is the same as that of step S101 or step S201, and will not be repeated here.

[0125] Figure 4 The data padding schematic diagram provided by the embodiments of the present disclosure is shown.

[0126] As Figure 4 shown, pad the data so that the length of the padded data is a multiple of 512 bits, because the message length processed by each round of the hash function is 512 bit.

[0127] When padding, add a 1 at the end of the data; add several 0s at the end of the data until the remainder of the message length modulo 512 is 448; add 64 bits of length at the end of the data to represent the number of bits of the original data.

[0128] Step S302: Compress the message to be compressed based on the first group of message words and the first pipeline structure to obtain a first compressed message.

[0129] The specific step flow of step S302 is the same as that of step S102 or step S202, and will not be repeated here.

[0130] Step S303: The message word expansion module determines the message words.

[0131] In some embodiments, the message word expansion module is disposed in the parallel computing unit, and the parallel computing unit is disposed in the second pipeline structure; the specific architecture of the second pipeline structure has been described in step S203 and will not be repeated here.

[0132] In the related art, the first 16 message words W0 to W of the message word expansion module 15 are directly grouped from the message to be compressed, and the remaining message words are obtained by the following iterative formula:

[0133] w t = σ1(w t-2 ) + w t-7 + σ0(w t-15 ) + w t-16

[0134] where, >>> represents circular right shift, >> represents right shift;

[0135] Due to the too long calculation path, the operation frequency is low, and thus the processing speed is slow; in the embodiments of the present disclosure, in order to shorten the calculation path of message word expansion and cooperate with the pipeline calculation of the compression function module, two registers w' t , w'' t are inserted in the middle of the original calculation path, and the two registers perform partial operations first.

[0136] Figure 5 FIG. shows a schematic structural diagram of the message expansion module provided by the embodiments of the present disclosure.

[0137] In some embodiments, the message word expansion module in the nth parallel computing unit is taken as an example for illustration. A first register and a second register are set in the message word expansion module; message word expansion operations are respectively performed based on the first register and the second register to obtain a first sub-message word and a second sub-message word; the (n + 1)th message word is determined based on the first sub-message word and the second sub-message word.

[0138] Specifically, as Figure 5 shown, the current message word group includes 16 message words, denoted as W0 to W 15. The first register determines a first sub-message word based on the first message word w t-15 and the second message word w t-16 in the current group of message words, where the first message word is the first message word in the current group of message words, and the second message word is the second message word in the current group of message words. The specific formula includes: w′ t =σ0(w t-15 ) + w t-16 . The second register determines a second sub-message word based on the third message word w t-2 and the fourth message word, w t-7 in the current group of message words. The specific formula includes: w″ t =σ1(w t-2 ) + w t-7 . Adding the first sub-message word and the second sub-message word to obtain the (n + 1)-th message word, specifically including:

[0139] w t =w′ t +w″ t

[0140] In some embodiments, the carrier replaces the last message word in the current group of message words based on the (n + 1)-th message word, and shifts all the message words in the current group of message words to the left by a first number of bits. Based on the left-shifted current group of message words, compression is performed on the second compressed message output by the n-th parallel computing unit. The first number of bits is the same as the length of the message word and can be 32.

[0141] Specifically, the newly generated message word is assigned to the register where the original message word W 15 is located, and W0 to W 15 are shifted to the left by 32 bits in sequence. The new group of message words is W1 to W 16 , and the subsequent message words (W 17 to W 63 ) are calculated in the same way. Through the above path optimization, the message word calculation originally completed in one clock cycle is converted into being completed in two clock cycles.

[0142] Step S304, the compression function module determines the calculation path.

[0143] In some embodiments, the compression function module is disposed in the parallel computing unit, and the parallel computing unit is disposed in the second pipeline structure; the specific architecture of the second pipeline structure has been described in step S203 and will not be repeated here.

[0144] In some embodiments, the compression function module in the nth parallel computing unit is taken as an example for illustration. An intermediate register is added in the compression function module, which is arranged between the input register and the output register, and the compression function paths among the input register, the intermediate register, and the output register included in the nth parallel computing unit are respectively determined; based on the compression function paths among the input register, the intermediate register, and the output register, the second compressed message is compressed.

[0145] Specifically, the carrier determines the compression function path between the input register and the intermediate register; determines the compression function path between the intermediate register and the output register; and determines the compression function path among the input register, the intermediate register, and the output register based on the compression function path between the input register and the intermediate register and the compression function path between the intermediate register and the output register.

[0146] In the related art, the calculation path from the input register to the output register is:

[0147]

[0148] In order to shorten the problem of low operating frequency and slow calculation speed caused by the too long calculation path from the input register to the output register, in the embodiments of the present disclosure, an intermediate register is inserted between the input register and the output register, and the original calculation path is changed into two relatively short calculation paths to improve the operating frequency.

[0149] Figure 6 The structural schematic diagram of the compression function module provided by the embodiments of the present disclosure is shown.

[0150] Specifically, as Figure 6 shown, the input register includes a t , b t , c t , d t , e t , f t , g t , h t ; the output register includes a t+1 , b t+1 , c t+1 , d t+1 , e t+1 , f t+1 , g t+1 and h t+1 ; the intermediate register includes α, a ′ , b ′ , c ′ , d ′ , e ′ , β, f ′ , g′ and γ.

[0151] When determining the compression function path between the input register and the intermediate register, the carrier determines the input of the sixth sub-register α in the intermediate register based on the outputs of the third sub-register a t , the fourth sub-register b t , and the fifth sub-register c t in the input register, and determines that a ′ is a t , b ′ is b t , c ′ is c t , d ′ is d t , e ′ is e t , and determines the input of the tenth sub-register β in the intermediate register based on the outputs of the seventh sub-register e t , the eighth sub-register f t , and the ninth sub-register g t in the input register, and determines that f ′ is f t , determines that g ′ is g t , and determines the input of the twelfth sub-register γ in the intermediate register based on the output of the eleventh sub-register h t in the input register. The specific formulas are as follows:

[0152] α = ∑0(a t ) + Maj(a t , b t , c t )

[0153] a ′ = a t

[0154] b ′ = b t

[0155] c ′ = c t

[0156] d ′ = d t

[0157] e ′ = e t

[0158] β = Σ1(e t ) + Ch(e t , f t , g t ​​)

[0159] f ′ = f t

[0160] g ′ = g t

[0161] γ = h t + K t + W t

[0162] Wherein, K t is a constant in the hash operation, and W t is a message word.

[0163] In the process of determining the compression function path between the intermediate register and the output register, the carrier determines the input of the thirteenth sub-register a t+1 in the output register based on the input of the sixth sub-register α, the input of the tenth sub-register β, and the input of the twelfth sub-register γ in the intermediate register; determines that b t+1 is a ′ , determines that c t+1 is b ′ , determines that d t+1 is c ′ , determines that based on the input of the fourteenth word register d ′ in the intermediate register, the input of the tenth sub-register β, and the input of the twelfth sub-register γ, determines the output of the fifteenth sub-register e t+1 in the output register, determines that f t+1 is e ′ , determines that g t+1 is f ′ , determines that h t+1 is g ′ . The specific formula is as follows:

[0164]

[0165] Step S305, compress the compressed message based on the current group of message words and the calculation path to obtain the third compressed message.

[0166] In some embodiments, the carrier generates the message words required for the next parallel computing unit based on the message word expansion path determined in step S303, compresses the compressed data based on the compression function path determined in step S304, and determines that the output of the last compression function module is the third compressed message.

[0167] Thus, through the hashing method described in the embodiments of the present disclosure, the path of the compression function module is optimized. An intermediate register is inserted inside the compression function. The compression function that originally needed one cycle to calculate is obtained through two clock cycles of calculation, so as to achieve the purpose of path optimization. The path of the message word expansion module is also optimized. A register is inserted inside the message word expansion module, so that the calculation cycle of the message word expansion module changes from one clock cycle to two clock cycles, and together with the compression function, a parallel pipeline architecture is formed.

[0168] Figure 7 FIG. shows an optional structural schematic diagram of a compression calculation system provided by an embodiment of the present disclosure, which will be described according to each part.

[0169] In some embodiments, the compression calculation system includes a central processing unit CPU 100, a random access memory RAM 200, a 32-bit data bus 300, and an SHA accelerator 400. The SHA accelerator is composed of a data padding module 410 and a high-speed pipeline calculation module 420. The high-speed pipeline calculation module is mainly composed of a message word expansion module 422 and a compression function module 421. When the system needs to verify data integrity, the central processing unit 100 transmits the message stored in the random access memory RAM 200 to the SHA accelerator 400 through the data bus. After receiving the compression instruction from the CPU, the SHA accelerator performs hash compression on the message, and the hashed value after compression is transmitted to the CPU or the RAM through the data bus.

[0170] The central processing unit CPU 100 sends instructions and addresses, and the random access memory RAM 200 responds to the request and transmits the message to be compressed to the SHA accelerator 400 through the 32-bit data bus 300. The SHA accelerator 400 is used to perform hash compression on the message. Then the central processing unit CPU 100 stores the compressed hashed value back to the random access memory RAM 200 through the data bus 300.

[0171] The data padding module 410 is used to pad the data to obtain the message to be compressed. Specifically, a first character, at least one second character, and at least one third character for characterizing the data length are added at the end of the data; wherein, the number of the at least one third character is a first preset value; the number of the at least one second character is determined based on a second preset value and the first preset value.

[0172] Figure 8 FIG. shows an optional structural schematic diagram of the high-speed pipeline calculation module provided by an embodiment of the present disclosure, which will be described according to each part.

[0173] As Figure 8As shown in the figure, the high-speed pipeline computing module 420 is mainly composed of a compression function 421 and a message word expansion module 422. In the embodiments of the present disclosure, the mainstream hash compression algorithm SHA-256 is adopted as a specific embodiment. The SHA-256 hash compression requires 64 rounds of compression function calculations. Therefore, 64 compression function modules are included in the high-speed pipeline architecture, and registers are inserted among the 64 compression function modules to achieve pipeline computing and accelerate hash compression. In addition, 64 message words are required in the 64-round iterative calculation. Therefore, the compression function and the message word expansion are combined into a parallel computing unit 423. However, there are only 48 such parallel computing units 423 in the high-speed pipeline architecture because the first 16 message words are directly composed of data filling groups and do not require calculation, and the last 48 message words need to be obtained through message word expansion calculation. To ensure the smooth execution of the pipeline, the calculation of the message word expansion is two clock cycles earlier than that of the compression function calculation, that is, the message word W used in the i (i>15) -th round of compression function calculation i is obtained from the message word expansion calculation in the previous round of the parallel computing unit. For example, the message word W used in the 16th round of compression function calculation 16 is completed in the clock cycle of the 15th round of parallel calculation. After completing 64 rounds of pipeline calculation, the result output by the last round of compression function calculation is added to the initial variables a - h to obtain the final hash value.

[0174] In some embodiments, the high-speed pipeline computing module includes a first pipeline structure and a second pipeline structure. The hash function needs to perform R rounds of iterative calculations to calculate the hash value. Therefore, R compression function modules are constructed, and each compression function module is connected by a register to form a high-speed pipeline calculation of R rounds of the compression function at a time. Since the calculation of the compression function depends on the message words output by the message word expansion, and the first 16 message words do not require calculation and are only obtained from the message block to be compressed, the high-speed pipeline is conceptually divided to determine that the first 15 compression function modules and registers form the first pipeline structure; based on the last 49 compression function modules and 48 registers, the second pipeline structure is determined. Since the 17th message word required for the calculation of the 17th compression function module needs to be generated based on the message word expansion module, in each second pipeline structure, there are 48 parallel computing units 423 composed of compression function modules and message word expansion modules, and 1 compression function module. That is to say, in the compression calculation system, R0 to R14 are compression function modules, R15 to R62 are parallel computing units, and R63 is a compression function module.

[0175] The message word expansion module included in the first parallel computing unit is used to generate the 17th message word (W 16 ), and the compression function module included in the first parallel computing unit is used to calculate based on the 16th message word (W15 ) Compress the first compressed message, transmit the obtained compressed message to the second parallel computing unit, and the second parallel computing unit generates the 18th message word (W 17 ), compress the compressed message based on the 17th message word until the 48th parallel computing unit. In the 48th parallel computing unit, the message word expansion module generates the 64th message word (W 63 ), and in the 48th parallel computing unit, the compression function module compresses based on the compressed data output by the 47th parallel computing unit and the 63rd message word (W 62 ), and outputs the compressed data to R63, that is, the last compression function module. The compression function module compresses the compressed message output by the 63rd parallel computing unit based on the 64th message word to obtain the third compressed data.

[0176] The carrier adds the result output by the last-round compression function calculation to the initial variables a - h to obtain the final hash value.

[0177] In specific implementation, the first pipeline structure includes at least one compression function module and at least one register, and one register is arranged between any two compression function modules;

[0178] The second pipeline structure includes at least one parallel computing unit and at least one register, and one register is arranged between any two parallel computing units;

[0179] Each parallel computing unit includes a message word expansion module and a compression function module;

[0180] The first pipeline structure is used to compress the message to be compressed to obtain the first compressed message;

[0181] The second pipeline structure is used to compress the first compressed message to obtain the third compressed message, specifically including compressing the second compressed message output by the nth parallel computing unit based on the (n + 1)th message word output by the nth parallel computing unit, and generating the (n + 2)th message word based on the (n + 1)th message word for the (n + 2)th parallel computing unit to use for compression.

[0182] The message word expansion module in the nth parallel computing unit is used for:

[0183] Performing message word expansion operations based on the first register and the second register respectively to obtain the first sub-message word and the second sub-message word;

[0184] Determining the (n + 1)th message word based on the first sub-message word and the second sub-message word.

[0185] The message word expansion module includes the first register and the second register;

[0186] The first register is used to determine a first sub-message word based on a first message word and a second message word in a current group of message words;

[0187] The second register is used to determine a second sub-message word based on a third message word and a fourth message word in the current group of message words;

[0188] Wherein, the first message word is the first message word in the current group of message words, and the second message word is the second message word in the current group of message words; the third message word is the ninth message word in the current group of message words, and the fourth message word is the 14th message word in the current group of message words.

[0189] The compression function module in the nth parallel computing unit is used for:

[0190] Determine the compression function path among the input register, the intermediate register and the output register included in the nth parallel computing unit;

[0191] Compress the second compressed message based on the compression function path among the input register, the intermediate register and the output register.

[0192] The compression function module in the nth parallel computing unit is used for:

[0193] Determine the compression function path between the input register and the intermediate register;

[0194] Determine the compression function path between the intermediate register and the output register;

[0195] Based on the compression function path between the input register and the intermediate register and the compression function path between the intermediate register and the output register, determine the compression function path among the input register, the intermediate register and the output register.

[0196] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0197] Figure 9 FIG. shows a schematic block diagram of an exemplary electronic device 800 that can be used to implement the embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely exemplary and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0198] As Figure 9 shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0199] Multiple components in the electronic device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disc, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0200] The computing unit 801 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 801 executes the various methods and processes described above, such as the hashing method. For example, in some embodiments, the hashing method can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the hashing method described above can be executed. Alternatively, in other embodiments, the computing unit 801 can be configured to execute the hashing method by any other appropriate means (e.g., by means of firmware).

[0201] The various embodiments of the systems and techniques described above in this specification can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from, and transmits data and instructions to, a storage system, at least one input device, and at least one output device.

[0202] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine, or entirely on the remote machine or server.

[0203] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0204] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0205] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

[0206] A computer system can include a client and a server. The client and the server are generally far from each other and usually interact through a communication network. The client - server relationship is generated by computer programs running on the respective computers and having a client - server relationship with each other. The server can be a cloud server, or a server of a distributed system, or a server incorporating a blockchain.

[0207] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution disclosed in this disclosure can be achieved, and no limitation is imposed herein.

[0208] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of this disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0209] As described above, it is only the specific implementation manner of the present disclosure. However, the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims described above.

Claims

1. A hashing method, characterized in that: The method comprises: Fill the data to obtain the message to be compressed; Inputting the message to be compressed and the first group of message words into a first pipeline structure composed of at least one compression function module and at least one register for compression to obtain a first compressed message; Inputting the first compressed message into a second pipeline structure; the second pipeline structure includes at least one parallel computing unit, at least one register group and a compression function module, the register group is arranged between any two parallel computing units, and any parallel computing unit includes a message word expansion module and a compression function module; Based on the n+1th message word output by the nth parallel computing unit, the second compressed message output by the nth parallel computing unit is compressed, and based on the n+1th message word, an n+2th message word is generated for compression by the n+2th parallel computing unit.

2. The method according to claim 1, characterized in that: The step of filling the data to obtain the message to be compressed includes: Adding a first character, at least one second character, and at least one third character for representing the length of the data at the end of the data; The number of the at least one third character is a first preset value; and the number of the at least one second character is determined based on a second preset value and the first preset value.

3. The method according to claim 1, characterized in that The first pipeline structure includes at least one compression function module, a register is set between any two compression function modules, and the message to be compressed and the first group of message words are input into the first pipeline structure composed of at least one compression function module and at least one register for compression to obtain a first compressed message, including: inputting the message to be compressed and the first group of message words into the first pipeline structure; Each compression function module performs compression based on the message to be compressed and the first group of message words, and transfers the compressed data to the next compression function module for compression based on the register, and determines that in the first pipeline structure, the output of the last compression function module is the first compressed message.

4. The method according to claim 1, characterized in that: The step of inputting the first compressed message into the second pipeline structure comprises: The first compressed message is input to the second pipeline structure through a register between the first pipeline structure and the second pipeline structure.

5. The method according to claim 1, characterized in that: Before compressing the second compressed message output by the nth parallel computing unit based on the n+1th message word output by the nth parallel computing unit, the method further includes outputting the n+1th message word based on the nth parallel computing unit, specifically including: In a message word expansion module included in the nth parallel computing unit, a first register and a second register are set; Performing a message word expansion operation based on the first register and the second register respectively to obtain a first sub-message word and a second sub-message word; An (n+1)th message word is determined based on the first sub-message word and the second sub-message word.

6. The method according to claim 5, characterized in that The method of performing a message word expansion operation based on the first register and the second register to obtain a first message word and a second sub-message word includes: The first register determines a first sub-message word based on the first message word and the second message word in the current group of message words; The second register determines the second sub-message word based on the third message word and the fourth message word in the current group message word; Among them, the first message word is the first message word in the current group of message words, the second message word is the second message word in the current group of message words; the third message word is the ninth message word in the current group of message words, and the fourth message word is the fourteenth message word in the current group of message words.

7. The method according to claim 5, characterized in that The determining the (n+1)th message word based on the first sub-message word and the second sub-message word comprises: The first sub-message word and the second sub-message word are added to obtain the (n+1)th message word.

8. The method according to claim 5, characterized in that After obtaining the n+1th message word, the method further comprises: The last message word in the current group of message words is replaced based on the n+1th message word, and all message words in the current group of message words are shifted left by the first digit, and the second compressed message output by the nth parallel computing unit is compressed based on the left-shifted current group of message words.

9. The method according to claim 1, characterized in that: The compressing the second compressed message output by the nth parallel computing unit based on the (n+1)th message word output by the nth parallel computing unit comprises: Determine a compression function path between an input register, an intermediate register, and an output register included in the nth parallel computing unit; The second compressed message is compressed based on a compression function path between the input register, the intermediate register and the output register.

10. The method according to claim 9, characterized in that The step of determining a compression function path between an input register, an intermediate register, and an output register included in the nth parallel computing unit comprises: determining a compression function path between an input register and an intermediate register; determining a compression function path between the intermediate register and the output register; Based on the compression function path between the input register and the intermediate register, and the compression function path between the intermediate register and the output register, a compression function path between the input register, the intermediate register and the output register is determined.

11. The method according to claim 10, characterized in that The determining of the compression function path between the input register and the intermediate register comprises: Determine the input of the sixth subregister in the intermediate register based on the outputs of the third subregister, the fourth subregister, and the fifth subregister in the input register; Determine the input of the tenth subregister in the intermediate register based on the outputs of the seventh subregister, the eighth word register, and the ninth subregister in the input register; Based on the output of the eleventh sub-register in the input register, an input of the twelfth sub-register in the intermediate register is determined.

12. The method according to claim 10, characterized in that The step of determining a compression function path between the intermediate register and the output register comprises: Determine an input of a thirteenth subregister in the output register based on an input of a sixth subregister, an input of a tenth subregister, and an input of a twelfth subregister in the intermediate register; An input of a fifteenth sub-register in the output register is determined based on an input of a fourteenth sub-register, an input of a tenth sub-register, and an input of a twelfth sub-register in the intermediate register.

13. A hash calculation system, characterized in that: The system includes a first pipeline structure and a second pipeline structure; The first pipeline structure includes at least one compression function module and at least one register, and a register is provided between any two compression function modules; The second pipeline structure includes at least one parallel computing unit and at least one register, and a register is provided between any two parallel computing units; Each parallel computing unit includes a message word expansion module and a compression function module; The first pipeline structure is used to compress the message to be compressed to obtain a first compressed message; The second pipeline structure is used to compress the first compressed message to obtain a third compressed message, specifically including compressing the second compressed message output by the nth parallel computing unit based on the n+1th message word output by the nth parallel computing unit, and generating the n+2th message word based on the n+1th message word for compression by the n+2th parallel computing unit.

14. The system according to claim 13, characterized in that The message word expansion module in the nth parallel computing unit is used for: Performing a message word expansion operation based on the first register and the second register respectively to obtain a first sub-message word and a second sub-message word; An (n+1)th message word is determined based on the first sub-message word and the second sub-message word.

15. The system according to claim 14, characterized in that The message word expansion module includes a first register and a second register; The first register is used to determine the first sub-message word based on the first message word and the second message word in the current group message word; The second register is used to determine the second sub-message word based on the third message word and the fourth message word in the current group message word; Among them, the first message word is the first message word in the current group of message words, the second message word is the second message word in the current group of message words; the third message word is the ninth message word in the current group of message words, and the fourth message word is the fourteenth message word in the current group of message words.

16. The system according to claim 13, characterized in that The compression function module in the nth parallel computing unit is used for: Determine a compression function path between an input register, an intermediate register, and an output register included in the nth parallel computing unit; The second compressed message is compressed based on the compression function path between the input register, the intermediate register and the output register.

17. The system according to claim 16, wherein the compression function module in the nth parallel computing unit is used for: determining a compression function path between an input register and an intermediate register; determining a compression function path between the intermediate register and the output register; Based on the compression function path between the input register and the intermediate register, and the compression function path between the intermediate register and the output register, a compression function path between the input register, the intermediate register and the output register is determined.

18. An electronic device, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1 to 12.

19. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to make a computer execute the method according to any one of claims 1-12.

20. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 12.

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