Solar cell and preparation method thereof

Abstract

The invention provides a solar cell and a preparation method thereof. The solar cell comprises a silicon substrate, the front surface of the silicon substrate is provided with a textured structure, the front surface of the silicon substrate is divided into a working area and an edge isolation area, the working area comprises a p-type emitter, a first passivation layer and a first electrode which are sequentially arranged on the front surface from inside to outside, and the edge isolation area comprises the first passivation layer arranged on the front surface. A tunneling oxide layer, an n-type doped polycrystalline silicon layer, a second passivation layer and a second electrode are sequentially arranged on the back face of the silicon substrate from inside to outside, the reflectivity of the suede structure in the working area is R1, the reflectivity of the suede structure in the edge isolation area is R2, R1 / R2 is within the range of 0.3-3, and R2 is within the range of 0.3-3. And the distance between the suede structure substrate of the working area and the suede structure substrate of the edge isolation area is within the range of 3-10 [mu] m.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] TOPCon (Tunnel Oxide Passivated Contact) solar cells rely on the synergistic passivation effect of the ultra-thin tunneling oxide layer and the doped polysilicon layer on the back surface, significantly reducing the carrier recombination loss and achieving high open-circuit voltage and high conversion efficiency. However, to meet the technical requirements of half-cell technology in the module end, the cell needs to be sliced by laser cutting. The silicon substrate surface exposed by the cutting section forms dangling bonds and defect states due to laser thermal damage. The dangling bonds and defect states become strong recombination centers for carriers, resulting in a cell efficiency loss of 0.1% - 0.2% after slicing, which restricts the power output of the module.

[0003] In response to the above problems, various paths have been tried for optimization in the prior art. Currently, the mainstream edge passivation technology in the industry covers an alumina passivation layer on the cutting surface through atomic layer deposition (ALD). Although it can improve the module power, it requires high-temperature annealing and special equipment, with high process costs, and the problem of passivation layer overplating is prominent, affecting the appearance consistency of the cell. The patent application with the publication number CN118507594A discloses a solution of "setting polished surface isolation areas on both sides of the cutting area", which reduces recombination by physically blocking the lateral migration path of carriers. However, its polished surface reflectivity is as high as 30% - 40%, losing part of the light, reducing the short-circuit current of the cell. At the same time, due to the laser damage being difficult to remove, the passivation of the isolation area is poor and the PL image is black, affecting the open-circuit voltage of the cell. Although the patent application with the publication number CN119029092A discloses a nanosecond laser etching and step-by-step cleaning process to improve passivation by forming a planar or textured structure, and adjusts the surface morphology of the isolation area by adjusting the spot overlap rate, this technology is complex to operate. Moreover, the inventors of the present application found that when using an alkaline solution to remove the residual boron emitter in the isolation area, the boron emitter in the working area is also damaged, thus affecting the light absorption rate and short-circuit current of the solar cell.

[0004] Therefore, the industry urgently needs to develop a new TOPCon solar cell structure and preparation method that can block the carrier recombination channel while taking into account high light absorption rate and short-circuit current. Summary of the Invention

[0005] Aiming at the problems of low light utilization rate and low short-circuit current of the sliced cells with isolation areas in the prior art, the present invention provides a solar cell and a preparation method thereof.

[0006] The first aspect of the present application provides a solar cell, which includes a silicon substrate. The front surface of the silicon substrate has a textured structure. The front surface of the silicon substrate is divided into a working area and an edge isolation area. The working area includes a p-type emitter, a first passivation layer, and a first electrode sequentially arranged on the front surface from inside to outside. The edge isolation area includes a first passivation layer arranged on the front surface. On the back surface of the silicon substrate, a tunneling oxide layer, an n-type doped polysilicon layer, a second passivation layer, and a second electrode are sequentially arranged from inside to outside. Among them, the reflectivity of the textured structure in the working area is R1, and the reflectivity of the textured structure in the edge isolation area is R2. The value of R1 / R2 is in the range of 0.3 - 3, and the distance between the textured structure substrate in the working area and the textured structure substrate in the edge isolation area is in the range of 3 μm - 10 μm.

[0007] The solar cell with the above structure realizes multiple reflections and scatterings by arranging a textured structure on the front surface to reduce light reflection loss and enhance light absorption efficiency, thereby improving the photoelectric conversion performance of the cell; by setting the edge isolation area to separate the p-type emitters, the recombination loss of the entire p-type emitter can be reduced; by arranging passivation layers outside the p-type emitter and the edge isolation area, surface carrier recombination can be inhibited, light absorption and carrier selective transport can be optimized, thereby improving the open-circuit voltage, short-circuit current, and the overall conversion efficiency of the cell; at the same time, controlling the reflectivity ratio of the textured structures in the working area and the edge isolation area within the range of 0.3 - 3 not only realizes the optical property regulation of specific film layers, but also this reflectivity ratio can reduce the local light intensity difference, making the generation and collection of carriers more uniform and maintaining a stable carrier transport path; controlling the distance between the textured structure substrate in the working area and the textured structure substrate in the edge isolation area within the range of 3 μm - 10 μm can not only cut off the pn junction for insulation isolation, but also avoid over-etching damage to the silicon substrate.

[0008] In any implementation manner of the first aspect, the reflectivity R1 is 7% - 15%. The above low-reflectivity design of the working area can reduce the surface reflection loss of incident light, especially enhance the absorption of long-wavelength light, thereby improving the short-circuit current.

[0009] In any implementation manner of the first aspect, the reflectivity R2 is 7% - 30%. Controlling the reflectivity of the edge isolation area within the above range not only realizes the passivation contact performance, optimizes the light utilization rate, but also avoids the process instability problem caused by extreme reflectivity.

[0010] In any implementation manner of the first aspect, the minimum size of the edge isolation area in the direction away from the working area is in the range of 10 μm - 1000 μm.

[0011] In any implementation manner of the first aspect, the edge isolation area is a rectangular area.

[0012] In any embodiment of the first aspect, the silicon substrate is an N-type silicon substrate. Optionally, the silicon base is a single-crystalline silicon wafer doped with phosphorus atoms; optionally, the resistivity of the silicon substrate is 0.1 Ω·cm - 100 Ω·cm; optionally, the thickness of the silicon substrate is 100 μm - 500 μm.

[0013] In any embodiment of the first aspect, the doping concentration of the p-type emitter is 2×10 18  atoms / cm 3 - 1×10 19 atoms / cm 3 . Optionally, the junction depth of the p-type emitter is 0.5 μm - 2 μm.

[0014] In any embodiment of the first aspect, the tunneling oxide layer includes one or more of silicon oxide, silicon nitride, and aluminum oxide.

[0015] In any embodiment of the first aspect, the thickness of the tunneling oxide layer is 0.5 nm - 2.5 nm.

[0016] In any embodiment of the first aspect, the thickness of the n-type doped polysilicon layer is 100 nm - 300 nm.

[0017] In any embodiment of the first aspect, the doping concentration of the n-type doped polysilicon layer is 3×10 20  atoms / cm 3 - 1×10 21 atoms / cm 3 .

[0018] In any embodiment of the first aspect, the first passivation layer and the second passivation layer each independently include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, or silicon oxynitride.

[0019] In any embodiment of the first aspect, the first electrode and the second electrode each independently include at least one of silver, silver alloy, copper, copper alloy, or a nickel / copper / silver multi-layer electrode.

[0020] The second aspect of the present application provides a method for manufacturing a solar cell, the manufacturing method comprising the following steps: S1, texturing the front surface of a silicon substrate to obtain a first textured surface; S2, preparing a p-type emitter on the front surface of the textured silicon substrate, and sequentially preparing a tunneling oxide layer and an n-type doped polysilicon layer on the back surface of the silicon substrate; S3, using a green picosecond laser to remove the p-type emitter at a preset position to form a pre-isolation region; S4, pickling to remove the peripheral phosphorus silicate glass and peripheral phosphorus borosilicate glass on the front surface; S5, re-texturing the front surface using an alkaline solution comprising a texturing additive to form a second textured surface in the pre-isolation region; S6, pickling to remove the borosilicate glass on the front surface and the phosphorus silicate glass on the back surface; S7, passivating the front and back surfaces; S8, respectively disposing electrodes on the front and back surfaces; S9, performing laser non-destructive cutting, the cutting site being within the pre-isolation region or on one side of the pre-isolation region, wherein the reflectivity of the first textured surface is R1, the reflectivity of the second textured surface is R2, R1 / R2 is within the range of 0.3 - 3, and the distance between the substrate of the first textured surface and the substrate of the second textured surface is within the range of 3 μm - 10 μm.

[0021] In the above manufacturing method, in step S3, the pre-isolation region formed by using the green picosecond laser cuts off the pn junction, isolating the emitters on both sides of the isolation region, providing space for subsequent electrode isolation and cutting. Moreover, compared with the nanosecond laser, the green picosecond laser can more thoroughly remove the p-type emitter in the pre-isolation region without residue of the p-type emitter, increasing the processing process window of the isolation region. Therefore, during the alkaline solution treatment in step S5, it is not necessary to remove the remaining p-type emitter in the pre-isolation region. Only the peripherally plated n-type doped polysilicon on the positive surface needs to be removed by using this alkaline solution. At the same time, due to the absence of the p-type emitter blocking in the pre-isolation region, this alkaline solution can also remove the borosilicate melt and laser damage generated in the pre-isolation region, and texture the pre-isolation region to increase the etching depth of the pre-isolation region and obtain the second textured surface, reducing the reflectivity of the isolation region to light, that is, increasing the light absorption rate in the isolation region and effectively improving the short-circuit current. The above steps cooperate with each other, not only realizing the zonal regulation of the reflectivity of the isolation region and the working region, increasing the light absorption rate in the isolation region, but also avoiding damage to the p-type emitter in the working region, thus effectively improving the short-circuit current. Moreover, the first textured surface and the second textured surface effectively improve the open-circuit voltage of the battery. The overall manufacturing method is efficient and convenient, which is conducive to mass production. At the same time, since a controllable pyramid structure can be formed after texturing the isolation region, the light utilization rate of the non-destructive laser scribing is higher. Compared with other structures, the power of the laser non-destructive cutting can be further reduced, so that the cutting damage is more controllable.

[0022] In any implementation manner of the second aspect, the wavelength of the green picosecond laser is 532 nm or 1064 nm. Optionally, the radiation power of the green picosecond laser is 1 W - 50 W. Optionally, the spot overlap rate of the green picosecond laser is 40% - 80%. Optionally, the energy density of the green picosecond laser is 100 mJ / cm2 -400 mJ / cm 2 The pulse duration of the picosecond laser is short and the peak power is high. It can focus and release a large amount of energy in an extremely short time, so that it has a very efficient etching effect on the p-type emitter in the pre-isolation region, and the thermal damage and mechanical damage are small.

[0023] In any implementation manner of the second aspect, the reflectivity R1 of the first matte surface is 7% - 15%.

[0024] In any implementation manner of the second aspect, the reflectivity R2 of the second matte surface is 7% - 30%.

[0025] In any implementation manner of the second aspect, the distance between two adjacent emitters after the pre-isolation region is formed is in the range of 10 μm - 1000 μm.

[0026] In any implementation manner of the second aspect, in step S4, the acid solution used for pickling is an HF solution with a concentration of 5% - 30%, and the pickling time is 10 s - 70 s.

[0027] In any implementation manner of the second aspect, in step S5, the mass ratio of the alkali in the alkali solution to the texturing additive is 1:2 - 5:1. Optionally, the temperature of texturing is 65°C - 85°C. Optionally, the texturing time is 600 s - 900 s. Description of the Drawings

[0028] The drawings here are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0029] Figure 1 It is a schematic cross-sectional structure diagram of the solar cell provided in Embodiment 1 of the present invention.

[0030] Figure 2 It shows a flowchart of the preparation method of the solar cell provided in an implementation manner of the present invention.

[0031] Figure 3 It is a schematic cross-sectional structure diagram of the solar cell provided in Comparative Example 1 of the present invention.

[0032] Figure 4 It is a schematic cross-sectional structure diagram of the solar cell provided in Embodiment 8 of the present invention.

[0033] Figure 5 It is a planar SEM image and a cross-sectional SEM image of the first matte surface and the second matte surface of the solar cell provided in Embodiment 1 of the present invention.

[0034] Figure 6Morphological plan SEM images and cross-sectional SEM images of the first and second textured surfaces of the solar cell provided in Comparative Example 1 of the present invention.

[0035] Figure 7 Morphological plan SEM images and cross-sectional SEM images of the first and second textured surfaces of the solar cell provided in Example 8 of the present invention.

[0036] Reference numerals:

[0037] 1 - silicon substrate, 2 - p-type emitter, 3 - tunneling oxide layer, 4 - n-type doped polysilicon layer, 5 - first passivation layer, 6 - second passivation layer, 7 - first electrode, 8 - second electrode. Detailed implementation manners

[0038] The implementation manners of the present invention will be described in detail below in conjunction with the drawings and examples. However, those skilled in the art will understand that the following examples are only used to illustrate the present invention and should not be construed as limiting the scope of the present invention. For those not specified in the examples, they are carried out under conventional conditions or conditions recommended by the manufacturer. For reagents or instruments not specified by the manufacturer, they are all conventional products that can be obtained commercially. If not otherwise specified, the concentrations mentioned in this application are mass contents. Taking a 20% HF solution as an example, it means that the mass content of HF in the solution is 20%.

[0039] If not otherwise specified, the technical terms or scientific terms used in this application should have the ordinary meaning understood by those of ordinary skill in the art belonging to the field of this disclosure. If not otherwise specified, the "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. All steps of this application can be carried out in sequence or randomly, and preferably in sequence. If not otherwise specified, the "including" and "comprising" mentioned in this application mean open-ended. For example, the "including" and "comprising" can mean that other components not listed can also be included or comprised.

[0040] To solve the problem of low light absorption rate and short - circuit current in TOPCon solar cells after setting the isolation region, this application conducted in - depth research and found that the direct reason is that when using lye to remove the residual boron emitter in the isolation region, the boron emitter in the working area is also damaged, affecting the light absorption rate and short - circuit current. However, since the boron emitters in the isolation region and the working area have the same composition, it is difficult to avoid damaging the boron emitter in the working area when removing the boron emitter in the isolation region. To avoid this damage, this application solves the problem at the root, that is, when using laser treatment, the boron emitter in the pre - formed isolation region is completely removed, and the reflectivity of the isolation region is adjusted to match the reflectivity of the working area to improve the light absorption rate. Based on this technical idea, this application provides a solar cell and its manufacturing method.

[0041] The first embodiment of this application provides a solar cell, as Figure 1 shown, the solar cell includes a silicon substrate 1. The front surface of the silicon substrate 1 has a textured structure. The front surface of the silicon substrate is divided into a working area and an edge isolation area. The working area includes a p - type emitter 2, a first passivation layer 5, and a first electrode 7 arranged on the front surface in sequence from inside to outside. The edge isolation area includes a first passivation layer arranged on the front surface. The back surface of the silicon substrate is provided with a tunneling oxide layer 3, an n - type doped polysilicon layer 4, a second passivation layer 6, and a second electrode 8 in sequence from inside to outside. Among them, the reflectivity of the textured structure in the working area is R1, the reflectivity of the textured structure in the edge isolation area is R2, and R1 / R2 is in the range of 0.3 - 3. And the distance h between the textured structure substrate in the working area and the textured structure substrate in the edge isolation area is in the range of 3μm - 10μm.

[0042] The applicant found that: in the above - mentioned solar cell structure, setting a textured structure on the front surface can reduce light reflection loss through multiple reflections and scattering, enhance the light absorption efficiency, and thus improve the photoelectric conversion performance of the battery; by setting the edge isolation area to separate the p - type emitters, the recombination loss of the entire p - type emitter can be reduced; setting a passivation layer outside the p - type emitter and the edge isolation area can inhibit surface carrier recombination, optimize light absorption and carrier selective transport, thereby improving the open - circuit voltage, short - circuit current, and the overall conversion efficiency of the battery; at the same time, controlling the reflectivity ratio of the textured structures in the working area and the edge isolation area within the range of 0.3 - 3 not only realizes the optical property regulation of specific film layers, but also this reflectivity ratio can reduce the local light intensity difference, making the generation and collection of carriers more uniform and maintaining a stable carrier transport path; controlling the distance h between the textured structure substrate in the working area and the textured structure substrate in the edge isolation area within the range of 3μm - 10μm can both cut off the pn junction for insulation and isolation, and avoid over - deep etching damage to the silicon substrate.

[0043] In some embodiments, the above R1 / R2 is 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3 or within the range of any two of the above values. In a preferred embodiment, R1 / R2 is 0.3 - 1.9, such as 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.875, 1.9 or within the range of any two of the above values.

[0044] In some embodiments, the reflectivity R1 is 7% - 15%, such as 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15% or within the range of any two of the above values. The above low - reflectivity design of the passivated p - type emitter can reduce the surface reflection loss of incident light, especially enhance the absorption of long - wavelength light, thereby improving the short - circuit current.

[0045] In some embodiments, the reflectivity R2 is 7% - 30%, such as 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30% or within the range of any two of the above values. By controlling the reflectivity of the passivated isolation region within the above range, both the passivation contact performance and the light utilization rate are achieved, while avoiding the process instability problem caused by extreme reflectivity.

[0046] In some embodiments, as Figure 1 shown, the minimum dimension b of the edge isolation region in the direction away from the working region is in the range of 10μm - 1000μm, such as 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm or within the range of any two of the above values. The design of this width range balances the isolation effect, passivation effect, and light utilization rate of the edge isolation region, while reserving a higher working window for laser slicing, which is beneficial to improving the subsequent slicing alignment problem, making the component efficiency better, and at the same time meeting the requirements of different application scenarios for voltage resistance, appearance, and quality reliability.

[0047] In some embodiments, the edge isolation region is a rectangular region, and the regular rectangular boundary can be precisely controlled by the laser direct writing process, which can not only ensure the isolation of the pn junction but also facilitate the vertical arrangement of the gate line electrodes to form a match.

[0048] In some embodiments, the silicon substrate is an N-type silicon substrate. In some embodiments, the N-type silicon substrate includes a single-crystalline silicon wafer doped with phosphorus atoms, a polycrystalline silicon wafer doped with phosphorus atoms, a single-crystalline silicon wafer doped with arsenic, and a single-crystalline silicon wafer doped with antimony.

[0049] In some embodiments, the resistivity of the silicon substrate is 0.1 Ω·cm - 100 Ω·cm, such as 0.1 Ω·cm, 0.2 Ω·cm, 0.3 Ω·cm, 0.4 Ω·cm, 0.5 Ω·cm, 0.6 Ω·cm, 0.7 Ω·cm, 0.8 Ω·cm, 0.9 Ω·cm, 1 Ω·cm, 5 Ω·cm, 10 Ω·cm, 20 Ω·cm, 30 Ω·cm, 40 Ω·cm, 50 Ω·cm, 60 Ω·cm, 70 Ω·cm, 80 Ω·cm, 90 Ω·cm, 100 Ω·cm or within the range of any two of the above values. The silicon substrate within the above resistivity range helps to improve the carrier migration speed, thereby improving the performance of the battery.

[0050] In some embodiments, the thickness of the silicon substrate is 100 μm - 500 μm, such as 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm or within the range of any two of the above values. A too thin silicon substrate may lead to insufficient light absorption, while a too thick one may increase the resistance loss. By selecting the appropriate thickness of the silicon substrate as described above, the light absorption and current collection efficiency are balanced.

[0051] In some embodiments, the doping concentration of the p-type emitter is 2×10 18  atoms / cm 3 - 1×10 19 atoms / cm 3 ,for example 2×10 18  atoms / cm 3 、3×10 18  atoms / cm 3 、4×10 18  atoms / cm 3 、5×10 18  atoms / cm 3 、6×10 18  atoms / cm 3 、7×10 18  atoms / cm 3 、8×10 18atoms / cm 3 ,9×10 18 atoms / cm 3 , 1×10 19 atoms / cm 3 Or within the range of any two of the above values. A moderate doping concentration of the p-type emitter can improve the electrical properties of the p-type emitter, both forming a good junction structure and avoiding carrier recombination caused by excessive doping.

[0052] In some embodiments, the junction depth of the p-type emitter is 0.5 μm-2 μm, such as 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 0.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, 2 μm, or within the range of any two of the above values. The above junction depth can optimize the collection efficiency of carriers and reduce the recombination loss in the junction area, thereby improving the open circuit voltage and overall performance of the battery.

[0053] In some embodiments, the tunnel oxide layer includes one or more of silicon oxide, silicon nitride, and aluminum oxide, and / or the thickness of the tunnel oxide layer is 0.5 nm to 2.5 nm. Selecting tunnel oxide layers of different materials or thicknesses can adjust their conductivity and dielectric properties, and adaptively improve the photoelectric conversion efficiency and stability of the battery.

[0054] In some embodiments, the thickness of the n-type doped polysilicon layer is 100nm-300nm, such as 100nm, 1100nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm, 300nm, or within the range of any two of the above values. The n-type doped polysilicon layer with this thickness range helps to improve the passivation effect and the dielectric effect, and minimizes the contact resistance of the metal electrode, thereby improving the efficiency and reliability of the battery.

[0055] In some embodiments, the doping concentration of the n-type doped polysilicon layer is 3×10 20 atoms / cm 3 - 1×10 21 atoms / cm 3 , for example 3×10 20 atoms / cm 3 , 4×10 20 atoms / cm 3 , 5×10 20atoms / cm 3 、6×10 20 atoms / cm 3 、7×10 20 atoms / cm 3 、8×10 20 atoms / cm 3 、9×10 20 atoms / cm 3 、1×10 21 atoms / cm 3 or within the range of any two of the above values.

[0056] In some embodiments, the first passivation layer and the second passivation layer each independently include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, or silicon oxynitride. The use of the above materials helps to reduce surface defects and recombination, improve the stability and efficiency of the battery, especially enhance the surface passivation effect, and avoid the recombination loss of current.

[0057] In some embodiments, the first electrode and the second electrode each independently include at least one of silver, silver alloy, copper, copper alloy, and nickel / copper / silver multi-layer electrode. The above metal materials can ensure good electrical conductivity, stability, and corrosion resistance during long-term use of the electrode, thereby optimizing the current conduction performance and efficiency of the battery.

[0058] The second embodiment of the present application provides a method for manufacturing a solar cell, as Figure 2 shown. The manufacturing method includes the following steps: S1, texturing the front surface of the silicon substrate to obtain a first textured surface; S2, preparing a p-type emitter on the front surface of the textured silicon substrate, and sequentially preparing a tunneling oxide layer and an n-type doped polysilicon layer on the back surface of the silicon substrate; S3, using a green picosecond laser to remove the p-type emitter at a preset position to form a pre-isolation region; S4, pickling to remove the wrap-around phosphosilicate glass and wrap-around phosphoborosilicate glass on the front surface; S5, re-texturing the front surface with an alkaline solution including a texturing additive to form a second textured surface in the pre-isolation region; S6, pickling to remove the borosilicate glass on the front surface and the phosphosilicate glass on the back surface; S7, passivating the front and back surfaces; S8, respectively setting electrodes on the front and back surfaces; S9, performing laser non-destructive cutting, and the cutting part is within or on one side of the pre-isolation region. Among them, the reflectivity of the first textured surface is R1, the reflectivity of the second textured surface is R2, R1 / R2 is within the range of 0.3 - 3, and the distance h between the first textured surface substrate and the second textured surface substrate is within the range of 3μm - 10μm.

[0059] In the above preparation method, in step S3, the pre-isolation region formed by using a green picosecond laser cuts off the pn junction, isolating the emitters on both sides of the isolation region, providing space for subsequent electrode isolation and cutting. Moreover, compared with nanosecond lasers, the green picosecond laser can more thoroughly remove the P-type emitter in the pre-isolation region without residue of the P-type emitter, which can increase the processing process window of the isolation region. Therefore, during the alkali treatment in step S5, it is not necessary to remove the remaining P-type emitter in the pre-isolation region. Only the n-type doped polysilicon deposited around the positive surface needs to be removed using this alkali solution. At the same time, since there is no P-type emitter blocking in the pre-isolation region, this alkali solution can also remove the boron-silicon melt and laser damage generated in the pre-isolation region, and texture the pre-isolation region to increase the etching depth of the pre-isolation region and obtain a second textured surface, reducing the reflectivity of light in the isolation region, that is, increasing the absorption rate of light in the isolation region and effectively improving the short-circuit current. The above steps cooperate with each other, not only realizing the zonal regulation of the reflectivity of the isolation region and the working region, increasing the absorption rate of light in the isolation region, but also avoiding damage to the p-type emitter in the working region, thus effectively improving the short-circuit current. And the first textured surface and the second textured surface effectively improve the open-circuit voltage of the battery. The overall preparation method is efficient and convenient, which is conducive to mass production. At the same time, since a controllable pyramid structure can be formed after the isolation region is textured, the light utilization rate of non-destructive laser scribing is higher. Compared with other structures, the power of non-destructive laser cutting can be further reduced, so the cutting damage is more controllable.

[0060] The above preparation method will be described below according to the order of step execution.

[0061] First, perform step S1 to texture the front surface of the silicon substrate to obtain a first textured surface. The first textured surface formed in step S1 can enhance the light trapping ability and reduce reflection loss.

[0062] Perform step S2 to prepare a p-type emitter on the front surface of the textured silicon substrate and sequentially prepare a tunneling oxide layer and an n-type doped polysilicon layer on the back surface of the silicon substrate. The methods for preparing the p-type emitter, tunneling oxide layer, and n-type doped polysilicon layer can refer to conventional technologies and will not be elaborated here.

[0063] The p-type emitter prepared in step S2 on the front surface realizes the pn junction, and the tunneling oxide layer and n-type doped polysilicon layer prepared on the back surface form a passivated contact structure, improving the carrier selectivity.

[0064] Perform step S3 to remove the p-type emitter at a preset position using a green picosecond laser to form a pre-isolation region.

[0065] In some embodiments, the wavelength of the green picosecond laser is 532 nm or 1064 nm. Picosecond laser refers to a laser with a pulse duration at the picosecond level (10 -12a laser with a pulse width of picoseconds (ps). The pulse duration of the picosecond laser is very short, so it has a higher peak power and can focus and release a large amount of energy in an extremely short time, thus having a very efficient etching effect on the p-type emitter in the pre-isolation region and causing less thermal damage and mechanical damage.

[0066] In some embodiments, the radiation power of the green picosecond laser is 1W - 50W, such as 1W, 2W, 3W, 4W, 5W, 6W, 7W, 8W, 9W, 10W, 15W, 20W, 25W, 30W, 35W, 40W, 45W, 50W or within the range of any two of the above values.

[0067] In some embodiments, the spot overlap rate of the green picosecond laser is 40% - 80%, such as 40%, 50%, 60%, 70%, 80% or within the range of any two of the above values. It should be noted that the above embodiments control the spot overlap rate of the green picosecond laser, and its main purpose is to improve the working efficiency of laser processing, and it is not expected to form a textured surface in the isolation region.

[0068] In some embodiments, the energy density of the green picosecond laser is 100 mj / cm 2 - 400 mj / cm 2 , such as 100 mj / cm 2 、150 mj / cm 2 、200 mj / cm 2 、250 mj / cm 2 、300 mj / cm 2 、350 mj / cm 2 、400 mj / cm 2 or within the range of any two of the above values. The radiation power, spot overlap rate, and energy density within the above ranges can achieve a processing effect with higher precision and lower thermal damage, while taking into account both efficiency and quality.

[0069] Perform step S4 to remove the circumferential phosphosilicate glass and circumferential phosphoborosilicate glass on the front surface by pickling.

[0070] In some embodiments, the acid solution used for pickling in step S4 is an HF solution with a concentration of 5% - 30%, such as 5%, 7%, 8%, 9%, 10%, 15%, 20%, 25%, 30% or within the range of any two of the above values. This concentration range can effectively dissolve the phosphosilicate glass and phosphoborosilicate glass on the surface of the silicon wafer, while avoiding excessive corrosion of the silicon substrate, thus maintaining the flatness and electrical properties of the silicon wafer surface.

[0071] In some embodiments, in step S4, the pickling time is 10 s - 70 s, such as 10 s, 20 s, 30 s, 40 s, 50 s, 60 s, 70 s or within the range of any two of the above values. Appropriate time control can ensure that the phosphosilicate glass or phosphoborosilicate glass is fully removed, while avoiding excessive corrosion of the silicon wafer surface, thereby maintaining good surface morphology and electrical properties.

[0072] Perform step S5, and use an alkaline solution containing a texturing additive to re-texture the front side to form a second textured surface in the pre-isolation region.

[0073] In some embodiments, in step S5, there is no particular limitation on the alkaline solution used for texturing, as long as its alkaline corrosion characteristics can form a textured surface structure on the silicon wafer surface. In a preferred embodiment, the alkaline solution used for texturing in step S5 is a NaOH or KOH solution. Compared with other alkaline solutions, NaOH or KOH has the characteristics of stable reaction rate and strong selective corrosion of crystal orientation, and can effectively avoid the collapse of the textured surface or metal contamination caused by excessive corrosion.

[0074] In some embodiments, in step S5, there is no particular limitation on the texturing additive used for texturing, as long as it can form a textured surface structure with the alkaline solution on the silicon wafer surface. Commonly used texturing additives include surfactants (such as isopropyl alcohol, ethanol), corrosion inhibitors (such as sodium silicate, sodium gluconate), complexing agents (such as EDTA), and pH regulators (such as acetic acid).

[0075] In some embodiments, the mass ratio of the alkali in the alkaline solution to the texturing additive is 1:2 - 5:1, such as 1:2, 1:1, 2:1, 3:1, 4:1, 5:1 or within the range of any two of the above ratios. The mass ratio of the alkali to the texturing additive affects the chemical activity and reaction selectivity of the texturing solution, and the above appropriate ratio can balance the corrosion rate and the uniformity of the textured surface, forming a more uniform textured surface.

[0076] In some embodiments, the temperature of texturing is 65°C - 85°C, such as 65°C, 66°C, 67°C, 68°C, 69°C, 70°C, 71°C, 72°C, 73°C, 74°C, 75°C, 76°C, 77°C, 78°C, 79°C, 80°C, 81°C, 82°C, 83°C, 84°C, 85°C or within the range of any two of the above values. Temperature is a key parameter for controlling reaction kinetics and textured surface morphology. Within the above temperature range, the corrosion rate of the alkali on silicon and the directional regulation effect of the additive reach a balance, which is beneficial to the uniform formation of the textured surface.

[0077] In some embodiments, the texturing time is 600s - 900s, such as 600s, 700s, 800s, 900s, or within the range of any two of the above values. The time parameter determines the integrity and size distribution of the textured surface. The above time range enables a more sufficient reaction, and the resulting textured surface size is within a suitable range.

[0078] Perform step S6 to pickling and remove the borosilicate glass on the front side and the phosphosilicate glass on the back side.

[0079] Perform step S7 to passivate the front side and the back side. The passivation treatment in step S7 can reduce the surface recombination rate and increase the open-circuit voltage.

[0080] In some embodiments, the reflectivity of the first textured surface after passivation is 7% - 15%, such as 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, or within the range of any two of the above values. The above low reflectivity design of the first textured surface after passivation can reduce the surface reflection loss of incident light, especially enhance the absorption of long-wavelength light, thereby improving the short-circuit current.

[0081] In some embodiments, the reflectivity of the second textured surface after passivation is 7% - 30%, such as 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, or within the range of any two of the above values. By controlling the reflectivity of the first textured surface after passivation within the above range, both the passivation contact performance and the light utilization rate are achieved, while avoiding the process instability problem caused by extreme reflectivity.

[0082] In some embodiments, the distance between two adjacent emitters after the formation of the pre-isolation region is within the range of 10μm - 1000μm, such as 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm, or within the range of any two of the above values. The design of this width range balances the isolation effect, passivation effect, light utilization rate of the pre-isolation region, and subsequent slicing alignment problem, making the component efficiency better, while meeting the requirements of different application scenarios for voltage resistance, appearance, and quality reliability.

[0083] Perform step S8 to set electrodes on the front side and the back side respectively. This electrode setting method can use screen printing or other methods to set silver paste and then cure and sinter to form electrodes.

[0084] Step S9 is executed to perform laser non-destructive cutting, and the cutting part is within or on one side of the pre-isolation area. This laser non-destructive cutting can refer to conventional laser non-destructive cutting. Since the isolation area of this application has a better isolation effect, and at the same time, since a controllable pyramid structure can be formed after the isolation area is textured, the light utilization rate of non-destructive laser scribing is higher. Compared with other structures, the power of laser non-destructive cutting can be further reduced, so that the cutting damage is more controllable.

[0085] [Embodiment]

[0086] Hereinafter, embodiments of the present application will be described. The embodiments described below are exemplary and are only used to explain the present application and should not be construed as a limitation to the present application. For those technologies or conditions not specified in the embodiments, they shall be carried out according to the technologies or conditions described in the literature in the art or according to the product specifications. For the reagents or instruments whose manufacturers are not indicated, they are all conventional products that can be obtained through commercial purchase.

[0087] Testing method: Under standard test conditions (STC: AM1.5G spectrum, light intensity of 1000 W / m², 25°C), the measurement methods and corresponding standards for each parameter are as follows: Use a steady-state IV tester to directly measure the open-circuit voltage (Voc) and short-circuit current (Isc), scan the IV curve and calculate the maximum power point, and measure and calculate the photoelectric conversion efficiency (pEFF) according to the ASTM E948 standard; Use a WCT120-SunsVoc detector to generate a Suns-Voc curve and fit it, obtain the pseudo fill factor (pFF) according to ASTM E1036, and obtain the base region diffusion current (J01) and the junction region recombination current (J02) through Suns-Voc technology analysis.

[0088] Embodiment 1 Prepare a solar cell according to the following steps: Step S1, subject an N-type silicon wafer with a resistivity of 1 Ω·cm and a thickness of 130 μm to a texturing treatment to obtain a first textured surface a, and the reflectivity of the first textured surface a is 9%; Step S2: Subsequently, load the silicon wafer into a high-temperature tube diffusion furnace, introduce boron trichloride (BCl3) to complete the boron diffusion process. At this time, a P+ emitter and borosilicate glass (BSG) are formed on the surface of the silicon wafer. Subsequently, use 40% hydrofluoric acid (HF) to etch one side of the battery to remove the BSG on the back of the battery. Then, use a 10% potassium hydroxide (KOH) solution and a polishing additive (Shichuang NI10V01) to polish the back of the battery. Since the front of the battery is protected by BSG, its morphology and structure remain unchanged. Immediately afterwards, introduce 20000 sccm of oxygen at 600 °C to thermally grow a 1-nm tunneling oxide layer, and use low-pressure chemical vapor deposition (LPCVD) to introduce silane at 620 °C to grow a 200-nm intrinsic polysilicon (i-Poly Si) layer. Subsequently, use phosphorus trichloride as a phosphorus source for phosphorus diffusion at 900 °C. After phosphorus diffusion, an n-type doped polysilicon layer and phosphosilicate glass (PSG) are formed on the surface, and a curved PSG and PBSG (phosphorus borosilicate glass) are formed on the front side; Step S3: Subsequently, at the position of the preset laser cutting area on the front side, use a green picosecond laser to perform laser etching to remove the P emitter. The laser wavelength is 532 nm, the set power is 20 W, the frequency is 1000 kHz, the spot overlap rate is 60%, and the energy density is 200 mJ / cm 2 , and set the isolation zone width to 400 μm; Step S4: Immediately afterwards, pickle with 20% hydrofluoric acid (HF) for 40 seconds to remove the deposited PSG / PBSG on the front side; Step S5: Subsequently, use a 10% sodium hydroxide (NaOH) solution (the concentration of the texturing additive (Shichuang ST10V18) in the NaOH solution is 2%) to re-texture the front side of the battery at a temperature of 68 °C for a reaction time of 900 s to obtain the second textured surface b. As Figure 1 shown, the reflectivity of the second textured surface b is 15%, the ratio of the reflectivity of the first textured surface a to the second textured surface b is 3:5, and the distance between the substrates of the first textured surface and the second textured surface is 7 μm. At this time, the back of the silicon wafer has PSG, and the P+ area on the front side is protected by BSG and is not damaged; Step S6: Finally, use a 10% HF solution to remove the BSG on the front side and the PSG on the back side; Step S7: Subsequently, deposit Al2O3 on the front side of the silicon wafer. At 250 °C, introduce trimethylaluminum and water to grow a 6-nm-thick Al2O3 layer on both the front and back sides. Immediately afterwards, in a plasma-enhanced chemical vapor deposition equipment, introduce silane and ammonia at 540 °C to complete the deposition of SiN x thin films on both the front and back sides, with a thickness of 75 nm each.

[0089] Step S8. Subsequently, the silver paste is printed on the P emitter and the n-type doped polysilicon layer region of the cell by screen printing, and after high-temperature sintering, the metallization is completed. Finally, after light injection treatment, a TOPCon cell is obtained. The schematic cross-sectional structure diagram of the TOPCon cell is as shown in Figure 1 shown. The topographic plan view and cross-sectional view of the first textured surface a and the second textured surface b of the TOPCon cell obtained by using a scanning electron microscope are as shown in Figure 5 shown in.

[0090] Example 2

[0091] The difference from Example 1 is that in step S5, the reaction time for re-texturing the front side of the cell is 550 s to obtain the second textured surface. The reflectivity of the first textured surface is measured to be 9%, the reflectivity of the second textured surface is 30%, the reflectivity ratio of the first textured surface to the second textured surface is 0.3, the substrate distance between the first textured surface and the second textured surface is 7.5 μm, and the isolation zone width is 400 μm.

[0092] Example 3

[0093] The difference from Example 1 is that in step S1, the N-type silicon wafer is textured to obtain the first textured surface with a reflectivity of 15%. In step S5, the concentration of the texturing additive in the 10% NaOH solution is 3.33%, and the reaction time for re-texturing the front side of the cell is 900 s to obtain the second textured surface. The reflectivity of the second textured surface is measured to be 8%, the reflectivity ratio of the first textured surface to the second textured surface is 1.875, the substrate distance between the first textured surface and the second textured surface is 7.4 μm, and the isolation zone width is 400 μm.

[0094] Comparative Example 1 The difference from Example 1 is that in step S5, the reaction time for re-texturing the front side of the cell is 400 s to obtain the second textured surface b. The reflectivity of the first textured surface a is measured to be 8.8%, the reflectivity of the second textured surface b is 50%, the reflectivity ratio of the first textured surface a to the second textured surface b is 0.176, the substrate distance between the first textured surface and the second textured surface is 4.3 μm, and the isolation zone width is 400 μm. The schematic cross-sectional structure diagram of the obtained TOPCon cell is as shown in Figure 3 shown. The topographic plan view and cross-sectional view of the first textured surface a and the second textured surface b of the TOPCon cell obtained by using a scanning electron microscope are as shown in Figure 6 shown in.

[0095] Comparative Example 2 The difference from Example 1 is that there is no re-texturing step in S5. The reflectivity of the first textured surface a is measured to be 9%, the reflectivity of the surface of the isolation region is 60%, the ratio of the reflectivity of the first textured surface a to the surface of the isolation region is 0.15, the substrate distance between the first textured surface and the surface of the isolation region is 3 μm, and the width of the isolation region is 380 μm.

[0096] Comparative Example 3 The difference from Example 1 is that in step S3, nanosecond laser etching with a wavelength of 520 nm is used to remove the P emitter, the spot overlap rate is set to 50%, and the energy density is 10 J / cm 2 , the pulse width is 10 ns. The reflectivity of the first textured surface is measured to be 10%, the reflectivity of the second textured surface is 20%, the ratio of the reflectivity of the first textured surface to the second textured surface is 0.5, the substrate distance between the first textured surface and the second textured surface is 11.5 μm, and the width of the isolation region is 600 μm.

[0097] Comparative Example 4 The difference from Example 1 is that in step S5, the reaction time for re-texturing the front surface of the battery is 1200 s to obtain the second textured surface. The reflectivity of the first textured surface is measured to be 9%, the reflectivity of the second textured surface is 2.8%, the ratio of the reflectivity of the first textured surface to the second textured surface b is 3.21, the substrate distance between the first textured surface and the second textured surface is 11 μm, and the width of the isolation region is 700 μm.

[0098] Measure the pEFF, Voc, Isc, pFF, J01, and J02 parameters of the TOPCon batteries obtained in the above Example 1 and Comparative Examples 1-4 and record them in Table 1 below.

[0099] Table 1

[0100]

[0101] The data in Table 1 show that Examples 1-3 all achieved relatively high pEFF, Voc, Isc, and pFF and relatively low J01 and J02, realizing a photoelectric conversion efficiency greater than 26.2% and excellent performance. In Comparative Example 1, due to the short texturing time, Figure 6The photos in [reference] also show that there is almost no texturing, resulting in a relatively high reflectivity, which in turn leads to an increase in the defect recombination of J02, causing a decrease in the overall photoelectric conversion efficiency. When there is no texturing in Comparative Example 2, the Isc is significantly low, indicating that the decrease in the carrier collection efficiency limits the current output, resulting in a decrease in the photoelectric conversion efficiency. In Comparative Example 3, when using a nanosecond laser with a relatively low peak power, J02 surges and J01 also increases significantly under this condition, indicating that the possibly remaining P-type emitter deteriorates the recombination mechanisms in both the diffusion layer and the space charge region, thereby significantly reducing the photoelectric conversion efficiency. When the texturing time is too long in Comparative Example 4, both J01 and J02 increase, indicating that it may cause over-corrosion on the surface of the isolation region, thereby exacerbating carrier recombination, while weakening the light absorption and carrier separation efficiency, resulting in a decrease in the photoelectric conversion efficiency.

[0102] The following examines the effects of laser power and energy density on the performance of solar cells.

[0103] Example 4 The difference from Example 1 lies in that in step S3, the laser power is set to 30 W. The reflectivity of the first textured surface is measured to be 8.9%, the reflectivity of the second textured surface is 16%, the reflectivity ratio of the first textured surface to the second textured surface is 0.5563, the substrate distance between the first textured surface and the second textured surface is 6.8 μm, and the isolation region width is 395 μm.

[0104] Example 5 The difference from Example 1 lies in that in step S3, the laser energy density is set to 280 mJ / cm 2 ². The reflectivity of the first textured surface is measured to be 9.1%, the reflectivity of the second textured surface is 15.3%, the reflectivity ratio of the first textured surface to the second textured surface is 0.5948, the substrate distance between the first textured surface and the second textured surface is 7.5 μm, and the isolation region width is 420 μm.

[0105] Measure the pEFF, Voc, Isc, pFF, J01, and J02 parameters of the TOPCon cells obtained in the above Examples 4 and 5, and record them in Table 2 below.

[0106] Table 2

[0107] The data in Table 2 show that the TOPCon cells prepared under the above conditions all have a relatively high level of photoelectric conversion efficiency (pEFF > 26%), and the performance results of each group are close, indicating good process stability.

[0108] The following examines the effects of the pickling conditions in step S4 on the performance of solar cells.

[0109] Example 6 The difference from Example 1 lies in that in step S4, pickling is carried out with 5% HF acid for 70 seconds. The reflectivity of the first textured surface is measured to be 8.7%, the reflectivity of the second textured surface is 14.9%, the reflectivity ratio of the first textured surface to the second textured surface is 0.5839, the substrate distance between the first textured surface and the second textured surface is 6.8 μm, and the isolation zone width is 405 μm.

[0110] Example 7 The difference from Example 1 lies in that in step S4, pickling is carried out with 30% HF acid for 10 seconds. The reflectivity of the first textured surface is measured to be 9.4%, the reflectivity of the second textured surface is 15.1%, the reflectivity ratio of the first textured surface to the second textured surface is 0.6225, the substrate distance between the first textured surface and the second textured surface is 6.9 μm, and the isolation zone width is 408 μm.

[0111] Measure the pEFF, Voc, Isc, pFF, J01, and J02 parameters of the TOPCon cells obtained in Examples 6 and 7 above and record them in Table 3 below.

[0112] The data in Table 3 show that the performance data of each group of TOPCon cells prepared under the above HF acid conditions are close, and all can achieve a high photoelectric conversion efficiency.

[0113] Table 3

[0114] Next, investigate the influence of the re-texturing conditions in step S5 on the performance of the solar cell.

[0115] Example 8 The difference from Example 1 lies in that in step S5, the reaction time for re-texturing the front side of the cell is 600 s to obtain the second textured surface. The reflectivity of the first textured surface is measured to be 9%, the reflectivity of the second textured surface is 21%, the reflectivity ratio of the first textured surface to the second textured surface is 3:7, and the substrate distance between the first textured surface and the second textured surface is 5.8 μm. The schematic cross-sectional structure diagram of the obtained TOPCon cell is as Figure 4 shown. Use a scanning electron microscope to take the morphology plan view and cross-sectional view of the first textured surface a and the second textured surface b of the obtained TOPCon cell, as Figure 7 shown in.

[0116] Example 9 The difference from Example 1 lies in that in step S5, in a 10% NaOH solution, the concentration of the texturing additive is 20%. The reflectivity of the first textured surface is measured to be 9.2%, the reflectivity of the second textured surface is 17%, the reflectivity ratio of the first textured surface to the second textured surface is 0.5412, the substrate distance between the first textured surface and the second textured surface is 7.6 μm, and the isolation zone width is 410 μm.

[0117] Example 10 The difference from Example 1 lies in that in step S5, the temperature for secondary texturing is 65°C. The reflectivity of the first textured surface is measured to be 9.5%, the reflectivity of the second textured surface is 16.5%, the ratio of the reflectivity of the first textured surface to that of the second textured surface is 0.5758, the substrate distance between the first textured surface and the second textured surface is 6.3 μm, and the width of the isolation zone is 395 μm.

[0118] Example 11 The difference from Example 1 lies in that in step S5, the temperature for secondary texturing is 85°C. The reflectivity of the first textured surface is measured to be 8.7%, the reflectivity of the second textured surface is 14.8%, the ratio of the reflectivity of the first textured surface to that of the second textured surface is 0.5878, the substrate distance between the first textured surface and the second textured surface is 7.1 μm, and the width of the isolation zone is 410 μm.

[0119] Measure the parameters of pEFF, Voc, Isc, pFF, J01, and J02 of the TOPCon cells obtained in Examples 8 - 11 above and record them in Table 4 below.

[0120] Table 4

[0121] The data in Table 4 show that the TOPCon cells prepared under the above conditions all have a relatively high level of photoelectric conversion efficiency. As can be seen from a comparison between Example 8 and Example 1, when the texturing time is shorter, the texturing of the second textured surface is reduced, resulting in an increase in the reflectivity of the second textured surface and a decrease in the number of effective photo-generated carriers, thus causing a slight decrease in the photoelectric conversion efficiency; the performance data of Examples 9 - 11 are close to those of Example 1, and all can achieve a relatively high photoelectric conversion efficiency.

[0122] Although the specific embodiments of the present invention have been described in detail, those skilled in the art will understand that various modifications and substitutions can be made to those details based on all the teachings that have been disclosed, and these changes are all within the protection scope of the present invention. The full scope of the present invention is given by the appended claims and any equivalents thereof.

Claims

1. A solar cell, comprising a silicon substrate, wherein the front side of the silicon substrate has a velvet structure, the front side of the silicon substrate is divided into a working area and an edge isolation area, the working area comprises a p-type emitter, a first passivation layer and a first electrode arranged on the front side in sequence from the inside to the outside, the edge isolation area comprises a first passivation layer arranged on the front side, and the back side of the silicon substrate comprises a tunneling oxide layer, an n-type doped polysilicon layer, a second passivation layer and a second electrode arranged in sequence from the inside to the outside, wherein: The reflectivity of the suede structure in the working area is R1, the reflectivity of the suede structure in the edge isolation area is R2, R1 / R2 is in the range of 0.3-3, and The distance between the velvet structure base in the working area and the velvet structure base in the edge isolation area is in the range of 3 μm-10 μm.

2. The solar cell according to claim 1, wherein: The reflectivity R1 is 7%-15%; and / or the reflectivity R2 is 7%-30%.

3. The solar cell according to claim 1 or 2, wherein: A minimum dimension of the edge isolation region in a direction away from the working region is in a range of 10 μm to 1000 μm.

4. The solar cell according to claim 1 or 2, wherein: The edge isolation area is a rectangular area.

5. The solar cell according to claim 1 or 2, wherein: The silicon substrate is an N-type silicon substrate.

6. The solar cell according to claim 1 or 2, wherein: The silicon substrate is a single crystal silicon wafer doped with phosphorus atoms.

7. The solar cell according to claim 1 or 2, wherein: The resistivity of the silicon substrate is 0.1 Ω·cm-100 Ω·cm; and / or the thickness of the silicon substrate is 100 μm-500 μm.

8. The solar cell according to claim 1 or 2, wherein: The doping concentration of the p-type emitter is 2×10 18 atoms / cm 3 - 1×10 19 atoms / cm 3 ; and / or the junction depth of the p-type emitter is 0.5μm-2μm.

9. The solar cell according to claim 1 or 2, wherein: The tunnel oxide layer includes one or more of silicon oxide, silicon nitride, and aluminum oxide, and / or the thickness of the tunnel oxide layer is 0.5 nm-2.5 nm.

10. The solar cell according to claim 1 or 2, wherein: The thickness of the n-type doped polysilicon layer is 100nm-300nm; and / or The doping concentration of the n-type doped polysilicon layer is 3×10 20 atoms / cm 3 - 1×10 21 atoms / cm 3 .

11. The solar cell according to claim 1 or 2, wherein: The first passivation layer and the second passivation layer each independently include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride or silicon oxynitride.

12. The solar cell according to claim 1 or 2, wherein: The first electrode and the second electrode each independently include at least one of silver, silver alloy, copper, copper alloy, and nickel / copper / silver multilayer electrode.

13. A method for preparing a solar cell, comprising the following steps: S1, texturing the front surface of the silicon substrate to obtain a first textured surface; S2, preparing a p-type emitter on the front side of the textured silicon substrate, and sequentially preparing a tunneling oxide layer and an n-type doped polysilicon layer on the back side of the silicon substrate; S3, using a green picosecond laser to remove the p-type emitter at a preset position to form a pre-isolation region; S4, acid washing to remove the winding phosphosilicate glass and winding phosphosilicate borosilicate glass on the front side; S5, re-texturing the front surface using an alkali solution including a texturing additive, so that the pre-isolation area forms a second velvet surface; S6, removing the borosilicate glass on the front side and the phosphosilicate glass on the back side by pickling; S7, passivating the front side and the back side; S8. Electrodes are provided on the front and back sides respectively; S9, performing laser non-destructive cutting, wherein the cutting position is within the pre-isolation area or on one side of the pre-isolation area, The reflectivity of the first velvet surface is R1, and the reflectivity of the second velvet surface is R2. R1 / R2 is in the range of 0.3-3. The distance between the first suede base and the second suede base is in the range of 3 μm-10 μm.

14. The preparation method according to claim 13, wherein: The green picosecond laser meets one or more of the following conditions: 1) The wavelength of the green picosecond laser is 532nm or 1064nm; 2) The radiation power of the green picosecond laser is 1W-50W; 3) The spot overlap rate of the green picosecond laser is 40%-80%; or 4) The energy density of the green picosecond laser is 100 mJ / cm 2 -400mJ / cm 2 .

15. The preparation method according to claim 13 or 14, wherein: The reflectivity of the first suede surface is 7%-15%, and / or the reflectivity of the second suede surface is 7%-30%.

16. The preparation method according to claim 13 or 14, wherein: After the pre-isolation region is formed, the distance between two adjacent emitters is in the range of 10 μm-1000 μm.

17. The preparation method according to claim 13 or 14, wherein: In step S4, the acid solution used for pickling is an HF solution with a concentration of 5%-30%, and the pickling time is 10s-70s.

18. The preparation method according to claim 13 or 14, wherein: The conditions of step S5 meet one or more of the following conditions: 1) The mass ratio of the alkali in the alkali solution to the texturing additive is 1:2-5:1; 2) The temperature of the velveting is 65°C-85°C; 3) The time of the texturing is 600s-900s.

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