Method and apparatus for controlling radiated spurious emissions in RF antenna switch

Abstract

Methods and apparatus for controlling radiated spurious emission (RSE) in an RF antenna switch are presented. The RF antenna switch includes: a through stack including at least one conventional N-type FET transistor and a plurality of intrinsic N-type FET transistors; and a shunt stack including a plurality of intrinsic N-type FET transistors. During the inactive mode of operation, the conventional transistor is turned off to exhibit a high impedance. The RF antenna switch includes a termination stack having a plurality of conventional P-type FET transistors that are activated during an inactive mode to present a termination impedance to the antenna. The bias signal generator remains partially active during the inactive mode of operation to generate a positive control voltage and a negative control voltage having an amplitude sufficiently high to maintain on / off control of transistors in the stack.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of co - pending U.S. Provisional Patent Application Serial No. 63 / 378,016, entitled "Methods and Devices to Control Radiated Spurious Emission in RF Antenna Switches", filed on September 30, 2022, the disclosure of which is incorporated herein by reference in its entirety. Field of the Invention

[0003] This disclosure relates to radio frequency (RF) switches and, more particularly, to methods and devices for controlling radiated spurious emissions (RSE) in RF antenna switches including FET switch stacks. Background Art

[0004] Figure 1 A simplified portion of two RF front - end systems (100, 200) in close proximity to each other is shown. Each such system can be configured to transmit and / or receive RF signals via a respective antenna (160, 260). Transmitting or receiving an RF signal can be selectively coupled via a respective antenna switch (150, 250) through a specific plurality of RF processing paths, as Figure 1 shown, the antenna switches (150, 250) being coupled to the antennas (160, 260) at respective common ports (AP, e.g., poles) of the antenna switches (150, 250). Under the control of respective control signals (CTL1, CTL2), a plurality of throws (S1, S2, …, Sk) of the respective antenna switches (150, 250) can sequentially couple the transmitted or received RF signal to the plurality of RF processing paths, which can be defined, for example, by respective filters (141, 142, …, 14k, e.g., part of a duplexer). Each RF front - end system (100, 200) can include a signal - sensing main processing unit (120, 220, e.g., transceiver), which can be configured to further process and / or control (e.g., via CTL1, CLT2) the RF signals flowing through the RF front - end systems (100, 200). It should be noted that the two RF front - end systems (100, 200) can be part of the same communication device (e.g., a handheld device, a cellular phone) or part of different communication devices.

[0005] Devices such as RF front - end systems (100, 200) can be designed to reduce interference to surrounding communication devices or systems by reducing / minimizing spurious RF emissions when active (e.g., transmitting and / or receiving) or inactive (e.g., not transmitting and not receiving). Some communication standards may even require system manufacturers and integrators to follow specifications aimed at reducing interference, including, for example, interference related to radiated spurious emissions (RSE).

[0006] The radiated spurious emissions (RSE) of the RF front - end system (100) are schematically and simply shown in Figure 1 as the RF signal RF that is transmitted (e.g., radiated) through the antenna (160) in response to the RF signal RF2 generated by the RF front - end (200). 12 . When the RF signal RF2 is generated by the RF front - end (200) and transmitted through the antenna (260), the antenna (160) of the RF front - end (100) can receive the attenuation amount of the RF signal RF2 based on the relative proximity of the two antennas (160, 260). Further, the RF signal RF2 received through the antenna (160) can be coupled to the common port AP of the antenna switch (150) and subjected to the internal impedance presented by various conduction paths inside the antenna switch (150). Further, the mismatch between such internal impedances and / or the mismatch between such internal impedance and the impedance of the conduction path between the antenna (160) and the common port AP may cause reflection of the received RF signal RF2, which can combine to generate the RF signal RF that is transmitted / radiated through the antenna (160). 12 The RF signal RF 12 can include harmonics, inter - modulation products, and / or frequency - conversion products of the RF signal RF2 generated by the RF front - end system (200).

[0007] Although the antenna switch (150) can be designed to sufficiently reduce / minimize RSE during the active operation mode of the RF front - end system (100), where the internal impedance of the antenna switch (150) is known, during the inactive operation mode of the RF front - end system (100), the internal impedance of the antenna switch (150) may be unknown and thus result in elevated RSE above the desired minimum level. The motivation of this teaching is to control and maintain RSE within the desired minimum level during both the active and inactive operation modes of the RF front - end communication system. SUMMARY OF THE INVENTION

[0008] According to a first aspect of the present disclosure, a radio frequency (RF) antenna switch is provided, including: a first switching element coupled between a common port of the RF antenna switch and a first throw of the RF antenna switch, the first switching element including: a through-stack including a plurality of N-type FET transistors arranged in series connection, the through-stack being coupled between the common port and the first throw; and a shunt-stack including a plurality of N-type FET transistors arranged in series connection, the shunt-stack being coupled between the first throw and a reference ground, and a bias signal generation circuit including at least one charge pump, the bias signal generator being configured to generate a positive bias voltage and a negative bias voltage based on a positive power supply voltage, wherein the RF antenna switch is configured to operate according to an active mode and an inactive mode, the inactive mode defining a low power consumption mode of the RF antenna switch, a control voltage applied to the first switching element during the active mode includes a positive voltage and a negative voltage having respective amplitudes of the positive bias voltage and the negative bias voltage, a control voltage applied to the first switching element during the inactive mode includes a positive voltage and a negative voltage having respective amplitudes greater than zero and less than the respective amplitudes of the positive bias voltage and the negative bias voltage, and at least one charge pump is inactive during the inactive mode.

[0009] According to a second aspect of the present disclosure, a radio frequency (RF) antenna switch is provided, including: a first switching element coupled between a common port of the RF antenna switch and a first throw of the RF antenna switch, the first switching element including: a through-stack including a plurality of intrinsic N-type FET transistors and at least one conventional N-type FET transistor arranged in series connection, the through-stack being coupled between the common port and the first throw; and a shunt-stack including a plurality of intrinsic N-type FET transistors arranged in series connection, the shunt-stack being coupled between the first throw and a reference ground.

[0010] According to a third aspect of the present disclosure, a radio frequency (RF) antenna switch is provided, including: a first switching element coupled between a common port of the RF antenna switch and a first throw of the RF antenna switch, the first switching element including: a through-stack including a plurality of intrinsic N-type FET transistors arranged in series connection, the through-stack being coupled between the common port and the first throw, and a shunt-stack including a plurality of intrinsic N-type FET transistors arranged in series connection, the shunt-stack being coupled between the first throw and a reference ground, and a terminal stack including a plurality of conventional P-type FET transistors arranged in series connection, the terminal stack being coupled between the common port and a reference ground.

[0011] Additional aspects of the present disclosure are provided in the description, drawings, and claims of this application. Description of the Drawings

[0012] The accompanying drawings incorporated herein and constituting a part of this specification illustrate one or more embodiments of the present disclosure and, together with the description of the exemplary embodiments, are used to explain the principles and implementations of the present disclosure.

[0013] Figure 1 A simplified portion of two RF front-end systems shown in close proximity to each other is presented.

[0014] Figure 2A Shows what can be used in Figure 1 Details of an example RF antenna switch that can be used in each of the two RF fronts are presented.

[0015] Figure 2B Shows what represents Figure 2A A timing diagram of the control signals and states of the internal switch of the RF antenna switch during active and inactive operating modes is presented.

[0016] Figure 3A Details of the through-stack of the switching elements of the RF antenna switch according to an embodiment of the present disclosure are presented.

[0017] Figure 3B Shows what represents including Figure 3A A timing diagram of the control signals and states of the internal switch of the RF antenna switch including the through-stack during active and inactive operating modes is presented.

[0018] Figure 4A Details of the terminal stack of the RF antenna switch according to an embodiment of the present disclosure are presented.

[0019] Figure 4B Shows what represents Figure 4A A timing diagram of the control signals and states of the terminal stack during active and inactive operating modes is presented.

[0020] Figure 5A A block diagram of a bias signal generator circuit is presented.

[0021] Figure 5B Shows Figure 5A More details of the block diagram are presented.

[0022] Figure 5C A block diagram of a bias signal generator circuit according to an embodiment of the present disclosure is presented.

[0023] Figure 5D A block diagram of a bias signal generator circuit according to another embodiment of the present disclosure is presented.

[0024] Figure 5E A block diagram of a bias signal generator circuit according to yet another embodiment of the present disclosure is presented.

[0025] Figure 5F shows an alternative implementation of a bias signal generator circuit. Figure 5E

[0026] Figure 5G shows a timing diagram of control signals and states during active and inactive operating modes of an internal switch of an antenna switch according to the present disclosure, Figure 2A wherein the internal switch is based on a bias signal provided by a bias signal generator.

[0027] Like reference numerals and names in the various figures indicate like elements. DETAILED DESCRIPTION

[0028] As used herein, the terms "active", "active state", "active mode", and "active operating mode" are synonymous and refer to an operating mode that enables all functions of a circuit or system such as an RF communication / front-end system and / or one or more elements in the RF communication / front-end system, such as an RF antenna switch. The goal of the active state may be to reduce any delay in signal processing / generation at the cost of relatively high power consumption. Thus, and by way of example, when Figure 1 the RF antenna switch (e.g., 150) of the RF front-end system (100) is active, then all (internal) elements of the RF antenna switch (150) and the corresponding driver / circuit that controls (e.g., generates the CTL1 signal) the RF antenna switch (150) are active and ready to transmit and / or receive RF signals through the RF antenna (160) with minimal delay.

[0029] As used herein, the terms "inactive", "inactive state", "inactive mode", "inactive operating mode", "standby", "standby state", "standby mode", "low power mode", and "standby operating mode" are synonymous and refer to an operating mode that disables all functions of a circuit or system such as an RF communication / front-end system and / or one or more elements in the RF communication / front-end system, such as an RF antenna switch. The goal of the inactive state may be to reduce power consumption at the cost of a delay in signal processing / generation when transitioning to the active mode. Thus, and by way of example, when Figure 1 the RF antenna switch (e.g., 150) of the RF front-end system (100) is inactive or in standby, then the corresponding driver / circuit that controls (e.g., generates CTL1) the antenna switch (150) may be inactive to achieve low power consumption.

[0030] ​Reducing power consumption can be considered the top priority for battery-powered handheld devices, and thus more system manufacturers and integrators may implement an inactive operating mode in their devices. Therefore, the inactive operating mode can be regarded as a low-power mode (LPM), which can be defined by strict requirements on the current consumption in the system and / or one or more components in the system. For the case of RF antenna switches (e.g., 150, 250 in Figure 1 ), the current consumption in the inactive state can be limited to as low as 5 microamps. To achieve such low current consumption, a typical design may disable the operation of the driver circuit that generates the control signal / voltage for controlling the operation of the RF antenna switch (e.g., the bias signal generator in Figures 5A to 5F described later). By doing so, the level of the control signal / voltage to the RF antenna switch (e.g., CTL1, CTL2 in Figure 1 ) may eventually reach zero volts, which in turn causes the internal devices of the RF antenna switch (e.g., the transistors, FETs shown in Figure 2A ) to stabilize to a state with impedances that, when combined, result in the increased RSE described above.

[0031] Figure 2A shows the details of an example RF antenna switch element SW of an RF antenna switch that can be used for an RF antenna switch such as Figure 1 . As shown on the left side of Figure 2A , the implementation of the RF antenna switch (e.g., 150, 250) can be provided by a plurality of single-pole single-throw switches (e.g., switch elements SW1, SW2,..., SW k ), which have corresponding poles connected / coupled to the common port AP of the RF antenna switch and corresponding throws connected / coupled to the plurality of throws (S1, S2,..., Sk) of the RF antenna switch. On the right side of Figure 2A , the details of the switch element SW that can be used to implement each of the switches (SW1, SW2,..., SW k ) including the switch SW1 are shown.

[0032] As shown in Figure 2A , the example switch element SW can include: a through-stack TS that is coupled between the common port AP of the RF antenna switch (e.g., 150, 250) and a corresponding throw (e.g., S1); and a shunt-stack SS that is coupled between the corresponding throw (e.g., S1) of the RF antenna switch (e.g., 150, 250) and the reference ground. The through-stack TS can include a plurality (e.g., n) of series-connected FET transistors (M T1 , M T2 ,..., MTn ), whose gates are coupled to the (through-stack) control signal V via respective multiple gate resistors (R T1 , R T2 , …, R Tn ), and each such gate resistor is connected in series with the corresponding transistor gate. Similarly, the shunt stack SS may include multiple (e.g., p) series-connected FET transistors (M CTL_TS ), whose gates are coupled to the (shunt-stack) control signal V via respective multiple gate resistors (R S1 , M S2 , …, M Sp ), and each such gate resistor is connected in series with the corresponding transistor gate. The on and off states of the switching element SW may be based on the on and off states of the through-stack TS and the shunt stack SS. It should be noted that other topologies of the switching element for the RF antenna switch may be implemented by including one or more additional through-stacks TS or shunt stacks SS (e.g., SS-TS-SS, etc.). The teachings according to the present disclosure may equally apply to such topologies. S1 , R S2 , …, R Sp ), and each such gate resistor is connected in series with the corresponding transistor gate. The on and off states of the switching element SW may be based on the on and off states of the through-stack TS and the shunt stack SS. It should be noted that other topologies of the switching element for the RF antenna switch may be implemented by including one or more additional through-stacks TS or shunt stacks SS (e.g., SS-TS-SS, etc.). The teachings according to the present disclosure may equally apply to such topologies. CTL_SS , and each such gate resistor is connected in series with the corresponding transistor gate. The on and off states of the switching element SW may be based on the on and off states of the through-stack TS and the shunt stack SS. It should be noted that other topologies of the switching element for the RF antenna switch may be implemented by including one or more additional through-stacks TS or shunt stacks SS (e.g., SS-TS-SS, etc.). The teachings according to the present disclosure may equally apply to such topologies.

[0033] Continuing to refer to Figure 2A , each of the stacks TS and SS should be able to withstand a high voltage corresponding to the highest expected (RF) voltage processed by the antenna switch (and thus by the switching element SW). Accordingly, the numbers n and p of the corresponding series-connected FET transistors (M T1 , M T2 , …, M Tn ) and (M S1 , M S2 , …, M Sp ) may be based on the high voltage and the corresponding breakdown voltage capabilities of each FET transistor (e.g., the high voltage is distributed / divided among the multiple FET transistors). Since the same type (and size) of FET transistors may be used in a typical switch design, and since both the stacks TS and SS can withstand the same high voltage (e.g., during their off states), in some non-limiting implementations, the number n may be equal to the number p.

[0034] Also referring to Figure 2A , during the active operating mode of the RF antenna switch (e.g., 150, 250), for Figure 2AThe switching element SW transitions to an on state (i.e., a low-impedance state, an on state), the stack TS is turned on, and the stack SS is turned off; and to transition the switching element SW to an off state (i.e., a high-impedance state, an isolation state), the stack TS is turned off, and the stack SS is turned on. The states of the stacks TS and SS are provided by the states of the corresponding FET transistors (M TI 、M T2 、…、M Tn ) and (M S1 、M S2 、…、M Sp ), and these transistors are in turn controlled by the corresponding control signals V CTL_TS and V CTL_SS . During the active operating mode, the voltage levels of the control signals V CTL_TS and V CTL_SS are generated (actively and deterministically) by the corresponding circuits (e.g., the bias signal generator of Figure 5A described later) to known levels, and the known levels control each of the FET transistors M T1 、M T2 、…、M Tn 、M S1 、M S2 、…、M Sp to operate in known and desired states (e.g., on or off, conducting or isolated, low impedance or high impedance, etc.). For example, assuming that all the FET transistors of the stacks TS and SS are N-type FET transistors, to turn on such transistors, the control signals V CTL_TS and V CTL_SS can apply a voltage level greater than the threshold voltage V TH of the transistor to the corresponding gates of the transistor, and to turn off such transistors, the control signals V CTL_TS and V CTL_SS can apply a voltage level less than the threshold voltage V TH of the transistor to the corresponding gates of the transistor.

[0035] In some RF antenna switch designs, the FET transistors (e.g., FET transistor switches) used in the switching element SW of Figure 2A are N-type FET transistors. One reason for this choice of transistor type can be attributed to the fact that the electron mobility in N-type doped silicon (where electrons are the majority carriers) is substantially higher (e.g., three times or more higher) than the hole mobility in P-type silicon (where holes are the majority carriers), and this can actually allow for a lower on-resistance (R ON ) for a given transistor size (e.g., the width-to-length ratio of the transistor). In other words, such as Figure 2AThe RF switch element of the switching element SW can be constructed with an N-type FET transistor of a smaller size, and the N-type FET transistor consumes less power and occupies a small die area while providing a sufficiently low R ON (and a sufficiently small off-capacitance).

[0036] The threshold voltage V of the FET transistor TH can be considered to represent the gate-to-source voltage, and the threshold voltage V TH when applied to the FET transistor, makes the transistor lie at the boundary between conducting (e.g., on state, saturation operating region) and non-conducting (e.g., off state, isolation, triode operating region). The typical value of the V TH voltage of a (conventional) FET transistor (e.g., NMOS FET) can be about (positive) 500 millivolts, or in the range from (positive) 450 millivolts to (positive) 650 millivolts (inverted / negative for PMOSFET). Additionally, the farther the FET transistor operates in its saturation region, the lower the R ON of the FET transistor, which is beneficial when used as an RF transistor switch. In other words, for the case of an N-type FET transistor, it can be expected to control the on state of the FET transistor with a gate voltage significantly greater than the threshold voltage V TH of the transistor. Similarly, to reduce the current leakage in the off state of the FET transistor, it can be expected to control the off state of the FET transistor with a gate voltage significantly smaller (including negative values) than the threshold voltage V TH of the transistor.

[0037] When reconciling the above characteristics of a (conventional) N-type FET transistor used as an RF switch with the desire to operate / control the RF switch with a low (control) voltage, in some RF antenna switch designs, an intrinsic N-type FET transistor is used. As used in this disclosure, a "conventional" FET transistor is a FET transistor having a (strictly) positive threshold voltage V TH in the range from (positive) 450 millivolts to (positive) 650 millivolts. As used in this disclosure, an "intrinsic" FET transistor is a FET transistor having a negative or zero threshold voltage V TH in the range from (negative) 150 millivolts to about zero volts. Thus, for a gate-to-source voltage of about zero volts, a conventional N-type FET transistor operates well in its triode operating region and is thus off (e.g., non-conducting, isolated). On the other hand, for a gate-to-source voltage of about zero volts, an intrinsic N-type FET transistor operates near its saturation operating region and can be considered (partially) conducting or partially on, and thus exhibits a relatively low R ON .

[0038] Return reference Figure 2A , and in view of the above description of the conventional transistor and the intrinsic transistor, in some preferred RF antenna switch designs, the switching element SW may only include an intrinsic N-type FET transistor. In other words, the corresponding FET transistors (M T1 , M T2 , …, M Tn ) and (M S1 , M S2 , …, M Sp ) of the stacked TS and SS are intrinsic N-type FET transistors, and thus as shown in Figure 2B , they can be turned on and off with gate voltages (e.g., V CTL_TS or V CTL_SS ) that are respectively (substantially) greater than zero volts and (substantially) less than zero volts.

[0039] Figure 2B Shows the control signals (e.g., V Figure 2A ) and states (e.g., SW CTL_TS or V CTL_SS ) of the internal switch (e.g., the switching element SW) of the antenna switch representing ON , SW OFF , SW INACT ) during the active and inactive operating modes. As shown in Figure 2B , during the active operating mode, the on-state SW ON of the switching element SW is provided by the on-state TS ON of the through-stack TS and the off-state SS OFF of the shunt-stack SS. On the other hand, during the active operating mode, the off-state SW OFF of the switching element SW is provided by the off-state TS OFF of the through-stack TS and the on-state SS ON of the shunt-stack SS. As described above, during the active operating mode, the on and off control of the through-stack TS and the shunt-stack SS is provided by the corresponding high voltage levels (e.g., V CTL_TS ) and low voltage levels (e.g., V CTL_SS ) of the corresponding control signals V POS and V NEG . Since such control signals are effectively applied to the corresponding gates of the intrinsic N-type FET transistors (M T1 , M T2 , …, M Tn ) and (M S1 , M S2 , …, M Sp ), the states TS ON and TSOFF can respectively represent the on and off states of each of a plurality of transistors (M T1 , M T2 , …, M Tn ). Similarly, the states SS ON and SS OFF of the stack SS can respectively represent the on and off states of each of a plurality of transistors (M S1 , M S2 , …, M Sp ). It should be noted that in some implementations, each transistor in the same stack can receive the same control signal and thus receive the same voltage level. However, in some implementations, to further optimize the on / off characteristics of the transistors in the same stack, each transistor in the same stack can receive different / corresponding control signals with appropriate / corresponding voltage levels. In both implementations, the voltage level of each transistor in the stack can be represented by the timing diagram (200B) of Figure 2B .

[0040] Continuing to refer to Figure 2B , the (stable) voltage level V CTL_TS or V CTL_SS generated for use by the control signal (e.g., V POS ) during the active operation mode can be in the range from about 1.5 volts to about 5 volts, such as, for example, in the range from 3.2 volts to 4.2 volts. On the other hand, the (stable) voltage level V CTL_TS or V CTL_SS generated for use by the control signal (e.g., V NEG ) during the active operation mode can be in the range from about -1.5 volts to about -5 volts, such as, for example, in the range from -3.2 volts to -4.2 volts. In some applications, and as described later with reference to Figure 5A , such voltage levels can be generated from an available low supply voltage (e.g., a battery) by a combination of functional blocks that can include a charge pump and a voltage regulator (e.g., Figure 5B described later).

[0041] During the inactive operation mode (as shown in Figure 2B , which occurs at time t INACT ), no (active) voltage levels V POS and V NEG are generated, and thus, as shown in Figure 2B , the (floating) nodes carrying such voltages discharge to eventually reach zero volts, where the discharge response is based on other leakage paths and the intrinsic N-type FET transistors (M T1 , M T2 , …, M Tn) and (M S1 、M S2 、…、M Sp ) of the corresponding combined capacitance presented by the gates. Due to the intrinsic properties of such transistors (e.g., partially conducting for a gate-to-source voltage of zero volts), and as shown in Figure 2B , the through-stack TS and the shunt-stack SS are (and remain) conducting (e.g., partially conducting) during the inactive operating mode. In turn, the (stable) state SW of the switching element SW is defined during the inactive operating mode INACT of the TS ON and SS ON such a combination of states may result in an impedance mismatch between the stacks TS and SS, as described above, which may lead to an elevated RSE above the desired minimum level.

[0042] The above-described drawbacks of the RF antenna switch are overcome in accordance with the teachings of the present disclosure, the RF antenna switch using only intrinsic N-type FET transistors when operating in the inactive operating mode while maintaining the benefits of using such intrinsic transistors. The first solution provided by this teaching (e.g., Figure 3A ) for controlling / maintaining a sufficiently low RSE may include modifying the architecture of the switching element (e.g., the switching element SWM including the through-stack TSM of Figure 3A ) to exhibit a different impedance during the inactive operating mode in which the control signal voltage reaches zero volts. The second solution provided by this teaching (e.g., Figure 4A ) for controlling / maintaining a sufficiently low RSE, including low intermodulation products, may include adding a termination stack (e.g., Figure 4A of the SW-TR) to the RF antenna switch, the termination stack being activated during the inactive operating mode to present a known termination impedance (e.g., 50 ohms at the operating frequency) to the common port of the RF antenna switch (e.g., Figure 4A of the AP). The third solution provided by this teaching (e.g., Figures 5C to 5F ) for controlling / maintaining a sufficiently low RSE may include modifying the bias signal generation circuit to actively drive the voltage used by the control signal (e.g., V CTL_TS or V CTL_SS ) to a (non-zero but lower magnitude) level (e.g., Figures 5C to 5F of V POSM or V NEGM ), the level which, when applied to the stacks (e.g., TS, SS) of the RF antenna switch shown in Figure 2A , produces a combination of states of the stacks defined during the inactive operating mode of the RF antenna switch, and thus, by design, maintains the RSE within the desired minimum level.

[0043] The first solution and the second solution according to the present teachings may include modifications to the RF antenna switch itself without including the bias signal generating circuit (e.g., Figure 5A ) can completely disable the bias signal generation circuit during the inactive operating mode to achieve minimum current consumption. Figures 3A to 4B A first solution and a second solution according to the present teaching are described.

[0044] On the other hand, a third solution according to the present teachings may not include modifications to the RF antenna switch itself (e.g., Figure 3A / Figure 4A ), but includes modifications to the bias signal generating circuit (e.g., Figures 5C to 5F ) to deactivate (e.g., corresponding inactive state) most of its functional blocks (e.g., charge pump and voltage regulator, described later), except for the block that converts the (positive) power supply voltage (e.g., battery) into the negative power supply voltage when applicable. During the inactive operation mode of the RF antenna switch, the voltage levels generated by the positive power supply voltage and the negative power supply voltage can in turn be used to actively control / drive the transistors of the stack (e.g., TS, SS) to a known / defined state. It should be noted that such voltage levels generated by the positive power supply voltage and the negative power supply voltage may include voltages of different (e.g., lower) amplitudes than the voltages used to control the state of the RF antenna switch during the active operation mode of the RF antenna switch. It should also be noted that since the voltage levels generated by the third solution may include amplitudes substantially greater than zero (e.g., substantially greater than |Vth| of conventional and intrinsic transistors), such voltage levels may be used to control any type of transistors, including conventional and / or intrinsic transistors, to a known / defined state during the inactive operation mode of the RF antenna switch. In other words, the third solution can be considered compatible with any type of FET switch stack, whether comprising intrinsic N-type or P-type transistors, conventional N-type or P-type transistors, or a combination thereof. Figures 5A to 5G A third solution according to the present teaching is described.

[0045] Figure 3A The bottom of FIG. 1 shows details of a through-stack TSM of a switch element SWM of an RF antenna switch according to an embodiment of the present disclosure, which is Figure 3A shown at the top of and previously referenced Figure 2A In contrast, the switch element SW described above is Figure 3A As shown in FIG. 1 , in the sense of the present application, a through-stack TSM may include the same number (eg, n) of N-type FET transistors (M) connected in series. T1 、M RT2 , …, M Tn), which may include at least one conventional N-type FET transistor M RT2 , where the remaining (eg, n-1) transistors (M T1 、M RT3 , …, M Tn ) can be an intrinsic N-type FET transistor in the sense of the present application. In other words, Figure 3A As shown in FIG. , by using conventional transistors (e.g., M RT2 ) replaces at least one of the intrinsic transistors of TS (e.g., M T2 ), can be obtained from Figure 2A The straight-through stacking TS obtains the straight-through stacking TSM according to the present disclosure. Figure 2A You can find Figure 3A The missing details of the switching element SWM, including the corresponding shunt stack (e.g., Figure 2A It should be noted that at least one conventional N-type FET transistor (e.g., M RT2 ) can be arranged anywhere within the stack, and more than one such conventional N-type FET transistor can be arranged within a through-stack TSM. Such a number of conventional N-type FET transistors can be designed based on power handling in the inactive mode or required / desired RSE performance. In addition, it should be noted that Figure 3A The switch element SWM shown in FIG. 1 must be used for multiple switch elements of an RF antenna switch (e.g., Figure 2A SW1, SW2, ...SW k ). In other words, a single switching element SWM may not be sufficient to control the RSE of the RF antenna switch in the inactive operation mode, the RF antenna switch comprising the switching elements according to Figure 2A Multiple (for example, k-1) switching elements SW.

[0046] Figure 3B Shown is a representation including Figure 3A The internal switch of the through-stack TSM RF antenna switch (for example, Figure 3A SWM) control signals during active and inactive operating modes (e.g., V CTL_TS or V CTL_SS ) and status (e.g., SWM ON , SWM OFF , SW INACT ) is a timing diagram (300B). In the timing diagram (300B), the Figure 2B Similar naming as used in the timing diagram (200B) of FIG. 10 with the addition of the suffix "M" to indicate the Figure 2B The element / state described in is compared to the modified element / state.Figure 3B includes as a reference Figure 3A at least one conventional N-type FET transistor M of the through-stack TSM RT2 threshold voltage V of THr . Since during the active operating mode, the voltage levels V POS and V NEG are sufficiently far from (e.g., greater than and less than) the threshold voltages of multiple intrinsic (e.g., Figure 2B V of THi ) and conventional (e.g., V THr ) N-type FET transistors, thus similar to Figure 2B the state described in ON the on-state SWM of the switch element SWM is provided by the on-state TSM of the through-stack TSM ON and the off-state SS of the shunt stack SS OFF . On the other hand, during the active operating mode, the off-state SWM of the switch element SWM OFF is provided by the off-state TSM of the through-stack TSM OFF and the on-state SS of the shunt stack SS ON . In other words, during the active operating mode, the switch element SWM can exhibit an impedance similar to that of Figure 3A the switch element SW and thus exhibit similar (acceptable) RSE performance.

[0047] However, and as shown in Figure 3B , during the non-active operating mode, the state SWM of the switch element SWM INACT is defined by the off-state TSM of the through-stack TSM OFF* and the on-state SS of the shunt stack SS ON . It should be noted that since the state SS ON is provided / defined by the corresponding on-states of the same transistors (e.g., M S1 , M S2 , …, M Sp ), this state can be the same as that described above with reference to Figure 2A / Figure 2B (e.g., the same impedance, on characteristics), and thus it exhibits the same (low) impedance. On the other hand, since the state TSM OFF* can be provided / defined by the corresponding off-state of at least one conventional N-type FET transistor M RT2 in combination with the corresponding on-states of the remaining intrinsic N-type FET transistors (M T1 , M T3 , …, M Tn ), thus the state TSM OFF*can be considered different from state TS OFF State. When the level of the control voltage (e.g., V POS , V NEG ) reaches (stabilizes to) zero volts during the inactive operation mode, at least one conventional N-type FET transistor M of the through-stack TSM RT2 turns off, while the remaining (intrinsic) transistors of the through-stack TSM conduct. Since these transistors are connected in series, during the inactive operation mode, the combined impedance of the through-stack TSM can essentially be represented by the high impedance of the off state of at least one conventional N-type FET transistor M RT2 . The desired combined high impedance of the through-stack TSM during the off state TSM OFF* can be considered to design the size and characteristics of at least one conventional N-type FET transistor M of the through-stack TSM RT2 , and the desired combined high impedance can be high enough (e.g., at the RF operating frequency) to limit the RSE in the inactive operation mode.

[0048] Figure 4A shows details of the terminal stack (SW-TR, R TRM ) of the RF antenna switch (450) according to an embodiment of the present disclosure. As shown on the left side of Figure 4A , the RF antenna switch (450) can be based on the RF antenna switches (150, 250) described above with reference to Figure 2A , and is modified by adding a terminal stack (SW-TR, R TRM ). As shown in Figure 4A , the terminal stack (SW-TR, R TRM ) can include a plurality (e.g., m) of serially connected FET transistors (P TR1 , P TR2 , …, P TRm ), whose gates are coupled to the (terminal stack) control signal V TR1 , R TR2 , …, R TRm via corresponding multiple gate resistors (R CTL_TRM ), and each such gate resistor is connected in series with the corresponding transistor gate.

[0049] Figure 4A The terminal stack (SW-TR, R TRM ) can operate as a switch that, under the control of the control signal V CTL_TRM , selectively couples the common port AP of the RF antenna switch to ground through an impedance (e.g., resistance, terminal impedance / resistance) R TRM . When the terminal stack is conducting (e.g., conducting, on state, active, activated), the impedance seen by the common port AP is the transistor (PTR1 , P TR2 , …, P TRm ) of R ON and the termination impedance R TRM of the combination (e.g., and). According to a non - limiting embodiment of the present disclosure, when the termination stack is turned on, such an impedance seen from the common port AP can be designed as the system impedance used in an RF communication system, such as, for example, 50 ohms. In this case, the value of the termination impedance R TRM can be based on the R TR1 of transistors (P TR2 , P TRm ), …, P ON such that the combination provides the system impedance. Thus, if the transistors (P TR1 , P TR2 ), …, P TRm ) are designed to provide R ON as a product (m × R ON ) equal to the system impedance, then the termination impedance R TRM may not be required (e.g., equal to zero ohms). On the other hand, when the termination stack is turned off, the common port AP sees a high impedance provided by the corresponding off - states of the transistors (P TR1 , P TR2 ), …, P TRm . It should be noted that in some embodiments, the number m of transistors (P TR1 , P TR2 ), …, P TRm may be equal to the number of transistors in the stacks TS, TSM, and SS described above with reference to Figure 2A and Figure 3A . It should be noted that in cases where a non - zero termination impedance R TRM may be required, such an impedance can be integrated on the same die (e.g., on - chip) as the termination stack / antenna switch, or be standalone (e.g., off - chip).

[0050] According to an embodiment of the present disclosure, Figure 4A the termination stack (SW - TR, R TRM ) is turned off during the active operating mode of the RF antenna switch (450) and is turned on during the non - active operating mode. Thus, during the active operating mode, the termination stack (SW - TR, R TRM ) can be considered isolated (e.g., in isolation, high impedance) with respect to the common port AP of the RF antenna switch (450), while during the non - active operating mode, the termination stack (SW - TR, R TRM) can be considered to terminate the common port AP of the RF antenna switch (450) with the system impedance. In turn, the termination of the common port AP can limit the RSE in the inactive operating mode, including the RSE associated with the emission of harmonics, intermodulation products, and / or frequency conversion products.

[0051] It should be noted that using Figure 4A the terminal stack (SW-TR, R TRM ) as a means to limit the RSE in the inactive operating mode of the RF antenna switch is compatible with the use of a switching element including at least one conventional N-type FET transistor as described above with reference to Figure 3A / Figure 3B (e.g., Figure 3A of the SWM). In other words, Figure 4A all of the internal switches (SW1, SW2,..., SW k ) of the RF antenna switch (450) shown in Figure 3A may include the switching element SWM described above with reference to

[0052] Continuing to refer to Figure 4A , since the R TR1 , P TR2 ,..., P TRm ) of the (low value) may not be considered a critical factor, such transistors can advantageously be designed to have a small size (e.g., aspect ratio) and as a conventional P-type FET transistor in the sense of this application. Thus, for a gate-to-source voltage of zero volts (and smaller, negative), the P-type FET transistors (P ON ) conduct, while for a gate-to-source voltage of one volt or higher, the P-type FET transistors (P TR1 , P TR2 ,..., P TRm ) turn off. TR1 , P TR2 ,..., P TRm ) turn off.

[0053] Next, according to an embodiment of the present disclosure, and as shown in the timing diagram (400B) of Figure 4B , during the active operating mode of the RF antenna switch (e.g., Figure 4A of 450), the voltage level of the control signal V TRM ) that controls the state of the terminal stack (SW-TR, R CTL_TRM ) is positive and (substantially) higher than the threshold voltage of the conventional P-type transistors (P TR1 , P TR2 ,..., P TRm ) (e.g., Figure 4B of -V THr, large (e.g., 1 V or greater) at about 0.5 V. Thus, as Figure 4B shown in, during the active operation mode of the RF antenna switch (e.g., Figure 4A 450), the state of the terminal stack (SW-TR, R TRM ) is off (e.g., SW-TR OFF ). On the other hand, during the inactive operation mode of the RF antenna switch (e.g., Figure 4A 450), the voltage level of the control signal V TRM that controls the state of the terminal stack (SW-TR, R CTL_TRM ) is zero volts, and thus (substantially) less than the threshold voltage of a conventional P-type transistor (P TR1 , P TR2 , …, P TRm ) (e.g., Figure 4B -V THr of, about 0.5 V). Thus, as Figure 4B shown in, during the inactive operation mode of the RF antenna switch (e.g., Figure 4A 450), the state of the terminal stack (SW-TR, R TRM ) is on (e.g., SW-TR ON ). It should be noted that, as Figure 4B shown in, the voltage level of the control signal V CTL_TRM is provided by a voltage V Figure 5A actively generated by a bias signal generator as shown in, for example, as described later. As previously described in this disclosure, during the inactive operation mode of such a bias signal generator circuit, the voltage V POS can naturally stabilize to zero volts, and thus no additional control and / or switching is required to generate the control signal V POS except for the switching of the operation mode of the bias signal generator circuit as described later. It should be noted that for the case of the P-type transistor described herein, the control voltage applied to the gate of such a transistor can effectively represent the source-to-gate voltage (rather than the gate-to-source voltage), which thus turns on the P-type transistor when it has an amplitude greater than the amplitude of the threshold voltage (e.g., |V CTL_TRM |). THr |).

[0054] Figure 5A shows a (simplified) block diagram of a bias signal generator circuit (500A) that can be configured to generate a (stable) bias voltage (e.g., V POS , V NEG ) at a level suitable for driving the internal switching element of an RF antenna switch, the RF antenna switch including an RF antenna switch according to this teaching. AsFigure 5A As shown, the bias signal generator circuit (500A) can include main functional blocks (510, 530, 540) capable of operating from a single supply voltage V DD . In the case of a handheld device, the single supply voltage V DD can be a battery or a regulated reduced voltage from a battery. Other implementations can include two independent supply voltages (e.g., a negative supply voltage and a positive supply voltage), but similar main functional blocks (e.g., 510, 530, 540).

[0055] In some implementations, the main functional blocks (e.g., 510, 530, 540) can include a block (510) configured to generate a stable reference (e.g., bandgap, reference) voltage V DD from a (e.g., slowly varying) supply voltage V REF . Further, a positive bias generator block (530) and a negative bias generator block (540) can generate a positive (e.g., V REF ) bias voltage and a negative (e.g., V DD ) bias voltage respectively based on voltages V POS and V NEG (referenced to ground Gnd).

[0056] Figure 5B More details of the bias signal generator (500A) block diagram are shown. In particular, Figure 5B details of specific functional blocks that can be included in the main functional blocks (530) and (540) respectively are shown. These include blocks (534, 535) and blocks (544, 545), where the blocks (534, 535) can be included in the main functional block (530) and the blocks (544, 545) can be included in the main functional block (540). Additionally, as Figure 5B shown, in some implementations of the bias signal generator (500A), a block (542) can also be (optionally) included within the block (540). The block (542) can be a negative voltage generator block configured to convert a positive supply voltage V DD into a negative supply voltage (-V DD , e.g., an inverted version of V DD ) having substantially equal magnitude. It should be noted that in some implementations, the negative voltage generator block (542) can be an external block of the bias signal generator (500A), or in other words, not included in the bias signal generator (500A) block diagram shown in Figure 5B . It should also be noted that in some implementations, the shown functional blocks (e.g., 534, 535, 542, 544, 545) can be arranged in a different order / sequence.

[0057] Continuing to refer toFigure 5B , the positive charge pump block (534) and the negative charge pump block (544) can respectively perform charge pump boosting (e.g., boosting to about 3 to 5 times, such as 4 times) on the positive power supply voltage V DD and the negative power supply voltage (-V DD ) generated by the block (542). These voltages are then fed to the corresponding positive voltage regulator block (535) and negative voltage regulator block (545) for regulation by means of the stable reference voltage V REF . Thus, as shown in Figure 5B , the outputs of the positive voltage regulator block (535) and the negative voltage regulator block (545) respectively provide the positive bias voltage V POS and the negative bias voltage V NEG . In addition, as shown in Figure 5A / Figure 5B , the positive bias voltage V POS and the negative bias voltage V NEG can be provided to a selector circuit (e.g., a switch, a level shifter), and the selector circuit generates the control signals (e.g., V Figure 2B and Figure 3B ) described above with reference to, for example, CTL_TS and CTL_SS .

[0058] Continuing to refer to Figure 5A / Figure 5B , according to the active operation mode or the inactive (low power) operation mode, the operation of the bias generator circuit (500A) can be based on the control signal CTL BG . In some example implementations, and as shown in Figure 5A / Figure 5B , such control signals can be routed to each main functional block (e.g., 510, 530, 540) and the corresponding specific functional blocks (e.g., 534, 535, 542, 544, 545) to control the operation mode of each such block. Such control can be comprehensive rather than specific to each block, or can be specific to each block (e.g., each block includes separate control lines and / or commands) for independent mode control of each block. It should be noted that in Figure 5A / Figure 5B , the power rails (e.g., V DD , Gnd) are shown in thick lines, the control lines (e.g., CTL BG ) are shown in dashed lines, and the outputs from the functional blocks are shown in normal lines.

[0059] It should also be noted that although Figure 5AThe functional blocks (e.g., 510, 530, 540) are shown as part of a circuit / block (500A), and the selector circuit (550) is shown external to the circuit / block (500A), but the functional partitioning provided by the circuit (500A) and the circuit (550) can be considered arbitrary, as any other partitioning of such functions integrated in different or the same blocks / modules can be envisioned. In particular, in some embodiments, any one or more of the functions provided by the circuit (500A) and the circuit (550) can be included in any one of the RF antenna switches described in the present disclosure. In other words, in some embodiments, the circuit (500A) and the circuit (550) can be integrally integrated with any one of the RF antenna switches (150), (250), or (450) described above in the present disclosure. Additionally, in some embodiments, one or more of the main blocks (510), (530), or (540) or specific blocks (534), (535), (542), (544), or (545) can be separated from the circuit block (500A) or replicated external to the circuit block (500A) to facilitate component placement and / or improve the performance of the corresponding / target system or integrated chip (IC).

[0060] During Figure 5A / Figure 5B the active operating mode of the bias generator circuit (500A), all of the main functional blocks (510, 530, 540) including the specific blocks (534, 535, 542, 544, 545) can be active to (actively) generate a positive bias voltage V POS and a negative bias voltage V NEG . For example, during the active operating mode, current can flow from the positive supply voltage V DD through each of the said blocks. On the other hand, to conserve power (especially for the operation of charge pumps 534 and 544 which may consume a significant amount of current), during the inactive operating mode, all of the main functional blocks (510, 530, 540) including the specific blocks (534, 535, 542, 544, 545) can be inactive such that these blocks consume substantially no current. For example, during the inactive operating mode, no current can flow from the positive supply voltage V DD through the said blocks. Thus, during the inactive operating mode of the bias generator circuit (500A), the voltages V POS and V NEG can (eventually) stabilize to zero volts, thereby resulting in the above-referenced, for example Figure 2B , Figure 3B and Figure 4BBehavior / state of the switching element of the described RF antenna switch. It should be noted that, according to a non-limiting embodiment, the control of the current flowing through the functional block for corresponding activation and deactivation can be based on the on / off state of the corresponding switch that can enable / disable the conduction path for the said current.

[0061] Figure 5C A (simplified) block diagram of a bias signal generator circuit (500C) according to an embodiment of the present disclosure is shown. Those skilled in the art will recognize that Figure 5C The block diagram of can be based on Figure 5A The block diagram of, including a bias signal generator (500A) and adding a selector switch (560), the selector switch may include a positive bias signal switch circuit (block) SW POS and a negative bias signal switch circuit (block) SW NEG . Under the control of the control signal CTL 560 , the selector switch (560) can output corresponding positive bias voltage V POSM and negative bias voltage V NEGM for operation in an active or inactive operation mode. In particular, during the active operation mode, the selector switch (560) can output voltages V POS and V NEG generated actively by the block (500A) and respectively coupled to the corresponding first throws of switches SW POS and SW NEG , and during the inactive operation mode, the selector switch (560) can output positive (power supply) voltage V POS and negative voltage V NEG coupled to the corresponding second throws of switches SW DD and SW SS respectively. The control signal CTL 560 can be provided to the selector switch (560) to control the states of the positive bias signal switch circuit SW POS and the negative bias signal switch circuit SW NEG . It should be noted that the control signal CTL 560 can be part of the control signal CTL BG for controlling the state of the block (500A), or independent of the control signal CTL BG for controlling the state of the block (500A). As shown in Figure 5C , the corresponding outputs V POS and V NEG of switches SW POSM and SW NEGM can be fed to a selector circuit similar to the selector circuit (550) described above with reference to Figure 5A / Figure 5B .

[0062] Continuing to refer to Figure 5C , according to an embodiment of the present disclosure, the negative voltage V SS may include an amplitude approximately equal to the amplitude of the positive supply voltage V DD . In other words, the negative voltage V SS may be such that V SS ≈ -V DD . According to the teachings of the present disclosure, the negative voltage V SS can be actively generated while minimizing the power consumption of the bias signal generator (500C) during the inactive operation mode. According to one embodiment of the present disclosure, the generation of the negative voltage V SS may include the complete deactivation of the bias signal generator (500A) as described above with reference to Figure 5A / Figure 5B , and the generation of the negative voltage V Figure 5D by a circuit (e.g., SS 580) that can be external to and separated from the bias signal generator (500A). According to another embodiment of the present disclosure, the generation of the negative voltage V SS may include the partial deactivation of the bias signal generator (500A) as described above with reference to Figure 5A / Figure 5B , and the generation of the negative voltage V Figure 5B by a functional block (e.g., SS 542) that can be inside the bias signal generator (500A). In other words, according to the teachings of the present disclosure, flexibility in implementation based on the design / implementation constraints of the target system can be provided. For example, if the target system includes a bias signal generator (e.g., 500A) that may not be suitable for providing a modified negative voltage (e.g., V SS ) during the inactive operation mode (i.e., while providing reduced power consumption), then the solution provided by this teaching can be represented in Figure 5D . On the other hand, if the target system includes a bias signal generator (e.g., 500A) that may be suitable for providing a modified negative voltage (e.g., V SS ) during the inactive operation mode (i.e., while providing reduced power consumption), then the solution provided by this teaching can be represented in Figure 5E / Figure 5F .

[0063] Figure 5D FIG. shows a block diagram of a bias signal generator circuit (500D) according to an embodiment of the present disclosure, wherein the negative voltage V SSThe bias signal generator (500A) may be generated by a circuit (580) that may be external to the bias signal generator (500A) and separate from the bias signal generator (500A). Figure 5D As shown in FIG. 5 , the circuit ( 580 ) may be a negative voltage generator configured to convert a positive power supply voltage V DD Converted into a negative supply voltage V SS ≈-V DD (For example, V DD The control signal CTL 580 May be provided to the circuit (580) to activate the circuit (580) during an inactive operating mode of the bias signal generator (500A).

[0064] In some embodiments, it may not be necessary during the active operating mode of the bias signal generator (500A). Figure 5D circuit (580), and therefore, the control signal CTL 580 The circuit (580) may be disabled (eg, reduced power consumption) during such an active operating mode. This may include where the bias signal generator (500A) may include the above referenced Figure 5B The negative bias voltage V NEG The case of the block (542) generating the internal negative supply voltage.

[0065] In some embodiments, during an active mode of operation of the bias signal generator (500A) it may be necessary to Figure 5D circuit (580), and therefore, the control signal CTL 580 The circuit (580) may not be deactivated during such an active operating mode. This may include where the bias signal generator (500A) may not include the above referenced Figure 5B block (542) described and thus can be used for negative bias voltage V NEG The externally generated negative (power supply) voltage V SS situation.

[0066] like Figure 5D As shown in , in some embodiments, control of the bias signal generator (500A) and circuit (580) regarding corresponding activation and deactivation can be provided via a single control signal STB. In this case, as Figure 5D As shown in , an inverter such as a logic inverter INV can be used to invert the polarity / state of the control signal STB so that blocks (500A) and (580) operate in opposite operating modes (activated or deactivated). Figure 5D As shown in FIG. 5 , the control signal STB (or an inverted version) may also be used to control the switch SW of the selector switch (560).POS and SW NEG status.

[0067] Figure 5E shows a block diagram of a bias signal generator circuit (500E) according to an embodiment of the present disclosure, wherein a negative voltage V SS can be generated by a negative voltage generator block (542) that can be inside the bias signal generator (500A) as described above with reference to Figure 5B During the active operating mode of the bias signal generator circuit (500E), all functional blocks (e.g., 510, 534, 535, 542, 544, 545) of the bias signal generator (500A) can be active to (actively) generate a positive bias voltage V POS and a negative bias voltage V NEG , and the corresponding states of the positive bias signal switch circuit (block) SW POS and the negative bias signal switch circuit (block) SW NEG can be configured to output the positive bias voltage V POS and the negative bias voltage V NEG respectively. In other words, the operation (and output) of the bias signal generator circuit (500E) during the active mode is similar to Figure 5A the operation (and output) of the circuit (500A) during the active mode.

[0068] On the other hand, in order to save power (especially with respect to the operation of charge pumps 534 and 544 that may consume a relatively large amount of current), while preventing the level of the bias voltage from dropping to zero volts, during the inactive operating mode, the functional blocks (510, 534, 535, 544, 545, shown as shaded blocks in Figure 5E ) of the bias signal generator (500A) can be inactive, e.g., substantially no current is consumed by such blocks, while the functional block (542, shown as a bright block in Figure 5E ) can be active to actively (generate) a negative supply voltage V SS (e.g., V SS ≈ -V DD ). Additionally, and as shown in Figure 5E , during the inactive operating mode, the corresponding states of the positive bias signal switch circuit SW POS and the negative bias signal switch circuit SW NEG can be configured to output the positive supply voltage V DD and the negative supply voltage V SS respectively.

[0069] Figure 5F shows Figure 5EAlternative implementations of the bias signal generator circuit, wherein the bias signal generator (e.g., Figure 5E of 500 A) and the selector switch (560) are part of the same piece (500F, e.g., an IC module). As previously described in this disclosure, the partitioning of the functions provided by the described circuits / pieces can be considered arbitrary. However, given the target system under consideration, there may be some limitations / constraints on such partitioning flexibility (in principle). Such limitations / constraints can be addressed according to the teachings of this disclosure.

[0070] In contrast to Figure 5A the bias signal generator (500A), during the inactive operation mode, the bias signal generator circuit according to this disclosure (e.g., 500C to 500F) actively generates a positive voltage and a negative voltage (e.g., V DD and V SS ) with a corresponding amplitude large enough (e.g., 1 volt or greater) to control the state of the internal (switch) elements (e.g., Figure 2A of 150, 250) of the RF antenna switch (e.g., Figure 2A of SW) to a known state (designed for low RSE) corresponding to the off state (e.g., Figure 2B of SW OFF ). This can be seen in the Figure 5G timing diagram (500G), which is to be read in view of and in contrast to the description of the Figure 2B timing diagram (200B), which shows the states TS Figure 2A of the corresponding through-stack TS and shunt-stack SS in OFF and SS ON defining the inactive state SW Figure 2A of the switch element (e.g., INACT of SW). In other words, because the levels of the control voltages V CTL-TS and V CTL-SS (e.g., V DD and V SS ) are high enough / remain high enough during the inactive mode, then as shown in Figure 5G , the through-stack TS can be controlled to the off state TS OFF , and the shunt-stack SS can be controlled to the on state SS ON to effectively isolate the common port AP from the throws (e.g., Figure 2A of S1, S2, …, Sk) of the RF antenna switch.

[0071] Applications of novel devices and systems that may include various embodiments include electronic circuitry used in high-speed computers, communication and signal processing circuitry, modems, single-processor modules or multi-processor modules, single or multiple embedded processors, data switches, and specialized modules including multi-layer, multi-chip modules. Such devices and systems may also be included as sub-components within various electronic systems such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., mp3 players), transportation vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), and others. Some embodiments may include multiple methods.

[0072] As used in this disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate that determines the conductivity of the transistor, and includes an insulated gate having a metal or metal-like, insulator, and / or semiconductor structure. The term "metal" or "metal-like" includes at least one conductive material (e.g., aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0073] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of approximately 3 kHz to approximately 300 GHz. The term also includes the frequencies used in wireless communication systems. RF frequencies may be the frequencies of electromagnetic waves or the frequencies of alternating voltage or current in a circuit.

[0074] The various embodiments of the present invention can be implemented to meet a wide variety of specifications. Unless otherwise stated above, selecting appropriate component values is a matter of design choice. The various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures) or in the form of hybrid or discrete circuits. Any suitable substrate and process (including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS)) can be used to fabricate the integrated circuit embodiments. Unless otherwise stated above, the embodiments of the present invention can be implemented in other transistor technologies, such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the embodiments of the present invention are particularly useful when fabricated using an SOI- or SOS-based process or a process with similar characteristics. Fabrication using an SOI or SOS process in CMOS enables the circuit to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can typically be kept low (or minimized and consistent across all cells, allowing them to be compensated).

[0075] The voltage levels can be adjusted, and / or the voltage and / or logic signal polarities can be inverted, according to specific specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). The component voltage, current, and power handling capabilities can be adjusted as needed, for example, by adjusting the device size, "stacking" components (especially FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components can be added without significantly changing the function of the disclosed circuit to enhance the capabilities of the disclosed circuit and / or to provide additional functionality.

[0076] The circuits and devices according to the present invention can be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention can be fabricated as integrated circuits (ICs), which can be encapsulated in IC packages and / or modules to facilitate handling, fabrication, and / or improved performance. In particular, IC embodiments of the present invention are often used in modules, where one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. Then, typically, the IC and / or module are often combined with other components on a printed circuit board to form part of a final product such as a cellular phone, laptop computer, or electronic tablet, or to form a higher-level module that can be used in a variety of products such as vehicles, test equipment, medical equipment, etc. Through various configurations of the modules and components, such ICs typically implement a communication mode, usually wireless communication.

[0077] Multiple embodiments of the present invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the present invention. For example, some of the steps described above can be order-independent and thus can be performed in an order different from the order described. Additionally, some of the steps described above can be optional. The various activities described with respect to the methods identified above can be performed in a repetitive, serial, and / or parallel manner.

[0078] It should be understood that the foregoing description is intended to be illustrative, not limiting, of the scope of the present invention, which is defined by the scope of the appended claims, and other embodiments are within the scope of the claims. In particular, the scope of the present invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the appended claims. (Note that the bracketed designations of claim elements are for ease of reference to such elements and do not themselves indicate a particular required order or enumeration of the elements; furthermore, such designations can be reused in dependent claims as a reference to additional elements without being regarded as initiating a conflicting sequence of designations).

Claims

1. A radio frequency (RF) antenna switch, comprising: A first switching element coupled between a common port of the RF antenna switch and a first throw of the RF antenna switch, the first switching element comprising: A through-stack including a plurality of N-type FET transistors arranged in series connection, the through-stack being coupled between the common port and the first throw; and A shunt-stack including a plurality of N-type FET transistors arranged in series connection, the shunt-stack being coupled between the first throw and a reference ground, and A bias signal generation circuit including at least one charge pump, the bias signal generator being configured to generate a positive bias voltage and a negative bias voltage based on a positive power supply voltage, Wherein, The RF antenna switch is configured to operate according to an active mode and an inactive mode, the inactive mode defining a low power consumption mode of the RF antenna switch, During the active mode, the control voltage applied to the first switching element includes a positive voltage and a negative voltage having respective amplitudes of the positive bias voltage and the negative bias voltage, During the inactive mode, the control voltage applied to the first switching element includes a positive voltage and a negative voltage having respective amplitudes greater than zero and less than the respective amplitudes of the positive bias voltage and the negative bias voltage, and During the inactive mode, the at least one charge pump is inactive.

2. The radio frequency (RF) antenna switch according to claim 1, wherein: The positive voltage of the control voltage applied to the first switching element during the inactive mode is the positive power supply voltage, and The negative voltage of the control voltage applied to the first switching element during the inactive mode is an inverted version of the positive power supply voltage, the amplitude of which is substantially equal to the amplitude of the positive power supply voltage.

3. The radio frequency (RF) antenna switch according to claim 2, further comprising: A positive bias signal switch configured to selectively output one of the positive bias voltage or the positive power supply voltage; And A negative bias signal switch configured to selectively output one of the negative bias voltage or the inverted version of the positive power supply voltage.

4. The radio frequency (RF) antenna switch according to any one of claims 1 to 3, wherein: The control voltage applied to the first switch during the inactive mode is configured to control the through-stack to an off state and the shunt-stack to an on state to isolate the common port from the first throw.

5. The radio frequency (RF) antenna switch according to any one of claims 1 to 4, wherein: The plurality of N-type FET transistors of the through-stack includes at least one intrinsic N-type FET transistor.

6. The radio frequency (RF) antenna switch according to any one of claims 1 to 5, wherein: The plurality of N-type transistors of the shunt-stack includes at least one intrinsic N-type transistor.

7. The radio frequency (RF) antenna switch according to claim 6, wherein: The plurality of N-type transistors of the through-stack or the shunt-stack includes at least one conventional N-type transistor.

8. The radio frequency (RF) antenna switch according to any one of claims 1 to 4, wherein: Each transistor in the plurality of N-type transistors of the through-stack or the shunt-stack is an intrinsic N-type transistor.

9. The radio frequency (RF) antenna switch according to any one of claims 1 to 4, wherein: Each transistor in the plurality of N-type transistors of the through-stack and the shunt-stack is an intrinsic N-type transistor.

10. The radio frequency (RF) antenna switch according to any one of claims 1 to 4, wherein: The plurality of N-type FET transistors of the through-stack includes at least one conventional N-type FET transistor.

11. The radio frequency (RF) antenna switch according to any one of claims 1 to 4, wherein: The plurality of N-type transistors of the shunt-stack includes at least one conventional N-type transistor.

12. The radio frequency (RF) antenna switch according to any one of claims 1 to 4, wherein: Each transistor in the plurality of N-type transistors of the through-stack or the shunt-stack is a conventional N-type transistor.

13. The radio frequency (RF) antenna switch according to any one of claims 1 to 4, wherein: Each transistor in the plurality of N-type transistors of the through-stack and the shunt-stack is a conventional N-type transistor.

14. The radio frequency (RF) antenna switch according to any one of claims 1 to 13, wherein: The respective amplitudes of the positive bias voltage and the negative bias voltage are greater than three.

15. The radio frequency (RF) antenna switch according to any one of claims 1 to 14, wherein: During the inactive mode, the respective amplitudes of the positive voltage and the negative voltage of the control voltage applied to the first switching element are greater than one.

16. The radio frequency (RF) antenna switch according to any one of claims 1 to 15, wherein: The bias signal generation circuit further includes a negative voltage generator configured to generate a negative power supply voltage based on the positive power supply voltage, The at least one charge pump includes a negative charge pump for generating the negative bias voltage based on the negative power supply voltage, and During the inactive mode, the negative voltage generator is active to provide the negative voltage of the control voltage.

17. The radio frequency (RF) antenna switch according to any one of claims 1 to 15, further comprising a first negative voltage generator configured to generate a first negative power supply voltage based on the positive power supply voltage, wherein: The bias signal generation circuit further includes a second negative voltage generator configured to generate a second negative power supply voltage based on the positive power supply voltage, The at least one charge pump includes a negative charge pump for generating the negative bias voltage based on the second negative power supply voltage, and During the inactive mode, the first negative voltage generator is active to provide the negative voltage of the control voltage, and the second negative voltage generator is inactive.

18. The radio frequency (RF) antenna switch according to claim 17, wherein: During the active mode, the first negative voltage generator is inactive, and the second negative voltage generator is active.

19. A radio frequency (RF) antenna switch, comprising: A first switching element coupled between a common port of the RF antenna switch and a first throw of the RF antenna switch, the first switching element comprising: A through-stack including a plurality of intrinsic N-type FET transistors and at least one conventional N-type FET transistor arranged in series connection, the through-stack being coupled between the common port and the first throw; and A shunt-stack including a plurality of intrinsic N-type FET transistors arranged in series connection, the shunt-stack being coupled between the first throw and a reference ground.

20. The radio frequency (RF) antenna switch according to claim 19, wherein: The RF antenna switch is configured to operate according to an active mode and an inactive mode, the inactive mode defining a low power consumption mode, The control voltage applied to the first switching element during the active mode includes a positive voltage and a negative voltage having respective magnitudes greater than one, and The control voltage applied to the first switching element during the inactive mode has a magnitude equal to zero.

21. The radio frequency (RF) antenna switch according to claim 20, wherein: The respective magnitudes of the positive voltage and the negative voltage are in the range from 3.2 to 4.

2.

22. The radio frequency (RF) antenna switch according to any one of claims 19 to 21, wherein: The impedance of the RF antenna switch presented at the common port during the inactive mode is a high impedance substantially corresponding to the off-impedance of at least one conventional N-type FET transistor of the through-stack.

23. The radio frequency (RF) antenna switch according to any one of claims 20 to 22, wherein: The control voltage applied to the first switch during the inactive mode is configured to: Turn on the respective plurality of intrinsic N-type FET transistors of the through-stack and the shunt-stack, and Turn off at least one conventional N-type FET transistor of the through-stack.

24. The radio frequency (RF) antenna switch according to any one of claims 20 to 23, wherein, The control voltage includes: A through-stack control voltage applied to the gates of the plurality of intrinsic N-type FET transistors and at least one conventional N-type FET transistor of the through-stack; and A shunt-stack control voltage applied to the gates of the plurality of intrinsic N-type FET transistors of the shunt-stack.

25. The radio frequency (RF) antenna switch according to claim 24, wherein: During the active mode, The control voltage is configured to control the on-state and off-state of the first switch to couple the first throw to the common port and decouple the first throw from the common port, respectively, the on-state of the first switch being provided by the on-state of the through-stack via a corresponding positive voltage and the off-state of the shunt-stack via a corresponding negative voltage, and the off-state of the first switch being provided by the off-state of the through-stack via a corresponding negative voltage and the on-state of the shunt-stack via a corresponding positive voltage, and During the inactive mode, The control voltage of zero magnitude is configured to turn off the at least one conventional N-type FET transistor.

26. The radio frequency (RF) antenna switch according to any one of claims 20 to 25 further comprises: A terminal stack including a plurality of conventional P-type FET transistors arranged in series connection, the terminal stack being coupled between the common port and the reference ground, wherein a terminal stack control voltage applied to the gates of the plurality of conventional P-type FET transistors: Has a positive voltage greater than one volt during the active mode, thereby turning off the terminal stack to present a high impedance at the common port, and Has a zero voltage during the inactive mode, thereby turning on the terminal stack to present a low terminal impedance at the common port.

27. The radio frequency (RF) antenna switch according to claim 26, wherein: The low terminal impedance is equal to 50 ohms.

28. The radio frequency (RF) antenna switch according to claim 26, wherein: The low terminal impedance is based on a combination of the respective on-resistances of the plurality of conventional P-type FET transistors.

29. The radio frequency (RF) antenna switch according to claim 28, wherein: The terminal stack is coupled to the reference ground through a series-connected resistor, and The low terminal impedance is provided by a combination of the series-connected resistor and the respective on-resistances.

30. The radio frequency (RF) antenna switch according to any one of claims 20 to 29 further comprises: A bias signal generation circuit including at least one charge pump, the at least one charge pump being configured to generate a positive voltage and / or a negative voltage based on a power supply voltage during the active mode, wherein, During the inactive mode, the at least one charge pump is inactive, thereby stabilizing the respective amplitudes of the positive voltage and / or the negative voltage to zero.

31. The radio frequency (RF) antenna switch according to any one of claims 19 to 30, wherein: Each of the respective plurality of intrinsic N-type FET transistors in the through-stack and the shunt-stack has a threshold voltage equal to or greater than 450 millivolts, and The at least one conventional N-type FET transistor has a threshold voltage equal to or less than zero volts.

32. The radio frequency (RF) antenna switch according to claim 31 further comprises: One or more additional switching elements coupled between the common port of the RF antenna switch and the respective throws of one or more additional throws, each of the one or more additional switching elements including: A respective through-stack including a plurality of intrinsic N-type FET transistors and at least one conventional N-type FET transistor arranged in series connection, the respective through-stack being coupled between the common port and the respective throw; and A respective shunt-stack including a plurality of intrinsic N-type FET transistors arranged in series connection, the shunt-stack being coupled between the respective throw and the reference ground.

33. A radio frequency (RF) front-end system comprising: An antenna; And The RF antenna switch according to any one of claims 19 to 32, wherein the common port of the RF antenna switch is coupled to the antenna.

34. A radio frequency (RF) antenna switch, comprising: A first switching element coupled between a common port of the RF antenna switch and a first throw of the RF antenna switch, the first switching element comprising: A through-stack comprising a plurality of intrinsic N-type FET transistors arranged in series connection, the through-stack being coupled between the common port and the first throw; and A shunt-stack comprising a plurality of intrinsic N-type FET transistors arranged in series connection, the shunt-stack being coupled between the first throw and a reference ground, and A termination-stack comprising a plurality of conventional P-type FET transistors arranged in series connection, the termination-stack being coupled between the common port and the reference ground.

35. The radio frequency (RF) antenna switch according to claim 34, wherein: The RF antenna switch is configured to operate according to an active mode and an inactive mode, the inactive mode defining a low power consumption mode, A first switching control voltage applied to the first switching element during the active mode comprises a positive voltage and a negative voltage having respective magnitudes greater than one, A termination-stack control voltage applied to the termination-stack during the active mode comprises a positive voltage having a magnitude greater than one, and The first switching control voltage and the termination-stack control voltage during the inactive mode have magnitudes equal to zero.

36. The radio frequency (RF) antenna switch according to claim 35, wherein: The termination-stack control voltage applied to the gates of the plurality of conventional P-type FET transistors: Turns off the termination-stack during the active mode to present a high impedance at the common port, and Turns on the termination-stack during the inactive mode to present a low termination impedance at the common port.

37. The radio frequency (RF) antenna switch according to any one of claims 34 to 36, wherein: The through-stack further comprises at least one conventional N-type FET transistor arranged in series connection with the plurality of intrinsic N-type FET transistors of the through-stack.

38. The radio frequency (RF) antenna switch according to any one of claims 35 to 37, further comprising: A bias signal generation circuit comprising at least one charge pump, the at least one charge pump being configured to generate a positive voltage and / or a negative voltage based on a power supply voltage during the active mode, Wherein, During the inactive mode, the at least one charge pump is inactive, thereby stabilizing the respective magnitudes of the positive voltage and / or the negative voltage to zero.

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