Synchronous pulse signal delay adjusting circuit

Abstract

The invention relates to a synchronous pulse signal delay adjusting circuit, belongs to the technical field of pulse signal delay, and solves the problems of complex structure and low efficiency of a synchronous pulse signal delay adjusting circuit in the prior art. Comprising a delay circuit, a phase detection circuit and a judgment unit, the delay circuit is used for delaying an input synchronous pulse signal when receiving a delay signal and inputting the delayed synchronous pulse signal into the phase detection circuit; the phase detection circuit is used for performing phase detection on the delayed synchronous pulse signal and outputting a sequence corresponding to the current phase; the judgment unit is used for judging whether the current phase is a target phase or not according to the sequence corresponding to the current phase, and if yes, synchronous pulse signal delay adjustment is completed; otherwise, a delay signal is sent to the delay circuit. And rapid synchronization pulse signal delay is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of pulse signal delay, and particularly to a synchronous pulse signal delay adjustment circuit. Background Art

[0002] When signals are synchronized, the circuit receiving the synchronous pulse signal needs to ensure that the phase of the pulse signal sampled each time is fixed. However, even for the same clock source, after frequency multiplication and division operations within different circuits, the phase relationship between the working clock of the circuit receiving the synchronous pulse signal and the synchronous pulse has a certain randomness. At the same time, hardware differences will also bring uncertainties. The superposition of the two leads to the uncertainty of sampling the synchronous pulse signal by the circuit receiving the synchronous pulse signal, which will cause the rising edge of the synchronous pulse signal to be close to the rising edge of the working clock signal, and the sampling result to randomly jump between 0 / 1, thus resulting in unstable sampling results. If the phase relationship between the pulse signal and the working clock can be quickly and accurately detected, then phase adjustment can be performed to avoid unstable sampling results. However, the existing synchronous pulse signal delay adjustment circuit has a complex structure and low efficiency. Summary of the Invention

[0003] In view of the above analysis, an embodiment of the present invention aims to provide a synchronous pulse signal delay adjustment circuit to solve the problems of complex structure and low efficiency of the existing synchronous pulse signal delay adjustment circuit.

[0004] On the one hand, an embodiment of the present invention provides a synchronous pulse signal delay adjustment circuit, including a delay circuit, a phase detection circuit, and a decision unit;

[0005] The delay circuit is used to delay the input synchronous pulse signal when receiving a delay signal, and input the delayed synchronous pulse signal into the phase detection circuit;

[0006] The phase detection circuit is used to perform phase detection on the delayed synchronous pulse signal and output a sequence corresponding to the current phase;

[0007] The decision unit is used to judge whether the current phase is the target phase according to the sequence corresponding to the current phase. If so, the synchronous pulse signal delay adjustment is completed; otherwise, a delay signal is sent to the delay circuit.

[0008] Based on a further improvement of the above technical solution, the delay circuit includes a plurality of cascaded delay units and a multiplexer;

[0009] A synchronization pulse signal is input to the input terminal of the first delay unit among the multiple cascaded delay units, and the output terminal is connected to the next delay unit; the input terminal of each intermediate delay unit is connected to the output terminal of the previous delay unit, and the output terminal is connected to the input terminal of the next delay unit; the input terminal of each delay unit is connected to a selection channel; the output terminal of the last delay unit is connected to a selection channel of the multiplexer switch.

[0010] Based on a further improvement of the above technical solution, the number of the delay units is determined according to the working clock of the clock domain where the synchronization pulse signal delay adjustment circuit is located.

[0011] Based on a further improvement of the above technical solution, the number of the delay units is the minimum number that satisfies the following formula:

[0012] The delay time of each delay unit × the number of delay units > the period of the working clock.

[0013] Based on a further improvement of the above technical solution, the decision unit is a look-up table unit with multiple-bit input and 2-bit output; the output data of the phase detection circuit is input to the look-up table unit as the search address, and the look-up table unit outputs the data stored at the address as a mark of whether it is the target phase.

[0014] Based on a further improvement of the above technical solution, the following method is used to determine the data stored at each address of the look-up table unit:

[0015] According to the multiple relationship between the sampling clock and the working clock, determine the address when the pulse signal has a 0 phase difference with the working clock as the target address;

[0016] Calculate the corresponding target addresses for other phase differences based on the target address at the 0 phase difference;

[0017] Write 1 to the target address in the look-up table unit that is closest to and write 0 to the target addresses corresponding to other phase differences,

[0018] where N represents the multiple of the sampling clock frequency relative to the working clock frequency.

[0019] Based on a further improvement of the above technical solution, the phase detection circuit includes the synchronization pulse signal rising edge detection circuit and the clock signal detection circuit;

[0020] The synchronization pulse signal detection circuit is used to judge the rising edge of the input pulse signal, and when the rising edge of the synchronization pulse signal arrives, a decision signal is generated and sent to the decision unit;

[0021] The clock signal detection circuit is used to perform multi-stage register storage on the working clock of the current clock domain, and send the working clock and the stored value of each stage of the working clock to the decision-making unit;

[0022] The decision-making unit is used to determine whether the current phase is the target phase according to the sequence corresponding to the current phase when receiving the decision signal.

[0023] Based on the further improvement of the above technical solution, the synchronization pulse signal detection circuit includes three cascaded flip-flops, an inversion circuit, and an AND gate;

[0024] The data input terminal of the first flip-flop of the synchronization pulse signal detection circuit receives the pulse signal; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop;

[0025] The output terminal of the last flip-flop of the synchronization pulse signal detection circuit is connected to the input terminal of the inversion circuit;

[0026] The clock signal input terminals of each flip-flop of the synchronization pulse signal detection circuit are all connected to the sampling clock of the current clock domain;

[0027] The output terminal of the second-to-last flip-flop of the synchronization pulse signal detection circuit and the output terminal of the inversion circuit are connected to the input terminal of the AND gate; the output terminal of the AND gate outputs the decision signal.

[0028] Based on the further improvement of the above technical solution, the clock signal detection circuit includes a plurality of cascaded flip-flops;

[0029] The data input terminal of the first flip-flop of the clock signal detection circuit is connected to the working clock of the current clock domain; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop;

[0030] The clock signal input terminals of each flip-flop of the clock signal detection circuit are all connected to the sampling clock of the current clock domain;

[0031] The working clock and the output terminals of each flip-flop of the clock signal detection circuit are connected to the input terminal of the decision-making unit.

[0032] Based on the further improvement of the above technical solution, the number of flip-flops in the clock signal detection circuit is set according to the multiple of the sampling clock frequency of the current clock domain relative to the working clock frequency.

[0033] Compared with the prior art, the synchronous pulse signal delay adjustment circuit provided in this embodiment delays the input synchronous pulse signal through a delay circuit, then detects the phase of the delayed synchronous pulse signal through a phase detection circuit, and judges whether the delayed phase is the target phase through a decision unit. If not, continue to delay until the decision unit determines that the detected phase is the target phase, so as to quickly and accurately obtain the phase difference between the pulse signal and the current working clock, and quickly delay the synchronous pulse signal, so that the phase of the delayed synchronous pulse signal is the target phase. The structure is simple and easy to implement, and the efficiency of delay adjustment is improved, so that the working clock can stably sample the delayed synchronous pulse, and the stability of the sampling result is improved.

[0034] In the present invention, the above technical solutions can also be combined with each other to achieve more preferred combination schemes. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can be made obvious from the description, or understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the content specifically pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings are only for the purpose of showing specific embodiments, and are not considered as a limitation of the present invention. Throughout the drawings, the same reference signs denote the same components;

[0036] Figure 1 is a block diagram of the synchronous pulse signal delay adjustment circuit according to an embodiment of the present invention;

[0037] Figure 2 is a circuit diagram of the delay circuit according to an embodiment of the present invention;

[0038] Figure 3 is a circuit diagram of the synchronous pulse signal detection circuit according to an embodiment of the present invention;

[0039] Figure 4 is a schematic diagram of the timing relationship according to an embodiment of the present invention;

[0040] Figure 5 is a schematic diagram of the timing relationship according to an embodiment of the present invention;

[0041] Figure 6 is a schematic diagram of the timing relationship according to an embodiment of the present invention;

[0042] Figure 7 is a schematic diagram of the timing relationship according to an embodiment of the present invention;

[0043] Figure 8 is a circuit diagram of the clock signal detection circuit according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] The preferred embodiments of the present invention will be specifically described below in conjunction with the accompanying drawings. The accompanying drawings form a part of this application and are used together with the embodiments of the present invention to explain the principles of the present invention, rather than to limit the scope of the present invention.

[0045] A specific embodiment of the present invention discloses a synchronous pulse signal delay adjustment circuit, as Figure 1 shown, which includes a delay circuit, a phase detection circuit, and a decision unit;

[0046] The delay circuit is used to delay the input synchronous pulse signal when receiving a delay signal, and input the delayed synchronous pulse signal into the phase detection circuit;

[0047] The phase detection circuit is used to perform phase detection on the delayed synchronous pulse signal and output a sequence corresponding to the current phase;

[0048] The decision unit is used to judge whether the current phase is the target phase according to the sequence corresponding to the current phase. If so, the delay adjustment of the synchronous pulse signal is completed; otherwise, a delay signal is sent to the delay circuit.

[0049] During implementation, the input pulse signal comes from the same source but different clock domains. The current clock domain is the clock domain where the synchronous pulse signal delay adjustment circuit is located. The working clock of the current clock domain is obtained by dividing the sampling clock.

[0050] Compared with the prior art, the synchronous pulse signal delay adjustment circuit provided in this embodiment delays the input synchronous pulse signal through the delay circuit, then performs phase detection on the delayed synchronous pulse signal through the phase detection circuit, and judges whether the delayed phase is the target phase through the decision unit. If not, continue to delay until the decision unit determines that the detected phase is the target phase, so as to quickly and accurately obtain the phase difference between the pulse signal and the current working clock, and quickly delay the synchronous pulse signal, so that the phase of the delayed synchronous pulse signal is the target phase. The structure is simple and easy to implement, and the efficiency of delay adjustment is improved, so that the working clock can stably sample the delayed synchronous pulse, and the stability of the sampling result is improved.

[0051] During implementation, as Figure 2 shown, the delay circuit includes a plurality of cascaded delay units and a multiplexer;

[0052] A synchronization pulse signal is input to the input terminal of the first delay unit among the multiple cascaded delay units, and the output terminal is connected to the next delay unit; the input terminal of each intermediate delay unit is connected to the output terminal of the previous delay unit, and the output terminal is connected to the input terminal of the next delay unit; the input terminals of each delay unit are all connected to a selection channel; the output terminal of the last delay unit is connected to a selection channel of the multiplexer switch.

[0053] In order to accurately adjust to the target phase, the number of delay units of the delay circuit is determined according to the working clock of the clock domain where the synchronization pulse signal delay adjustment circuit is located.

[0054] The number of the delay units is the minimum number that satisfies the following formula:

[0055] The delay time of each delay unit × the number of delay units > the period of the working clock.

[0056] For example, if the delay time of each delay unit is 36 ps and the frequency of the working clock is 600 MHz, then at least 48 delay units are required.

[0057] The range of the delay value is 0 - 47. Initially, the delay value is set to 0. At this time, the multiplexer switch is placed in the first channel. The phase of the synchronization pulse signal at 0 delay is detected by the phase detection circuit to determine whether it is the target phase. If not, a delay signal is output. The delay unit switches the multiplexer switch to the next channel according to the delay signal, and the phase of the synchronization pulse signal at 36 ps delay is detected by the phase detection circuit, and so on.

[0058] Specifically, the phase detection circuit includes the synchronization pulse signal rising edge detection circuit and the clock signal detection circuit;

[0059] The synchronization pulse signal detection circuit is used to judge the rising edge of the input pulse signal and generate a decision signal when the rising edge of the synchronization pulse signal arrives;

[0060] The clock signal detection circuit is used to perform multi-stage storage on the working clock of the current clock domain and send the working clock and each stage storage value of the working clock to the decision unit.

[0061] During implementation, in order to obtain a stable pulse signal and avoid metastability, the input pulse is clocked multiple times through the first register circuit to obtain a stable rising edge of the pulse signal.

[0062] During implementation, as Figure 3 described, the synchronization pulse signal detection circuit includes three cascaded flip-flops, an inversion circuit, and an AND gate;

[0063] The data input terminal of the first flip-flop of the synchronous pulse signal detection circuit receives the pulse signal; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop;

[0064] The output terminal of the last flip-flop of the synchronous pulse signal detection circuit is connected to the input terminal of the inversion circuit;

[0065] The clock signal input terminal of each flip-flop of the synchronous pulse signal detection circuit is connected to the sampling clock of the current clock domain;

[0066] The output terminal of the penultimate flip-flop of the synchronous pulse signal detection circuit and the output terminal of the inversion circuit are connected to the input terminal of the AND gate; the output terminal of the AND gate outputs a decision signal.

[0067] During implementation, in order to accurately detect the state of the working clock at the rising edge moment of the pulse signal, as Figure 8 shown, the clock signal detection circuit includes a plurality of cascaded flip-flops;

[0068] The data input terminal of the first flip-flop of the clock signal detection circuit is connected to the working clock of the current clock domain; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop;

[0069] The clock signal input terminal of each flip-flop of the clock signal detection circuit is connected to the sampling clock of the current clock domain;

[0070] The working clock and the output terminal of each flip-flop of the clock signal detection circuit are connected to the input terminal of the decision unit.

[0071] During implementation, the phase difference relationship between the input pulse signal and the working clock is related to the multiple relationship between the sampling clock and the working clock. Therefore, the number of flip-flops in the clock signal detection circuit is set according to the multiple of the sampling clock frequency in the current clock domain relative to the working clock frequency.

[0072] For example, if the frequency of the sampling clock is 4 times that of the working clock, 3-stage flip-flops are used; if the frequency of the sampling clock is 5 times that of the working clock, 4-stage flip-flops are used, that is, the number of flip-flops is the multiple number minus one.

[0073] The value of the working clock at the current moment and the output results of the multi-stage flip-flops constitute a sequence corresponding to the current phase.

[0074] The working clock signal and the output signal of each flip-flop in the clock signal detection circuit are both input to the decision unit. When the decision signal is valid, the decision unit determines whether the current phase is the target phase according to the sequence corresponding to the current phase.

[0075] During implementation, the clock signal of the decision unit is the sampling signal of the current clock domain.

[0076] During implementation, in order to quickly determine the target phase, the decision unit is a lookup table unit with multiple-bit input and 2-bit output; the output data of the phase detection circuit is input as the lookup address to the lookup table unit, and the lookup table unit outputs the data stored at the address as a flag indicating whether it is the target phase.

[0077] During implementation, the number of input bits of the lookup table unit is the multiple of the sampling clock frequency in the current clock domain relative to the working clock frequency. Therefore, by using the working clock and the stored value of each stage of the working clock as the address, the data stored in the lookup table can be quickly read to obtain the result.

[0078] That is, the working clock and the output terminals of each flip-flop in the clock signal detection circuit are connected to the address input terminal of the lookup table unit, and the flag indicating whether the phase corresponding to the address is the target phase is stored at the address of the lookup table. For example, if three-stage storage is adopted, the sequence of stored values includes four elements, which are the working clock value at the current moment, the first-stage stored value of the working clock (the output value of the first flip-flop), the second-stage stored value of the working clock (the output value of the second flip-flop), and the third-stage stored value of the working clock (the output value of the third flip-flop) in sequence.

[0079] The data stored at each address of the lookup table unit is determined in the following manner:

[0080] According to the frequency multiplication relationship between the sampling clock and the working clock, the address when the pulse signal has a 0-phase difference from the working clock is determined as the target address;

[0081] Based on the target address at the 0-phase difference, the target addresses corresponding to other phase differences are calculated;

[0082] Write 1 to the target address in the lookup table unit that is closest to , and write 0 to the target addresses corresponding to other phase differences,

[0083] where N represents the multiple of the sampling clock frequency relative to the working clock frequency.

[0084] Since the other phase relationships between the pulse signal and the working clock can all be calculated based on the target address when the pulse signal is in the same phase as the working clock, during implementation, first calculate the target address when the pulse signal is in the same phase as the working clock (i.e., 0 phase), and based on the target address at the 0-phase difference, calculate the target addresses corresponding to other phase differences.

[0085] The multiple of the sampling clock frequency relative to the working clock frequency is usually 4 times or more.

[0086] The high level and low level of the working clock each maintain sampling clock cycles. If That is, N = 4 or N = 5. At the decision moment, the working clock is at a low level. Since Therefore, the first-level register value and the second-level register value of the working clock are both 1. Since Therefore, the remaining register values are all 0, that is, the corresponding target address values are successively 1 zero, several 1s, several 0s. When N = 4, the target address is 0110. When N = 5, the target address is 01100.

[0087] When N = 4, the timing relationship of the pulse signal, the working clock, and the multi-level register values of the working clock is as Figure 4 shown. clk600 represents the working clock signal, clk_d1 represents the first-level register value of the working clock, clk_d2 represents the second-level register value of the working clock, and clk_d3 represents the third-level register value of the working clock.

[0088] If At the decision moment, the working clock, the first-level register value, and the second-level register value of the working clock are all 1, and the subsequent several register values are 0, several 1s. Therefore, the value of the corresponding target address is 3 1s, several 0s, several 1s.

[0089] For example, when N = 6, the timing relationship of the pulse signal, the working clock, and the multi-level register values of the working clock is as Figure 5 shown. clk400 represents the working clock signal, clk_d1 represents the first-level register value of the working clock, clk_d2 represents the second-level register value of the working clock, clk_d3 represents the third-level register value of the working clock, clk_d4 represents the third-level register value of the working clock, and clk_d5 represents the third-level register value of the working clock. The target address is 111000.

[0090] Then, calculate the corresponding target addresses at other phase differences according to the target address at 0 phase difference, specifically including:

[0091] When the phase difference is , circularly shift the target address at 0 phase difference to the left by k bits to obtain the corresponding target address;

[0092] Among them, N represents the multiple of the sampling clock frequency relative to the working clock frequency, and 0 ≤ k < N.

[0093] Since the pulse signal is a signal sampled by the sampling clock, therefore, the phase difference between the pulse signal and the working clock includes N cases, that is, the phase difference is 0,

[0094] When N = 4, the rising edge of the working clock is after the rising edge of the pulse signal In the cycle, the timing relationships of the pulse signal, the working clock, and the multi-stage register values of the working clock are as Figure 6 shown. At this time, the corresponding register value sequence is 1100. When the rising edge of the working clock is after the rising edge of the pulse signal In the cycle, the timing relationships of the pulse signal, the working clock, and the multi-stage register values of the working clock are as Figure 7 shown. At this time, the corresponding register value sequence is 1001.

[0095] Therefore, when the phase is , the target address at 0 phase difference is circularly shifted left by k bits to obtain the target address corresponding to the phase difference of .

[0096] When the distance between the rising edge of the pulse signal and the rising edge of the working clock signal is far, the sampling is more stable. Therefore, when the phase difference is , the two rising edges are the farthest. Therefore, write 1 to the target address in the lookup table that is closest to , and write 0 to the target addresses corresponding to other phase differences.

[0097] For example, when N = 4, the address corresponding to 0 phase difference is 0110. Therefore, store 0 at the 0110 address in the lookup table, the address corresponding to the phase difference is 1100. Therefore, store 0 at the 1100 address in the lookup table, the address corresponding to the phase difference is 1001. Therefore, store 1 at the 1001 address in the lookup table.

[0098] The phase difference includes N cases. Therefore, the phase difference values are stored at the subsequent N addresses, and the lookup table has 2 N addresses. Therefore, 2 N -1 can be stored at other addresses to represent non-phase differences. When 1 is found, output 1. When 0 is found, the lookup table outputs 0. When 2 N -1 is found, output 3.

[0099] The lookup table needs to output 3 values. Therefore, the output bit number of the lookup table unit is 2 bits.

[0100] When the judgment unit determines that the current is not the target phase, it sends a delay signal to the delay circuit to delay the synchronous pulse signal until the target phase is found.

[0101] If there is no next-level channel in the multiplexer of the delay circuit, an error is reported.

[0102] Those skilled in the art can understand that all or part of the processes for implementing the methods of the above embodiments can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. Among them, the computer-readable storage medium is a disk, an optical disc, a read-only memory, a random access memory, etc.

[0103] As described above, the above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A synchronous pulse signal delay adjustment circuit, characterized in that, It includes a delay circuit, a phase detection circuit and a decision unit; The delay circuit is used to delay the input synchronization pulse signal when receiving a delay signal, and input the delayed synchronization pulse signal into the phase detection circuit; The phase detection circuit is used to detect the phase of the delayed synchronization pulse signal and output a sequence corresponding to the current phase; The decision unit is used to judge whether the current phase is the target phase according to the sequence corresponding to the current phase. If so, the delay adjustment of the synchronization pulse signal is completed; otherwise, a delay signal is sent to the delay circuit.

2. The synchronous pulse signal delay adjustment circuit according to claim 1, characterized in that The delay circuit includes a plurality of cascaded delay units and a multiplexer; The input end of the first delay unit among the plurality of cascaded delay units inputs the synchronization pulse signal, and the output end is connected to the next delay unit; the input end of each intermediate stage delay unit is connected to the output end of the previous stage delay unit, and the output end is connected to the input end of the next stage delay unit; the input end of each delay unit is connected to a selection channel; the output end of the last stage delay unit is connected to a selection channel of the multiplexer.

3. The synchronous pulse signal delay adjustment circuit according to claim 2, wherein The number of the delay units is determined according to the working clock of the clock domain where the synchronization pulse signal delay adjustment circuit is located.

4. The synchronous pulse signal delay adjustment circuit according to claim 2, wherein, The number of the delay units is the minimum number that satisfies the following formula: The delay time of each delay unit × the number of delay units > the period of the working clock.

5. The synchronous pulse signal delay adjustment circuit according to claim 1, wherein, The decision unit is a lookup table unit with multiple-bit input and 2-bit output; the output data of the phase detection circuit is used as the lookup address to input into the lookup table unit, and the lookup table unit outputs the data stored at the address as a mark of whether it is the target phase.

6. The synchronous pulse signal delay adjustment circuit according to claim 5, wherein The following method is used to determine the data stored at each address of the lookup table unit: According to the multiple relationship between the sampling clock and the working clock, determine the address when the pulse signal has a 0 phase difference with the working clock as the target address; Calculate the corresponding target addresses for other phase differences according to the target address at the 0 phase difference; Write a 1 to the target address in the lookup table unit that is closest to and write a 0 to the target addresses corresponding to other phase differences. Wherein, N represents the multiple of the sampling clock frequency relative to the working clock frequency.

7. The synchronous pulse signal delay adjustment circuit according to claim 2, wherein The phase detection circuit includes the rising edge detection circuit of the synchronization pulse signal and the clock signal detection circuit; The synchronization pulse signal detection circuit is used to judge the rising edge of the input pulse signal, and generate a decision signal to send to the decision unit when the rising edge of the synchronization pulse signal arrives; The clock signal detection circuit is used to perform multi-stage storage on the working clock of the current clock domain, and send the working clock and each stage storage value of the working clock to the decision unit; The decision unit is used to judge whether the current phase is the target phase according to the sequence corresponding to the current phase when receiving the decision signal.

8. The synchronous pulse signal delay adjustment circuit according to claim 7, wherein The synchronization pulse signal detection circuit includes three cascaded flip-flops, an inversion circuit and an AND gate; The data input end of the first flip-flop of the synchronization pulse signal detection circuit receives the pulse signal; The data input end of the subsequent flip-flop is connected to the output end of the previous flip-flop; The output end of the last flip-flop of the synchronization pulse signal detection circuit is connected to the input end of the inversion circuit; The clock signal input terminal of each flip-flop in the synchronous pulse signal detection circuit is connected to the sampling clock of the current clock domain; The output terminal of the penultimate flip-flop in the synchronous pulse signal detection circuit and the output terminal of the inversion circuit are connected to the input terminal of the AND gate; the output terminal of the AND gate outputs a decision signal.

9. The synchronous pulse signal delay adjustment circuit according to claim 7, characterized in that The clock signal detection circuit includes a plurality of cascaded flip-flops; The data input terminal of the first flip-flop in the clock signal detection circuit is connected to the working clock of the current clock domain; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop; The clock signal input terminal of each flip-flop in the clock signal detection circuit is connected to the sampling clock of the current clock domain; The working clock and the output terminal of each flip-flop in the clock signal detection circuit are connected to the input terminal of the decision unit.

10. The synchronous pulse signal delay adjustment circuit according to claim 9, wherein, The number of flip-flops in the clock signal detection circuit is set according to the multiple of the sampling clock frequency of the current clock domain relative to the working clock frequency.

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