Power supply method and circuit for high-speed parallel port interconnection between large-scale Chiplets

Abstract

The invention discloses a power supply method for high-speed parallel port interconnection between large-scale Chiplets, and the method comprises the steps: in a Chiplet interconnection circuit, a TX end is connected with a plurality of drivers, each driver is connected with a transmission link, and a plurality of transmission links are formed; the number of the transmission links sharing one LDO is calculated through a preset algorithm, and the number and the distribution position of the required LDO are obtained according to the number and the distance of the transmission links, so that each transmission link supplements power supply charges in time. In a system in which a plurality of Chiplets work in parallel, the method can ensure that each Chiplet obtains accurate voltage, performance reduction or faults caused by power supply fluctuation are avoided, and therefore the overall reliability and stability of the system are improved. The LDO in the method is small in size and simple in design, required external elements (such as an inductor and a capacitor) can be effectively reduced, and then the overall size and cost of the system are reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power supply, and particularly relates to a power supply method and circuit for high-speed parallel port interconnection between large-scale Chiplets. Background Art

[0002] There are a large number of parallel transceiver data links in the Chiplet interface. The transmitted data will affect the stability of the system power supply and generate ripples on the power supply. During high-speed data transmission, the quality of the transmitted data is closely related to the stability of the output voltage of the Low-dropout regulator (LDO). The speed of change of the LDO load current will also change at a high speed, which will cause a large amount of extraction of the charge of the power supply. The traditional LDO power supply method cannot achieve such a high bandwidth. If a relatively stable power supply voltage is required, a large decoupling capacitor is needed, which will consume more chip area. Summary of the Invention

[0003] The purpose of the present invention is to provide a power supply method for high-speed parallel port interconnection between large-scale Chiplets, which uses a hybrid LDO method for power supply. It can not only enable each transmission link to timely replenish the power charge, but also reduce the size of the load capacitance of a single LDO, making the layout design of the entire LDO more reasonable.

[0004] To solve the above problems, the technical solution of the present invention is as follows: A power supply method for high-speed parallel port interconnection between large-scale Chiplets, which uses a hybrid LDO power supply method to supply power to the Chiplet interconnection circuit, including the following steps: In the Chiplet interconnection circuit, the TX end is connected to a plurality of drivers, and each driver is connected to a transmission link to form a plurality of transmission links; Calculate the number of transmission links sharing a single LDO using a preset algorithm, and obtain the number and distribution positions of the required LDOs according to the number of transmission links and the distance, so that each transmission link can timely replenish the power charge; Among them, the preset algorithm calculates the relationship between the compensation performance of the LDO and the number of links through the charge conservation formula to accurately control the number of LDO power supply links.

[0005] According to an embodiment of the present invention, a comparator is connected to the output end of the LDO, and the output end of the comparator is connected to a compensation tube; The output voltage of the LDO is detected by the comparator. When the output voltage exceeds the preset range, the compensation tube is triggered to quickly compensate or release charge during the data transmission cycle to ensure the stability of the power supply voltage, and at the same time reduce the value of the decoupling capacitor and save chip area.

[0006] According to an embodiment of the present invention, a dual comparator is used to detect the output voltage of the LDO, which is respectively used to compare the output voltage with the upper limit voltage and the lower limit voltage, so as to realize the rapid compensation or release of charge, ensure the stability of the LDO output voltage, and realize an on-chip LDO.

[0007] According to an embodiment of the present invention, the voltage fluctuation of the LDO output node is suppressed by the cooperative work of a comparator and a compensation transistor, so as to ensure the output data quality and optimize the BER value.

[0008] According to an embodiment of the present invention, the suppression of the voltage fluctuation of the LDO output node by the cooperative work of a comparator and a compensation transistor further includes: The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during data transmission. When the value of VDDQ is lower than the preset lower limit voltage, the comparator outputs a valid bit to control the compensation transistor to adjust the unit charging current to compensate for the lost charge, so as to stabilize VDDQ within one clock cycle.

[0009] According to an embodiment of the present invention, the output terminal of the LDO is connected to the input terminal of a first comparator, and the other input terminal of the first comparator is connected to a first reference voltage, and the first reference voltage is used to indicate the lower limit voltage; the output terminal of the first comparator is connected to a first CTR module, the first CTR module is connected to a first Charge module, and the output of the first Charge module is connected to the output terminal of the LDO; The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during data transmission. When the value of VDDQ is lower than the first reference voltage, the first comparator outputs a valid bit to control the first CTR module to adjust the unit charging current of the first Charge module to compensate for the lost charge, so as to stabilize VDDQ within one clock cycle.

[0010] According to an embodiment of the present invention, the output terminal of the LDO is connected to the input terminal of a second comparator, and the other input terminal of the second comparator is connected to a second reference voltage, and the second reference voltage is used to indicate the upper limit voltage; the output terminal of the second comparator is connected to a second CTR module, the second CTR module is connected to a second Charge module, and the output of the second Charge module is connected to the output terminal of the LDO; The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during data transmission. When the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit to control the second CTR module to adjust the unit charging current of the second Charge module to release the excess charge, so as to stabilize VDDQ within one clock cycle.

[0011] A power supply circuit for high-speed parallel interconnection between large-scale Chiplets includes: The Chiplet interconnection circuit, the TX end of any Chiplet is connected to multiple drivers, and each driver is connected to a transmission link to form multiple transmission links; Multiple LDO modules, the distribution positions calculated by each LDO module according to a preset algorithm supply power to multiple transmission links within the distribution position area, so that each transmission link can replenish power charges in time; The output end of each LDO module is connected to a comparator, and the output end of the comparator is connected to a compensation tube; The comparator is used to detect the output voltage of the LDO. When the output voltage exceeds the preset range, it triggers the compensation tube to quickly compensate or release charges during the data transmission cycle, ensuring the stability of the power supply voltage, and at the same time reducing the value of the decoupling capacitor and saving chip area.

[0012] According to an embodiment of the present invention, the output end of the LDO is connected to the input end of a first comparator, the other input end of the first comparator accesses a first reference voltage, and the first reference voltage is used to indicate the lower limit voltage; the output end of the first comparator is connected to a first CTR module, the first CTR module is connected to a first Charge module, and the output of the first Charge module is connected to the output end of the LDO; The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during data transmission. When the value of VDDQ is lower than the first reference voltage, the first comparator outputs a valid bit, controls the first CTR module to adjust the unit charging current of the first Charge module, and compensates for the lost charges to stabilize VDDQ within one clock cycle.

[0013] According to an embodiment of the present invention, the output end of the LDO is connected to the input end of a second comparator, the other input end of the second comparator accesses a second reference voltage, and the second reference voltage is used to indicate the upper limit voltage; the output end of the second comparator is connected to a second CTR module, the second CTR module is connected to a second Charge module, and the output of the second Charge module is connected to the output end of the LDO; The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during data transmission. When the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit, controls the second CTR module to adjust the unit charging current of the second Charge module, and releases the excess charges to stabilize VDDQ within one clock cycle.

[0014] Due to the adoption of the above technical solutions, the present invention has the following advantages and positive effects compared with the prior art: 1) The power supply method for high-speed parallel interface interconnection between large-scale Chiplets in an embodiment of the present invention. In the Chiplet interconnection circuit, the TX end is connected to multiple drivers, and each driver is connected to a transmission link, forming multiple transmission links. The number of transmission links sharing a single LDO is calculated using a preset algorithm, and based on the number of transmission links and the distance, the required number and distribution positions of the LDOs are obtained, enabling each transmission link to replenish power charges in a timely manner. In a system where multiple Chiplets operate in parallel, this method can ensure that each Chiplet obtains an accurate voltage, avoiding performance degradation or failures caused by power fluctuations, thereby enhancing the overall reliability and stability of the system. For applications such as high-performance computing and AI accelerators, the low-noise characteristics of the LDO are particularly important, helping to maintain the purity of signals and the response speed of the system. The LDOs in this method are small in size and simple in design, which can effectively reduce the required external components (such as inductors, capacitors, etc.), thereby reducing the overall volume and cost of the system. In Chiplet design, since multiple small chips are integrated into a single system, the compactness of the LDO makes it an ideal choice for solving space limitations.

[0015] 2) The power supply method for high-speed parallel interface interconnection between large-scale Chiplets in an embodiment of the present invention. A comparator is connected to the output end of the LDO, and the output end of the comparator is connected to a compensation tube. The output voltage of the LDO is detected by the comparator. When the output voltage exceeds the preset range, the compensation tube is triggered to quickly compensate or release charges during the data transmission cycle, ensuring the stability of the power supply voltage and avoiding the impact of ripples on signal quality. By means of rapid charge compensation, the area and power consumption of the decoupling capacitor are reduced, and the chip power consumption is lowered. Brief Description of the Drawings

[0016] Figure 1 is a flowchart of the power supply method for high-speed parallel interface interconnection between large-scale Chiplets in an embodiment of the present invention; Figure 2 is a schematic diagram of the high-speed parallel interface interconnection circuit between large-scale Chiplets in an embodiment of the present invention; Figure 3 is a schematic diagram of the module for splitting a single LDO shared by multiple transmission links according to the distance in an embodiment of the present invention; Figure 4 is a schematic diagram of the rapid charge compensation circuit in an embodiment of the present invention. Detailed Description of the Embodiment

[0017] The following further elaborates in detail on a power supply method and circuit for high-speed parallel interface interconnection between large-scale Chiplets proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer based on the following description and the claims.

[0018] Chiplet technology decomposes a chip into multiple small chip modules. Each module is independently designed and optimized according to its function, and an appropriate process and power management strategy can be selected to reduce power consumption. Different Chiplet modules can be independently switched and the voltage frequency can be adjusted to avoid power consumption of unused parts and improve energy efficiency. High-speed parallel interface interconnection between Chiplets requires additional communication circuits such as transceivers and routing logic, which will increase power consumption. Power management strategies need to be designed for different Chiplet modules to coordinate power supply and power consumption optimization. Improper design may lead to unreasonable power consumption distribution and power interference, thereby increasing power consumption.

[0019] There are a large number of parallel data transceiver links in the Chiplet interconnection interface. The transmitted data will affect the stability of the system power supply and generate ripples on the power supply. During high-speed data transmission, the quality of the transmitted data is closely related to the stability of the output voltage of the Low-dropout regulator (LDO). The speed of change of the LDO load current will also change at a high speed, which will cause a large amount of charge of the power supply to be extracted. The traditional LDO power supply method cannot achieve such a high bandwidth. If a relatively stable power supply voltage is required, a larger decoupling capacitor is needed, which will consume more chip area.

[0020] In order to improve the stability of the power supply voltage and reduce the area of the decoupling capacitor at the same time, this embodiment uses a hybrid LDO method for power supply. And by adding a comparator and a compensating current tube, the charge can be quickly compensated or released. It balances the requirements of LDO in terms of efficiency, stability and area. While meeting the requirements of low voltage drop and high-precision voltage regulation, by switching to the switching voltage regulation mode when the load is high, the overall power consumption of the system is reduced, the current efficiency is improved, and the quality of the output data is optimized.

[0021] Specifically, please refer to Figure 1 This embodiment provides a power supply method for high-speed parallel interface interconnection between large-scale Chiplets. The hybrid LDO power supply method is used to supply power to the Chiplet interconnection circuit, including the following steps: In the Chiplet interconnection circuit, the TX end is connected to multiple drivers, and each driver is connected to a transmission link, forming multiple transmission links; Calculate the number of transmission links sharing a single LDO with a preset algorithm, and based on the number of transmission links and the distance, obtain the number and distribution positions of the required LDOs, so that each transmission link can replenish power charges in a timely manner.

[0022] By this method, the LDOs are reasonably arranged. Multiple transmission links share a single LDO. The module is split according to the distance, so that the LDO is close to the load, reducing the transmission distance and voltage drop, and improving the power supply efficiency, stability and layout compactness.

[0023] Split the LDO into multiple locations to avoid heat concentration, reduce the chip temperature, improve thermal performance and reliability. Or reasonably layout the LDO so that it is close to the heat dissipation structure or area to enhance the heat dissipation effect and ensure the stable operation of the chip under high power consumption.

[0024] Multiple LDOs can be customized to meet the power consumption and voltage requirements of different Chiplets, support multiple power specifications, and enhance design flexibility. Adjust the number and layout of LDOs according to requirements to meet the needs of different application scenarios, facilitating chip design upgrades and expansions.

[0025] Among them, the preset algorithm calculates the relationship between the compensation performance of the LDO and the number of links through the charge conservation formula to precisely control the number of power supply links of the LDO. For example, the average current extracted from the change of data in a single link is , the capacitance value after the LDO is C, and the change in the output voltage of the LDO is , and the total amount of charge that the LDO can compensate within the specified time t is Q. According to the charge conservation formula, the following results are obtained: Since the average current extracted by each link is determined after the design is completed, only by relying on the compensation performance of the designed LDO can the number of power supply links of the LDO be precisely controlled.

[0026] Example: When the average current extracted by a single link at one time is 1 mA and the continuous extraction time is 100 ps, the lost charge amount is , and the charge amount that the LDO can compensate within 1 UI time is (the unit is the same as above), then one LDO can drive 5 to 6 links.

[0027] Specifically, please refer to Figure 2 , the performance of the high-speed Chiplet interconnection circuit is not only related to its own circuit design, but also has a great relationship with the stability of the power supply. Since the output at the TX end is a driver, the output current of the driver is large, and the current will change synchronously and rapidly with the data code stream, and it is necessary to continuously draw current from the power supply. If the LDO cannot timely replenish the charge to its output node, this will cause the power supply voltage at the driver end to drop, and the power supply voltage at the driver end will affect the quality of the output signal at the TX end. The current in each transmission line will generate a transient peak current when the data jumps. Since the interconnection circuit is located at the edge of the Chiplet and multiple transmission links need to be integrated in each Chiplet, the area requirement for the Chiplet interconnection circuit is very high. When designing the power supply of the Chiplet interconnection circuit, multiple transmission links can share a single LDO and optimize the design of the LDO to save the area of the decoupling capacitors required, such asFigure 2 As shown, 20 transmission links share a single LDO for power supply. However, when too many links are shared, due to the excessive distance between the transmission links, it is impossible to timely replenish the changed charge to the transmission links far from the LDO. Therefore, module splitting can be carried out. For example, every 5 transmission links share an LDO, and so on, as Figure 3 shown. By selecting an appropriate number of transmission links sharing the LDO, not only can each transmission link timely replenish the power charge, but also the load capacitance of a single LDO can be reduced, making the layout design of the entire LDO more reasonable.

[0028] Furthermore, a comparator is connected to the output terminal of the LDO, and the output terminal of the comparator is connected to a compensation tube; the output voltage of the LDO is detected by the comparator. When the output voltage exceeds the preset range, the compensation tube is triggered to quickly compensate or release charge during the data transmission cycle, ensuring the stability of the power supply voltage and simultaneously reducing the value of the decoupling capacitor, saving chip area.

[0029] Preferably, a dual comparator is used to detect the output voltage of the LDO, which is respectively used to compare the output voltage with the upper limit voltage and the lower limit voltage, so as to achieve rapid compensation or release of charge, ensure the stability of the LDO output voltage, and realize an on-chip LDO.

[0030] Specifically, at the output node of the LDO, since the load current will change, it will cause the voltage at the LDO output node to drop or overshoot. To suppress overshoot and voltage drop, 2 comparators are added in this case, which are respectively used to detect the upper limit voltage and the lower limit voltage. When the LDO output voltage is higher than the upper preset threshold voltage VH or lower than the lower preset threshold voltage VL, it will cause the output voltage of the comparator to change. Then, the output of the comparator is applied to the gate of a compensation tube. Since the extraction of charge changes at the rate of data, the result of each comparison only needs to be able to replenish or release charge within one cycle, then the stability of the power supply voltage can be ensured and the impact on the output data is small. This method can greatly reduce the value of the required decoupling capacitor and save chip area.

[0031] The voltage fluctuation at the LDO output node is suppressed through the collaborative work of the comparator and the compensation tube, ensuring the quality of the output data and optimizing the BER value. Please refer to Figure 4 As shown in, the output terminal of the LDO is connected to the input terminal of the first comparator (CMP1), and the other input terminal of the first comparator is connected to the first reference voltage (VREF1), which is used to indicate the lower limit voltage; the output terminal of the first comparator is connected to the first CTR module, the first CTR module is connected to the first Charge module, and the output of the first Charge module is connected to the output terminal of the LDO.

[0032] The output terminal of the LDO is connected to the input terminal of the second comparator (CMP2). The other input terminal of the second comparator is connected to a second reference voltage (VREF2), which is used to indicate the upper limit voltage. The output terminal of the second comparator is connected to a second CTR module, the second CTR module is connected to a second Charge module, and the output of the second Charge module is connected to the output terminal of the LDO.

[0033] In the figure, VDDQ is the output terminal power supply that needs to be stabilized.

[0034] The goal of power supply compensation is to ensure that during the 0-1 transition of data, the lost charge can be compensated within one clock cycle, so as not to affect the transmission of the next 0-1 data.

[0035] Cooperative compensation mechanism: First, the LDO provides an initial value to VDDQ. Data transmission will cause the voltage of VDDQ to change. When VDDQ is lower than the voltage value VREF1, the comparator will output a valid bit, thereby controlling the subsequent Charge module and CTR module. The CTR module is a module used to adjust the magnitude of the unit charging current in the Charge module. The CTR module is an adjustable module designed for testing.

[0036] That is, the LDO outputs an initial voltage VDDQ. The value of VDDQ changes during data transmission. When the value of VDDQ is lower than the first reference voltage, the first comparator outputs a valid bit, controlling the first CTR module to adjust the unit charging current of the first Charge module to compensate for the lost charge and stabilize VDDQ within one clock cycle.

[0037] Or the LDO outputs an initial voltage VDDQ. The value of VDDQ changes during data transmission. When the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit, controlling the second CTR module to adjust the unit charging current of the second Charge module to release the excess charge and stabilize VDDQ within one clock cycle.

[0038] By quickly compensating for the lost charge, the voltage can be quickly stabilized back to the normal VDDQ within one clock cycle, so as not to affect the transmission of the next 0-1 transition data. The quality of the output data is closely related to the power supply voltage of the Driver, which will directly affect the eye height of the output data eye diagram and will also have a certain impact on the rising and falling edges of the data. As long as the voltage is stabilized within one cycle, the eye diagram and data quality can be optimized, and the BER value can also be optimized.

[0039] If the compensation tube is not added, the rate of the LDO cannot compensate for the lost charge within one clock cycle. It takes a certain number of cycles to compensate for the charge, which will affect the eye diagram quality of the output data and deteriorate the BER.

[0040] In this embodiment, a comparator and a compensation current tube are added to the LDO, which can quickly detect the output voltage fluctuation and compensate or release the charge, maintain the power supply stability, and avoid the ripple from affecting the signal quality. Through fast charge compensation, the area and power consumption of the decoupling capacitor are reduced, and the chip power consumption is lowered. A stable voltage is provided for each Chiplet to prevent performance degradation or faults caused by power supply fluctuations, improving the system reliability. The power supply ripple and noise are reduced, enhancing the system's anti-interference ability and ensuring stable operation. The power supply of the TX end driver is guaranteed to be stable, reducing the influence of current fluctuation on the output signal and improving the signal integrity. Through fast charge compensation, the interference of power supply voltage fluctuation on signal transmission is reduced, the bit error rate (BER) is lowered, and the data transmission reliability is improved.

[0041] In summary, the power supply method for high-speed parallel interconnection between large-scale Chiplets can flexibly provide stable voltage for different Chiplets, supporting various power supply specifications and low-voltage design requirements. Compared with the traditional LDO scheme, this method can more precisely meet the power supply requirements of each Chiplet, thereby improving the power efficiency and performance of the entire system. The design has strong flexibility and can be customized according to different application requirements; manufacturers can design LDOs with different specifications according to different Chiplet application scenarios, further broadening the product line and meeting the needs of different industries and customers. This customization ability has great market appeal in the chip industry and can help enterprises occupy more market shares. With the continuous progress of semiconductor processes, chip design is gradually trending towards miniaturization and high integration, and the high-precision power control characteristics of LDOs are in line with the miniaturization design. Using this method to supply power to Chiplets can not only meet the requirements of advanced process technologies, make the control module faster, but also reduce the manufacturing cost through optimized design and manufacturing processes, enhancing the market competitiveness of products.

[0042] Based on the same concept, the present invention also provides a power supply circuit for high-speed parallel interconnection between large-scale Chiplets. Please refer to Figures 2 - 4 , the circuit includes: Chiplet interconnection circuit, the TX end of any Chiplet is connected to multiple drivers, and each driver is connected to a transmission link, forming multiple transmission links; Multiple LDO modules, which are distributed at the positions calculated according to a preset algorithm to supply power to the multiple transmission links within the area of the distribution positions, so that each transmission link can timely replenish the power charge; The output terminal of each LDO module is connected to a comparator, and the output terminal of the comparator is connected to a compensation transistor; the comparator is used to detect the output voltage of the LDO. When the output voltage exceeds the preset range, it triggers the compensation transistor to quickly compensate or release charges during the data transmission cycle, ensuring the stability of the power supply voltage and at the same time reducing the value of the decoupling capacitor to save chip area.

[0043] Among them, the output terminal of the LDO is connected to the input terminal of the first comparator, the other input terminal of the first comparator is connected to a first reference voltage, and the first reference voltage is used to indicate the lower limit voltage; the output terminal of the first comparator is connected to the first CTR module, the first CTR module is connected to the first Charge module, and the output of the first Charge module is connected to the output terminal of the LDO; The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during data transmission. When the value of VDDQ is lower than the first reference voltage, the first comparator outputs a valid bit to control the first CTR module to adjust the unit charging current of the first Charge module to compensate for the lost charges and stabilize VDDQ within one clock cycle.

[0044] The output terminal of the LDO is connected to the input terminal of the second comparator, the other input terminal of the second comparator is connected to a second reference voltage, and the second reference voltage is used to indicate the upper limit voltage; the output terminal of the second comparator is connected to the second CTR module, the second CTR module is connected to the second Charge module, and the output of the second Charge module is connected to the output terminal of the LDO; The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during data transmission. When the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit to control the second CTR module to adjust the unit charging current of the second Charge module to release the excess charges and stabilize VDDQ within one clock cycle.

[0045] This circuit can implement the above-mentioned power supply method for high-speed parallel port interconnection between large-scale Chiplets, providing stable voltage for different Chiplets.

[0046] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, provided that these changes fall within the scope of the claims of the present invention and its equivalent technologies, they still fall within the protection scope of the present invention.

Claims

1. A power supply method for high-speed parallel interface interconnection between large-scale Chiplets, characterized in that Power the Chiplet interconnection circuit using a hybrid LDO power supply method, including the following steps: In the Chiplet interconnection circuit, the TX end is connected to multiple drivers, and each driver is connected to a transmission link, forming multiple transmission links; Calculate the number of transmission links sharing a single LDO using a preset algorithm, and based on the number of transmission links and the distance, obtain the required number and distribution positions of the LDOs, so that each transmission link can replenish power charges in a timely manner; Among them, the preset algorithm calculates the relationship between the compensation performance of the LDO and the number of links through the charge conservation formula to precisely control the number of LDO power supply links.

2. The power supply method for high-speed parallel interface interconnection between large-scale Chiplets according to claim 1, wherein Connect a comparator to the output end of the LDO, and the output end of the comparator is connected to a compensation tube; Detect the output voltage of the LDO through the comparator. When the output voltage exceeds the preset range, trigger the compensation tube to quickly compensate or release charges during the data transmission cycle to ensure the stability of the power supply voltage, and at the same time reduce the value of the decoupling capacitor to save chip area.

3. The power supply method for high-speed parallel interface interconnection between large-scale Chiplets according to claim 2, characterized in that, Use a dual comparator to detect the output voltage of the LDO, which is respectively used to compare the output voltage with the upper limit voltage and the lower limit voltage, so as to achieve rapid compensation or release of charges, ensure the stability of the LDO output voltage, and implement an on-chip LDO.

4. The power supply method for high-speed parallel interface interconnection between large-scale Chiplets according to claim 2, characterized in that, Suppress the voltage fluctuation of the LDO output node through the collaborative work of the comparator and the compensation tube to ensure the output data quality and optimize the BER value.

5. The power supply method for high-speed parallel interface interconnection between large-scale Chiplets according to claim 4, characterized in that, The suppression of the voltage fluctuation of the LDO output node through the collaborative work of the comparator and the compensation tube further includes: The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during the data transmission. When the value of VDDQ is lower than the preset lower limit voltage, the comparator outputs a valid bit to control the compensation tube to adjust the unit charging current to compensate for the lost charges and stabilize VDDQ within one clock cycle.

6. The power supply method for high-speed parallel interface interconnection between large-scale Chiplets according to claim 3, wherein The output end of the LDO is connected to the input end of the first comparator, and the other input end of the first comparator is connected to a first reference voltage, and the first reference voltage is used to indicate the lower limit voltage; the output end of the first comparator is connected to a first CTR module, the first CTR module is connected to a first Charge module, and the output of the first Charge module is connected to the output end of the LDO; The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during the data transmission. When the value of VDDQ is lower than the first reference voltage, the first comparator outputs a valid bit to control the first CTR module to adjust the unit charging current of the first Charge module to compensate for the lost charges and stabilize VDDQ within one clock cycle.

7. The power supply method for high-speed parallel interface interconnection between large-scale Chiplets according to claim 3, characterized in that, The output end of the LDO is connected to the input end of the second comparator, and the other input end of the second comparator is connected to a second reference voltage, and the second reference voltage is used to indicate the upper limit voltage; the output end of the second comparator is connected to a second CTR module, the second CTR module is connected to a second Charge module, and the output of the second Charge module is connected to the output end of the LDO; The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during data transmission. When the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit to control the second CTR module to adjust the unit charging current of the second Charge module and release the excess charge to stabilize VDDQ within one clock cycle.

8. A power supply circuit for high-speed parallel interface interconnection between large-scale Chiplets, characterized in that, Including: A Chiplet interconnection circuit, where the TX end of any Chiplet is connected to multiple drivers, and each driver is connected to a transmission link to form multiple transmission links; Multiple LDO modules, which are distributed at positions calculated according to a preset algorithm to supply power to the multiple transmission links within the distribution position area, so that each transmission link can replenish power charges in a timely manner; The output end of each LDO module is connected to a comparator, and the output end of the comparator is connected to a compensation tube; The comparator is used to detect the output voltage of the LDO. When the output voltage exceeds the preset range, it triggers the compensation tube to quickly compensate or release charges during the data transmission cycle to ensure the stability of the power supply voltage and at the same time reduce the value of the decoupling capacitor to save chip area.

9. The power supply circuit for high-speed parallel interface interconnection between large-scale Chiplets according to claim 8, wherein, The output end of the LDO is connected to the input end of the first comparator, and the other input end of the first comparator is connected to a first reference voltage, which is used to indicate the lower limit voltage; the output end of the first comparator is connected to the first CTR module, the first CTR module is connected to the first Charge module, and the output of the first Charge module is connected to the output end of the LDO; The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during data transmission. When the value of VDDQ is lower than the first reference voltage, the first comparator outputs a valid bit to control the first CTR module to adjust the unit charging current of the first Charge module and compensate for the lost charge to stabilize VDDQ within one clock cycle.

10. The power supply method for high-speed parallel interface interconnection between large-scale Chiplets according to claim 8, wherein The output end of the LDO is connected to the input end of the second comparator, and the other input end of the second comparator is connected to a second reference voltage, which is used to indicate the upper limit voltage; the output end of the second comparator is connected to the second CTR module, the second CTR module is connected to the second Charge module, and the output of the second Charge module is connected to the output end of the LDO; The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes during data transmission. When the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit to control the second CTR module to adjust the unit charging current of the second Charge module and release the excess charge to stabilize VDDQ within one clock cycle.

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