Direct current offset correction circuit and method of single current source

Abstract

The invention provides a direct current offset correction circuit and method of a single current source. The direct current offset correction circuit comprises a numerical control multi-path current mirror circuit, a comparison circuit, an intermediate frequency link and a digital logic circuit, the numerical control multi-path current mirror circuit comprises a path of reference current source; the comparison circuit detects the in-phase output voltage and the inverted output voltage of the intermediate-frequency link; when the in-phase output voltage is greater than the inverted output voltage, the output voltage is sent to the digital logic circuit; the digital logic circuit controls the sign bit to be a high level according to the output voltage, so that the numerical control multi-path current mirror circuit injects current into the inverted input end, and the inverted output voltage is increased; when the in-phase output voltage is still greater than the inverted-phase output voltage, changing the size of the injected current by adopting a dichotomy according to the high level output by the comparison circuit until the in-phase output voltage is equal to the inverted-phase output voltage, and obtaining a corresponding code word; the circuit area is optimized, the current direction and size control is completed through one reference current source, the precision is not affected, and the control circuit is simplified.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a DC offset correction circuit and method for a single current source. Background Art

[0002] In a zero-IF transceiver architecture, there is a large DC offset in the IF circuit. The offset voltage after high-gain amplification by the IF circuit will cause the subsequent circuit to deviate from the normal DC operating point, thus seriously affecting the function and performance of the circuit. In addition, the mismatch caused by the circuit structure and manufacturing process will also result in a differential offset voltage, which cannot be eliminated by the common-mode feedback circuit. Therefore, generally, a DCOC (DC Offset Cancellation) is required to suppress it.

[0003] Referring to Figure 1 , in the IF link, two current sources are connected to each of the P terminal and the N terminal, and the magnitude of the current value is controlled by the code word sent by the digital logic module; one current source is responsible for injecting current into the link when the detected voltage is low, and the other is for extracting current from the link when the detected voltage is high. While the current source extracts and injects current, the voltages at the P and N terminals are continuously detected through the digital logic circuit and the code is searched to find the balance value, so as to achieve the purpose of eliminating the DC offset of the link.

[0004] Generally, the IF link has multiple stages. If DCOC correction is required for each stage, two current sources are connected to each end of the differential link, and a total of four current sources are required for one stage. Moreover, for each end, the current extraction and injection cannot be carried out simultaneously, that is, only two current sources are in the working state at the same time, and the other two current sources are idle. If n stages need to be corrected, the total number of current sources required is n*4, and the number of idle current sources is n*2. This causes a large waste of area, increases the wiring difficulty, and deteriorates the matching between current source units. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a DC offset correction circuit and method for a single current source, which greatly optimizes the circuit area. The direction and magnitude of the current can be controlled by a single reference current source, and the accuracy is not affected, which greatly simplifies the control logic circuit.

[0006] In a first aspect, an embodiment of the present invention provides a DC offset correction circuit for a single current source, where the DC offset correction circuit includes: a numerically controlled multi-path current mirror circuit, a comparison circuit, an IF link, and a digital logic circuit; wherein, the numerically controlled multi-path current mirror circuit includes a path of reference current source;

[0007] The numerically controlled multi-path current mirror circuit, the IF link, and the digital logic circuit are respectively connected to the comparison circuit, and the digital logic circuit is connected to the numerically controlled multi-path current mirror circuit;

[0008] The comparison circuit is configured to detect the in-phase output voltage and the quadrature output voltage of the intermediate frequency link, and compare the in-phase output voltage with the quadrature output voltage; when the in-phase output voltage is greater than the quadrature output voltage, the output voltage is sent to the digital logic circuit;

[0009] The digital logic circuit is configured to control the sign bit to be at a high level according to the output voltage, so that the numerically controlled multi-path current mirror circuit injects current into the inverting input terminal, and the quadrature output voltage increases; when the in-phase output voltage is still greater than the quadrature output voltage, the magnitude of the injected current is changed by the binary search method according to the high level output by the comparison circuit until the in-phase output voltage is equal to the quadrature output voltage, and the corresponding codeword is obtained.

[0010] Further, the numerically controlled multi-path current mirror circuit includes a reference current source, a multi-path current mirror unit, a plurality of switches, and a low-pass filter circuit; wherein, the low-pass filter circuit includes a resistor and a capacitor, and the plurality of switches include a fast control switch, a first switch, a second switch, and a third switch.

[0011] Further, each path of the current mirror unit corresponds to a current source with a binary proportional relationship; each path of the current source mirrors and replicates the current from the reference current source according to a proportional relationship through a bias voltage; each path of the current source is controlled by a corresponding switch.

[0012] Further, the low-pass filter circuit is configured to filter out high-frequency noise.

[0013] Further, the fast control switch is connected in parallel with the resistor; in the calibration mode, the fast control switch is closed to short-circuit the resistor.

[0014] Further, each path of the multi-path current mirror unit is respectively connected to one end of the first switch, the other end of the first switch is respectively connected to one end of the second switch and one end of the third switch, the other end of the second switch is connected to the inverting input terminal, and the other end of the third switch is connected to the in-phase input terminal.

[0015] Further, the reference current source is generated by an external reference current, and the magnitude of the current of the reference current source is an integer multiple of the minimum current.

[0016] In a second aspect, an embodiment of the present invention provides a direct current offset correction method for a single current source, which is applied to the direct current offset correction circuit for a single current source as described above. The direct current offset correction circuit includes a numerically controlled multi-path current mirror circuit, a comparison circuit, an intermediate frequency link, and a digital logic circuit; wherein, the numerically controlled multi-path current mirror circuit includes a path of reference current source; the method includes:

[0017] The comparison circuit detects the in-phase output voltage and the quadrature output voltage of the intermediate frequency link;

[0018] The comparison circuit compares the in-phase output voltage with the quadrature output voltage;

[0019] When the in-phase output voltage is greater than the quadrature output voltage, the comparison circuit sends the output voltage to the digital logic circuit;

[0020] The digital logic circuit controls the sign bit to be high according to the output voltage, so that the numerically controlled multi-path current mirror circuit injects current into the inverting input terminal, and the quadrature output voltage increases;

[0021] When the in-phase output voltage is still greater than the quadrature output voltage, the digital logic circuit changes the magnitude of the injected current by the dichotomy method according to the high level output by the comparison circuit until the in-phase output voltage is equal to the quadrature output voltage, and the corresponding codeword is obtained.

[0022] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor. A computer program that can run on the processor is stored on the memory. When the processor executes the computer program, the method described above is implemented.

[0023] In a fourth aspect, an embodiment of the present invention provides a computer-readable medium having non-volatile program code executable by a processor. The program code causes the processor to execute the method described above.

[0024] An embodiment of the present invention provides a DC offset correction circuit and method with a single current source. The DC offset correction circuit includes a numerically controlled multi-path current mirror circuit, a comparison circuit, an intermediate frequency link, and a digital logic circuit. Among them, the numerically controlled multi-path current mirror circuit includes a reference current source. The numerically controlled multi-path current mirror circuit, the intermediate frequency link, and the digital logic circuit are respectively connected to the comparison circuit, and the digital logic circuit is connected to the numerically controlled multi-path current mirror circuit. The comparison circuit is used to detect the in-phase output voltage and the quadrature output voltage of the intermediate frequency link, and compare the in-phase output voltage with the quadrature output voltage. When the in-phase output voltage is greater than the quadrature output voltage, the output voltage is sent to the digital logic circuit. The digital logic circuit is used to control the sign bit to be high according to the output voltage, so that the numerically controlled multi-path current mirror circuit injects current into the inverting input terminal, and the quadrature output voltage increases. When the in-phase output voltage is still greater than the quadrature output voltage, the magnitude of the injected current is changed by the dichotomy method according to the high level output by the comparison circuit until the in-phase output voltage is equal to the quadrature output voltage, and the corresponding codeword is obtained. The circuit area is greatly optimized. The direction and magnitude of the current can be controlled by a single reference current source, and the accuracy is not affected. The control logic circuit is greatly simplified.

[0025] Other features and advantages of the present invention will be set forth in the following description, and in part will be obvious from the description, or may be learned by practice of the present invention. The objectives and other advantages of the present invention are realized and attained by the structure particularly pointed out in the specification, claims, and drawings.

[0026] In order to make the above objectives, features, and advantages of the present invention more comprehensible, the following presents preferred embodiments in conjunction with the accompanying drawings and provides a detailed description as follows. Description of the Drawings

[0027] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0028] Figure 1 Schematic diagram of the 9-bit DCOC circuit structure for the prior art;

[0029] Figure 2 Schematic diagram of the DC offset correction circuit with a single current source provided in the first embodiment of the present invention;

[0030] Figure 3 Schematic diagram of another DC offset correction circuit structure with a single current source provided in the first embodiment of the present invention;

[0031] Figure 4 Flowchart of the DC offset correction method with a single current source provided in the second embodiment of the present invention.

[0032] Reference numerals:

[0033] 1 - Numerically controlled multi-channel current mirror circuit; 2 - Comparison circuit; 3 - Intermediate frequency link; 4 - Digital logic circuit. Detailed Embodiments

[0034] In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions of the present invention in conjunction with the drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0035] Refer to Figure 1, the 9-bit DCOC circuit includes two reference current sources CS1 and CS2, a multi-channel current mirror unit module with switch control (P_SOURCE module, N_SOURCE module, P_SINK module, N_SINK module), a low-pass filter network (composed of Rn and Cn), fast control switches S1 and S2, and switches S3 to S6 for controlling the current directions at the P end and N end, etc.

[0036] The reference current source CS1 (CS2) is generated by the SINK (SOURCE) current provided externally, and the current magnitude is I; the P_SOURCE (P_SINK) and N_SOURCE (N_SINK) modules are each composed of 8 current mirror units, and are connected to the reference current source CS1 (CS2) through the bias signals VBP (VBN), and copy the current from CS1 (CS2) according to a certain ratio (1:2:4:8:16:32:64:128).

[0037] The current mirror units in the P_SOURCE (P_SINK) and N_SOURCE (N_SINK) modules are connected in series with switch control, and the on and off of the corresponding branch currents are controlled through the control signal ctl<7:0> (or the inverted signal of ctl<7:0>).

[0038] Among them, each of the N_SOURCE and P_SINK modules has a fixed minimum current unit I, which has no switch control and is always in the open state, so that the DCOC output differential current shows strict monotonicity with the change of the codeword (because monotonicity is the premise for the digital logic module to optimize by the dichotomy method). If this branch is not added, when the codeword changes from 255 to 256, the DCOC output differential current is 0, and it does not have monotonicity.

[0039] By adding this fixed current I, when the codeword changes from 255 to 256, the DCOC output differential current changes by one LSB, which is a perfect monotonic change; switches S3 and S4 (S5 and S6) are used to control the current drawing and injection directions at the P end (N end), and are realized through the control signal ctl<8> of the highest bit: when ctl<8> is at a low level, P_SINK and N_SOURCE are opened, and when ctl<8> is at a high level, P_SOURCE and N_SINK are opened, so the absolute values of the currents flowing in and out at the P end and N end are equal; in addition, RC filter circuits are added to the bias signals VBP and VBN of the current mirror (Rp and Cp are included in the VBP path, and Rn and Cn are included in the VBN path), which can effectively reduce the noise during the operation of the DCOC; switches S1 and S2 are fast control switches, which bypass Rp and Rn during DCOC calibration, so that the voltages at both ends of the resistors Rp and Rn are quickly established, and the response speed of the DCOC is improved.

[0040] This current compensation type DCOC circuit calibrates the DC voltage of the differential circuit by using the pumping current method. The comparator connected to the differential terminal outputs the comparison result to the digital module, and then the optimal codeword is searched by the dichotomy method in the digital domain, so as to realize the function of eliminating the DC Offset of the circuit.

[0041] However, Figure 1 The intermediate frequency link in [reference] generally has multiple stages and a relatively complex structure. If DCOC correction is required for each stage, two current sources are connected to each end of the differential link, and a total of four current sources are required for one stage. Moreover, for each end, the extraction current and the pumping current cannot be carried out simultaneously, that is, only two current sources are in the working state at the same time, and the other two current sources are idle.

[0042] If n stages need to be corrected, the total number of current sources required is n * 4, and the number of idle current sources is n * 2, which will cause a large area waste, increase the wiring difficulty, and deteriorate the matching between current source units.

[0043] The circuit structure of the present application is relatively simple. This circuit only needs to use one reference current source to complete the control of the direction and magnitude of the current, and the accuracy is not affected, and the control logic circuit is also greatly simplified.

[0044] For the convenience of understanding this embodiment, the embodiments of the present invention will be introduced in detail below.

[0045] Embodiment 1:

[0046] Figure 2 It is a schematic diagram of a single current source DC offset correction circuit provided by Embodiment 1 of the present invention.

[0047] Referring to Figure 2 , the DC offset correction circuit includes: a numerically controlled multi-channel current mirror circuit 1, a comparison circuit (cmp) 2, an intermediate frequency link (amp) 3, and a digital logic circuit (digital) 4; wherein, the numerically controlled multi-channel current mirror circuit 1 includes one reference current source P_bias;

[0048] The numerically controlled multi-channel current mirror circuit 1, the intermediate frequency link 3, and the digital logic circuit 4 are respectively connected to the comparison circuit 2, and the digital logic circuit 4 is connected to the numerically controlled multi-channel current mirror circuit 1;

[0049] The comparison circuit 2 is used to detect the in-phase output voltage and the anti-phase output voltage of the intermediate frequency link 3, and compare the in-phase output voltage with the anti-phase output voltage; when the in-phase output voltage is greater than the anti-phase output voltage, the output voltage is sent to the digital logic circuit 4;

[0050] The digital logic circuit 4 is used to control the sign bit to be at a high level according to the output voltage, so that the numerically controlled multi-channel current mirror circuit 1 injects current into the inverting input terminal, and the inverting output voltage increases; when the non-inverting output voltage is still greater than the inverting output voltage, the magnitude of the injected current is changed by the binary method according to the high level output by the comparison circuit 2 until the non-inverting output voltage is equal to the inverting output voltage, and the corresponding codeword is obtained.

[0051] Here, in this application, the injection of current into the non-inverting input terminal (vip terminal) and the inverting input terminal (vin terminal) is changed to be controlled by switches. The most significant bit code<7> and its inverted signal code_b<7> control the on / off of switches S2 and S3, and thus control whether the output current is injected into the non-inverting input terminal (vip terminal) or the inverting input terminal (vin terminal). The first switch S1 is used as the total output current switch and cuts off the current when the circuit is disabled.

[0052] Specifically, the comparison circuit 2 detects the non-inverting output voltage and the inverting output voltage of the intermediate frequency link 3; when the non-inverting output voltage is greater than the inverting output voltage, the output voltage vout is sent to the digital logic circuit 4; the digital logic circuit 4 controls the sign bit (code<7>) to be at a high level, the second switch S2 is turned on, and P_source injects current into the inverting input terminal (vin terminal), and the inverting output voltage rises.

[0053] After the inverting output voltage rises, when the non-inverting output voltage is still greater than the inverting output voltage, the comparison circuit 2 outputs a high level to the digital logic circuit 4, and the digital logic circuit 4 changes code<6:0> according to the binary method, thereby changing the magnitude of the injected current until the codeword where vip is just less than vin is found. At this time, the non-inverting output voltage (vip) ≈ the inverting output voltage (vin), achieving the purpose of correcting the DC offset.

[0054] Further, the numerically controlled multi-channel current mirror circuit 1 includes a reference current source, a multi-channel current mirror unit P_source with switch control, multiple switches, and a low-pass filter circuit; wherein, the low-pass filter circuit includes a resistor Rp and a capacitor Cp, and the multiple switches include a fast control switch S0, a first switch S1, a second switch S2, and a third switch S3.

[0055] Further, each current mirror unit corresponds to a current source with a binary proportional relationship; each current source copies the current proportionally from the reference current source through the bias voltage; each current source is controlled by the corresponding switch.

[0056] Specifically, refer to Figure 3, the multi-channel current mirror unit P_source includes multi-channel current sources with a binary ratio relationship (7 channels in this circuit) (64I, 32I, 16I, 8I, 4I, 2I, I). These current sources mirror and copy the current from the reference current source P_bias through the bias voltage VBP in proportion. The switches of the multi-channel current sources are controlled by code<6:0>. For example, the first current source is controlled by switch code0, the second current source is controlled by switch code1, the third current source is controlled by switch code2, and so on.

[0057] Furthermore, a low-pass filter circuit is used to filter out high-frequency noise.

[0058] An RC, Rp, and Cp are added to the bias voltage to form an RC low-pass filter circuit, whose function is to filter out high-frequency noise.

[0059] Furthermore, the fast control switch S0 is connected in parallel with the resistor Rp; in the calibration mode, the fast control switch is closed to short-circuit the resistor.

[0060] Specifically, when closed in the calibration mode, it short-circuits the resistor Rp to quickly establish the voltage across the resistor Rp and improve the response speed of the circuit. S0 is composed of complementary switches and can cancel channel charge injection.

[0061] Furthermore, the multi-channel current mirror units are respectively connected to one end of the first switch. The other end of the first switch is respectively connected to one end of the second switch and one end of the third switch. The other end of the second switch is connected to the inverting input terminal, and the other end of the third switch is connected to the non-inverting input terminal.

[0062] Furthermore, the reference current source P_bias is generated by an external reference current, and the current magnitude of the reference current source is an integer multiple kI of the minimum current I.

[0063] Embodiment 2:

[0064] Figure 4 This is the flowchart of the DC offset correction method for a single current source provided by the second embodiment of the present invention.

[0065] Refer to Figure 4 , this method is applied to the DC offset correction circuit of a single current source as described above. The DC offset correction circuit includes a numerically controlled multi-channel current mirror circuit, a comparison circuit, an intermediate frequency link, and a digital logic circuit; among them, the numerically controlled multi-channel current mirror circuit includes one reference current source; this method includes the following steps:

[0066] Step S101, the comparison circuit detects the in-phase output voltage and the anti-phase output voltage of the intermediate frequency link;

[0067] Step S102, the comparison circuit compares the in-phase output voltage with the anti-phase output voltage;

[0068] In step S103, when the in-phase output voltage is greater than the anti-phase output voltage, the comparison circuit sends the output voltage to the digital logic circuit;

[0069] In step S104, the digital logic circuit controls the sign bit to be at a high level according to the output voltage, so that the numerically controlled multi-current mirror circuit injects current into the inverting input terminal, and the inverting output voltage increases;

[0070] In step S105, when the in-phase output voltage is still greater than the anti-phase output voltage, the digital logic circuit uses the binary method to change the magnitude of the injected current according to the high level output by the comparison circuit until the in-phase output voltage is equal to the anti-phase output voltage, and the corresponding codeword is obtained.

[0071] An embodiment of the present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the steps of the DC offset correction method of the single current source provided in the above embodiment are implemented.

[0072] An embodiment of the present invention also provides a computer-readable medium having non-volatile program code executable by a processor. A computer program is stored on the computer-readable medium. When the computer program is run by the processor, the steps of the DC offset correction method of the single current source in the above embodiment are executed.

[0073] The computer program product provided by the embodiment of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method described in the foregoing method embodiment. For specific implementation, reference can be made to the method embodiment, which will not be elaborated here.

[0074] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems and devices described above can refer to the corresponding processes in the foregoing method embodiments, which will not be elaborated here.

[0075] In addition, in the description of the embodiments of the present invention, unless otherwise clearly defined and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0076] If the above-described functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0077] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0078] Finally, it should be noted that the above-described embodiments are only specific embodiments of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting them. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that any person skilled in the art within the technical scope disclosed by the present invention can still modify the technical solutions described in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A DC offset correction circuit with a single current source, characterized in that, The DC offset correction circuit includes: a numerically controlled multi-channel current mirror circuit, a comparison circuit, an intermediate frequency link, and a digital logic circuit; wherein, the numerically controlled multi-channel current mirror circuit includes a reference current source. The numerically controlled multi-channel current mirror circuit, the intermediate frequency link, and the digital logic circuit are respectively connected to the comparison circuit, and the digital logic circuit is connected to the numerically controlled multi-channel current mirror circuit. The comparison circuit is configured to detect the in-phase output voltage and the anti-phase output voltage of the intermediate frequency link, and compare the in-phase output voltage with the anti-phase output voltage; when the in-phase output voltage is greater than the anti-phase output voltage, the output voltage is sent to the digital logic circuit. The digital logic circuit is configured to control the sign bit to be at a high level according to the output voltage, so that the numerically controlled multi-channel current mirror circuit injects current into the inverting input terminal, and the anti-phase output voltage increases; when the in-phase output voltage is still greater than the anti-phase output voltage, the size of the injected current is changed by the binary method according to the high level output by the comparison circuit until the in-phase output voltage is equal to the anti-phase output voltage, and the corresponding codeword is obtained.

2. The DC offset correction circuit of a single current source according to claim 1, characterized in that, The numerically controlled multi-channel current mirror circuit further includes a multi-channel current mirror unit, a plurality of switches, and a low-pass filter circuit; wherein, the low-pass filter circuit includes a resistor and a capacitor, and the plurality of switches include a fast control switch, a first switch, a second switch, and a third switch.

3. The DC offset correction circuit of a single current source according to claim 2, wherein Each current mirror unit corresponds to a current source with a binary proportional relationship; each current source mirrors and replicates the current from the reference current source according to a ratio through a bias voltage; each current source is controlled by a corresponding switch.

4. The DC offset correction circuit of a single current source according to claim 2, wherein The low-pass filter circuit is configured to filter out high-frequency noise.

5. The DC offset correction circuit of a single current source according to claim 2, wherein The fast control switch is connected in parallel with the resistor; when in the calibration mode, the fast control switch is closed to short-circuit the resistor.

6. The DC offset correction circuit of a single current source according to claim 2, wherein, The multi-channel current mirror unit is respectively connected to one end of the first switch, the other end of the first switch is respectively connected to one end of the second switch and one end of the third switch, the other end of the second switch is connected to the inverting input terminal, and the other end of the third switch is connected to the non-inverting input terminal.

7. The DC offset correction circuit with a single current source according to claim 2, wherein The reference current source is generated by an external reference current, and the current magnitude of the reference current source is an integer multiple of the minimum current.

8. A DC offset correction method for a single current source, characterized in that, Applied to the DC offset correction circuit with a single current source according to any one of claims 1 to 7, the DC offset correction circuit includes a numerically controlled multi-channel current mirror circuit, a comparison circuit, an intermediate frequency link, and a digital logic circuit; wherein, the numerically controlled multi-channel current mirror circuit includes a reference current source; the method includes: The comparison circuit detects the in-phase output voltage and the anti-phase output voltage of the intermediate frequency link. The comparison circuit compares the in-phase output voltage with the anti-phase output voltage. When the in-phase output voltage is greater than the anti-phase output voltage, the comparison circuit sends the output voltage to the digital logic circuit. The digital logic circuit controls the sign bit to be at a high level according to the output voltage, so that the numerically controlled multi-channel current mirror circuit injects current into the inverting input terminal, and the inverting output voltage increases; When the non-inverting output voltage is still greater than the inverting output voltage, the digital logic circuit changes the magnitude of the injected current by the dichotomy method according to the high level output by the comparison circuit, until the corresponding codeword is obtained when the non-inverting output voltage is equal to the inverting output voltage.

9. An electronic device, comprising a memory and a processor, wherein a computer program capable of running on the processor is stored on the memory, characterized in that When the processor executes the computer program, the method described in claim 8 above is implemented.

10. A computer-readable medium having non-volatile program code executable by a processor, characterized in that, The program code causes the processor to execute the method described in claim 8.

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