Data erasing method and memory storage device

Abstract

The invention provides a data erasing method and a memory storage device, which can reduce the response time of a data erasing instruction so as to improve the performance of a host system. The memory storage device comprises a memory module and a memory control circuit unit. The data erasing method comprises the steps that in response to a data erasing instruction, multiple target mapping tables are determined according to a target logic address of the data erasing instruction, and the multiple target mapping tables comprise a first mapping table and a second mapping table; executing a data erasing operation on the first mapping table to erase mapping information corresponding to the target logic address in the first mapping table; performing data pre-erasing operation on the second mapping table to mark the second mapping table in the target index table; and sending a reply to indicate that the data erasing instruction is completed.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and more particularly to a data erasure method and a memory storage device. Background Art

[0002] In recent years, the growth of smart phones, tablet computers, and personal computers has been very rapid, which has led to a sharp increase in consumers' demand for storage media. Since rewritable non-volatile memory modules (such as flash memory) have the characteristics of data non-volatility, power saving, small size, and no mechanical structure, they are very suitable for being built into various portable multimedia devices exemplified above.

[0003] Generally speaking, when there is valid data in the flash memory, the mapping information associated with this valid data will be stored in the mapping table to facilitate subsequent data erasure, reading, and writing operations. Specifically, the aforementioned mapping table is stored in the flash memory, and the memory controller can read the mapping table from the flash memory to perform data erasure, reading, and / or writing operations. For example, in a data erasure operation, the memory controller needs to load the mapping table from the flash memory and erase the data according to the mapping information in the mapping table. Then, the mapping table needs to be updated and rewritten into the flash memory. Such cumbersome steps make the data erasure operation take a long time to complete, resulting in low efficiency. Summary of the Invention

[0004] Exemplary embodiments of the present invention provide a data erasure method and a memory storage device, which can reduce the response time of data erasure instructions to improve the performance of the host system.

[0005] Exemplary embodiments of the present invention provide a data erasure method for a memory module. The memory module stores multiple mapping tables and multiple index tables. The data erasure method includes: in response to a data erasure instruction, determining multiple target mapping tables from the multiple mapping tables according to the target logical address of the data erasure instruction, where the multiple target mapping tables include a first mapping table and a second mapping table; performing a data erasure operation on the first mapping table to erase the mapping information corresponding to the target logical address in the first mapping table; performing a data pre-erasure operation on the second mapping table to mark the second mapping table in a target index table in the multiple index tables; and sending a reply to indicate that the data erasure instruction is completed.

[0006] In exemplary embodiments of the present invention, a part of the first mapping table corresponds to the target logical address, and the second mapping table completely corresponds to the target logical address.

[0007] In an exemplary embodiment of the present invention, after sending a reply to indicate completion of the data erasure instruction, the data erasure method further includes: performing the data erasure operation on the second mapping table to erase all mapping information in the second mapping table.

[0008] In an exemplary embodiment of the present invention, before sending the reply to indicate completion of the data erasure instruction, the data erasure method further includes: generating a data erasure task corresponding to the second mapping table and suspending it.

[0009] In an exemplary embodiment of the present invention, the step of performing the data pre-erasure operation on the second mapping table to mark the second mapping table in the target index table further includes: setting the most significant bit of the physical address of the second mapping table recorded in the target index table to 1 to mark the physical address as an invalid address.

[0010] In an exemplary embodiment of the present invention, the step of performing the data erasure operation corresponding to the second mapping table further includes: determining the second mapping table according to the invalid address in the target index table to perform the data erasure operation on the second mapping table.

[0011] In an exemplary embodiment of the present invention, each of the mapping tables is used to record the physical address of data in the memory module, and each of the index tables is used to record the physical address of the index table or the mapping table in the memory module.

[0012] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a memory module, and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the memory module. The connection interface unit is coupled to a host system. The memory module stores multiple mapping tables and multiple index tables. In response to a data erasure instruction, the memory control circuit unit determines multiple target mapping tables from the multiple mapping tables according to the target logical address of the data erasure instruction, where the multiple target mapping tables include a first mapping table and a second mapping table. The memory control circuit unit performs a data erasure operation on the first mapping table to erase the mapping information corresponding to the target logical address in the first mapping table. The memory control circuit unit performs a data pre-erasure operation on the second mapping table to mark the second mapping table in a target index table among the multiple index tables. The memory control circuit unit sends a reply to indicate completion of the data erasure instruction.

[0013] In an exemplary embodiment of the present invention, after sending the reply to indicate the completion of the data erasure instruction, the memory control circuit unit performs the data erasure operation on the second mapping table to erase all mapping information in the second mapping table.

[0014] In an exemplary embodiment of the present invention, before sending the reply to indicate the completion of the data erasure instruction, the memory control circuit unit generates a data erasure task corresponding to the second mapping table and suspends it.

[0015] In an exemplary embodiment of the present invention, the memory control circuit unit sets the highest bit of the physical address of the second mapping table recorded in the target index table to 1 to mark the physical address as an invalid address.

[0016] In an exemplary embodiment of the present invention, the memory control circuit unit determines the second mapping table according to the invalid address in the target index table to perform the data erasure operation on the second mapping table.

[0017] Based on the above, the present invention provides a data erasure method and a memory storage device, which can send a reply immediately after completing the data erasure operation on a part of the first mapping table corresponding to the target logical address to indicate the completion of the data erasure instruction, so as to reduce the response time of the data erasure instruction and improve the performance of the host system.

[0018] To make the above features and advantages of the present invention more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown according to an exemplary embodiment of the present invention;

[0020] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown according to an exemplary embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of a host system and a memory storage device shown according to an exemplary embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of a memory storage device shown according to an exemplary embodiment of the present invention;

[0023] Figure 5 is a schematic diagram of a memory control circuit unit shown according to an exemplary embodiment of the present invention;

[0024] Figure 6 is a schematic diagram of managing a memory module as shown in an exemplary embodiment of the present invention;

[0025] Figure 7 is a schematic diagram of managing a mapping table and an index table as shown in an exemplary embodiment of the present invention;

[0026] Figure 8 is a schematic diagram of a target mapping table as shown in an exemplary embodiment of the present invention;

[0027] Figure 9 is a flowchart of a data erasing method as shown in an exemplary embodiment of the present invention;

[0028] Figure 10 is a flowchart of a data erasing method as shown in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0029] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0030] Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0031] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device as shown in an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device as shown in an exemplary embodiment of the present invention.

[0032] Please refer to Figure 1 and Figure 2 , the host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110.

[0033] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 through a data transmission interface 114. For example, the host system 11 may store data in the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 through a system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0034] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 in a wired or wireless manner.

[0035] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon), etc., which are memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0036] In an exemplary embodiment, the host system 11 is a computer system. In an exemplary embodiment, the host system 11 may be any system that can substantially cooperate with the memory storage device to store data. In an exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include Figure 3 the memory storage device 30 and the host system 31.

[0037] Figure 3 is a schematic diagram of a host system and a memory storage device shown according to an exemplary embodiment of the present invention.

[0038] Please refer to Figure 3, the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342 that directly couple the memory module to the substrate of the host system.

[0039] Figure 4 is a schematic diagram of the memory storage device shown in an exemplary embodiment of the present invention.

[0040] Please refer to Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a memory module 43.

[0041] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be encapsulated in a single chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip that includes the memory control circuit unit 42.

[0042] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware form and perform operations such as data writing, reading, and erasing in the memory module 43 according to the instructions of the host system 11.

[0043] The memory module 43 is used to store the data written by the host system 11. The memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which 1 bit can be stored in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which 2 bits can be stored in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module in which 3 bits can be stored in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module in which 4 bits can be stored in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0044] Each memory cell in the memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, and thus one or more bits stored in this memory cell can be obtained.

[0045] In an exemplary embodiment, the memory cells of the memory module 43 may form multiple physical programming units, and these physical programming units may form multiple physical units. Specifically, the memory cells on the same word line may form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be at least classified into lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in an MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0046] In an exemplary embodiment, an entity programming unit is the smallest unit of programming. That is, an entity programming unit is the smallest unit for writing data. For example, an entity programming unit can be an entity page or an entity sector. If the entity programming unit is an entity page, these entity programming units may include a data bit region and a redundancy bit region. The data bit region contains a plurality of entity sectors for storing user data, and the redundancy bit region is used for storing system data (e.g., management data such as error correction codes). In this exemplary embodiment, the data bit region contains 32 entity sectors, and the size of one entity sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit region may also contain 8, 16, or a greater or smaller number of entity sectors, and the size of each entity sector may also be larger or smaller. On the other hand, an entity unit is the smallest unit of erasure. That is, each entity unit contains the smallest number of storage units that are erased together. For example, an entity unit is an entity block.

[0047] Figure 5 It is a schematic diagram of a memory control circuit unit shown according to an exemplary embodiment of the present invention.

[0048] Please refer to Figure 5 , the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0049] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as data writing, reading, and erasing. When explaining the operation of the memory management circuit 51 below, it is equivalent to explaining the operation of the memory control circuit unit 42.

[0050] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into this read-only memory. When the memory storage device 10 operates, these control instructions are executed by the microprocessor unit to perform operations such as data writing, reading, and erasing.

[0051] In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a specific area of the memory module 43 in the form of code (e.g., the system area of the memory module dedicated to storing system data). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the memory module 43 into the random access memory of the memory management circuit 51. After that, the microprocessor unit runs these control instructions to perform operations such as writing, reading, and erasing data.

[0052] In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage units or groups of storage units of the memory module 43. The memory write circuit is used to issue a write instruction sequence to the memory module 43 to write data into the memory module 43. The memory read circuit is used to issue a read instruction sequence to the memory module 43 to read data from the memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the memory module 43 to erase data from the memory module 43. The data processing circuit is used to process the data to be written into the memory module 43 and the data read from the memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence may each include one or more codes or instruction codes and are used to instruct the memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the memory module 43 to instruct the execution of corresponding operations.

[0053] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 is used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0054] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the memory module 43. For example, the memory management circuit 51 can access the memory module 43 through the memory interface 53. That is, the data to be written to the memory module 43 will be converted into a format acceptable to the memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences can include a write instruction sequence for indicating writing data, a read instruction sequence for indicating reading data, an erase instruction sequence for indicating erasing data, and corresponding instruction sequences for indicating various memory operations (such as changing the read voltage level or performing a garbage collection operation, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on the bus. These signals or data can include instruction codes or codes. For example, in the read instruction sequence, information such as the read identification code and memory address will be included.

[0055] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correcting circuit 54, a buffer memory 55, and a power management circuit 56.

[0056] The error checking and correcting circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correcting circuit 54 generates corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write instruction, and the memory management circuit 51 writes the data corresponding to this write instruction and the corresponding error correcting code and / or error detecting code into the memory module 43. After that, when the memory management circuit 51 reads data from the memory module 43, it also reads the corresponding error correcting code and / or error detecting code of this data, and the error checking and correcting circuit 54 performs error checking and correcting operations on the read data according to this error correcting code and / or error detecting code.

[0057] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0058] In an exemplary embodiment, Figure 4 the memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 the memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 the memory management circuit 51 may include a flash memory management circuit.

[0059] Figure 6 is a schematic diagram of managing a memory module shown in an exemplary embodiment of the present invention.

[0060] Please refer to Figure 6 , the memory management circuit 51 can logically group the physical units 610(0) - 610(B) in the memory module 43 into a storage area 601 and a spare area 602. A physical unit refers to a virtual block (VB). A virtual block may include multiple physical programming units. For example, a virtual block may contain one or more physical units.

[0061] The physical units 610(0) - 610(A) in the storage area 601 are used to store user data (such as from Figure 1user data of the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A + 1) to 610(B) in the free area 602 do not store data (such as valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to the free area 602. In addition, the physical units in the free area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the free area 602 to store this new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool.

[0062] The memory management circuit 51 can configure the logic units 612(0) to 612(C) to map the physical units 610(0) to 610(A) in the storage area 601. In an exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address can include one or more logical block addresses (LBAs) or other logical management units.

[0063] It should be noted that a logic unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logic unit, it means that the data stored in this physical unit currently contains valid data. On the contrary, if a physical unit is not currently mapped by any logic unit, it means that the data stored in this physical unit does not contain any valid data.

[0064] The memory management circuit 51 can record management data (also referred to as logical-to-physical mapping information) that describes the mapping relationship between the logic units and the physical units in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can perform data access operations on the memory storage device 10 according to the information in this logical-to-physical mapping table.

[0065] Figure 7 is a schematic diagram of a management mapping table and an index table shown according to an exemplary embodiment of the present invention.

[0066] Please refer to Figure 7 , the memory management circuit 51 can manage the information describing the mapping relationship between the logic units and the physical units using a multi-level (for example, three-level) table. In an exemplary embodiment, the memory module 43 stores multiple index tables FMT(0) to FMT(X), SMT(0) to SMT(Y), and multiple mapping tables TMT(0) to TMT(Z).

[0067] In an exemplary embodiment, mapping tables TMT(0) to TMT(Z) are used to record the physical addresses of data in memory module 43. Specifically, a logical unit can be mapped to one or more physical units. Each logical unit corresponds to a logical address. For example, a logical address can include one or more logical block addresses or other logical management units. Each physical unit corresponds to a physical address. For example, a physical address can include one or more physical block addresses (PBAs) or other physical management units. Mapping tables TMT(0) to TMT(Z) can be used to record the mapping information corresponding to logical addresses LNA(0) to LNA(i - 1). For example, mapping table TMT(0) can be used to record the mapping information corresponding to the first n logical addresses LNA(0) to LNA(n - 1) (i.e., the physical addresses of the data corresponding to the first n logical addresses LNA(0) to LNA(n - 1) in memory module 43). For example, mapping table TMT(1) can be used to record the mapping information corresponding to the (n + 1)th to 2nth logical addresses LNA(n) to LNA(2n - 1) (i.e., the physical addresses of the data corresponding to the first n logical addresses LNA(0) to LNA(n - 1) in memory module 43), and so on.

[0068] In an exemplary embodiment, index tables SMT(0) to SMT(Y) are used to record the physical addresses of mapping tables TMT(0) to TMT(Z) in memory module 43. For example, index table SMT(0) can be used to record the physical addresses of the first m mapping tables TMT(0) to TMT(m - 1) in memory module 43. For example, index table SMT(1) can be used to record the physical addresses of the (m + 1)th to 2mth mapping tables TMT(m) to TMT(2m - 1) in memory module 43, and so on.

[0069] In an exemplary embodiment, index tables FMT(0) to FMT(X) are used to record the physical addresses of index tables SMT(0) to SMT(Y) in memory module 43. For example, index table FMT(0) can be used to record the physical addresses of the first k index tables SMT(0) to SMT(k - 1) in memory module 43, and so on.

[0070] In an exemplary embodiment, when data stored in the memory module 43 is to be erased, the host system 11 transmits a data erase instruction and corresponding logical addresses (e.g., logical addresses LBA(2) to LBA(n + 3)) to the memory storage device 10. When performing a data erase operation corresponding to the data erase instruction, the memory management circuit 51 calculates corresponding mapping tables TMT(0), TMT(1), a corresponding index table SMT(0), and FMT(0) according to the logical addresses LBA(2) to LBA(n + 3). The index table FMT(0) is read (or loaded) from the memory module 43 to determine the physical address of the index table SMT(0), SMT(0) is read (or loaded) to determine the physical addresses of the mapping tables TMT(0), TMT(1), and finally the mapping tables TMT(0), TMT(1) corresponding to the logical addresses LBA(2) to LBA(n + 3) are read (or loaded), and the physical addresses mapped to the logical addresses LBA(2) to LBA(n + 3) are obtained from the mapping table TMT(0), and the valid data count in the physical unit corresponding to this physical address is modified. Thereafter, the memory management circuit 51 may erase the information associated with the logical addresses LBA(2) to LBA(n + 3) in the mapping tables TMT(0), TMT(1), and then write the modified mapping tables TMT(0), TMT(1) to the memory module 43. Specifically, the memory management circuit 51 needs to disconnect the mapping relationship between the logical addresses LBA(2) to LBA(n + 3) and their corresponding physical addresses, and then write the modified mapping tables TMT(0), TMT(1) to the memory module 43.

[0071] Thereafter, the memory management circuit 51 updates the index table FMT(0) and the index table SMT(0) corresponding to the mapping tables TMT(0), TMT(1), and then writes the updated index table FMT(0) and the index table SMT(0) to the memory module 43. Specifically, after the modified mapping tables TMT(0), TMT(1) are rewritten to the memory module 43, since the storage addresses of the mapping tables TMT(0), TMT(1) have changed, the memory management circuit 51 needs to update the physical addresses of the mapping tables TMT(0), TMT(1) recorded in the corresponding index table SMT(0), and then write the updated index table SMT(0) to the memory module 43. Similarly, after the updated index table SMT(0) is rewritten to the memory module 43, the memory management circuit 51 needs to update the physical address of the index table SMT(0) recorded in the corresponding index table FMT(0), and then write the updated index table FMT(0) to the memory module 43. Finally, the memory management circuit 51 outputs a reply (e.g., an erase success message) to the host system 11 to indicate that the data erase instruction has been completed.

[0072] According to the above, in the data erasure operation, the memory management circuit 51 reads the required mapping tables and index tables from the memory module 43. Therefore, if the range of logical addresses corresponding to the data erasure operation is very large, the memory management circuit 51 needs to read (load) many mapping tables and index tables from the memory module 43, update the read mapping tables and index tables, and rewrite the updated mapping tables and index tables to the memory module 43 before it can indicate to the host system 11 that the erasure is complete. In this way, it takes a lot of time to complete the data erasure operation, resulting in an overly long waiting time for the host system 11 for the data erasure operation, thus affecting the performance of the host system 11.

[0073] In view of this, the present invention improves the above data erasure operation by dividing the data erasure operation into operations to be processed currently and operations to be processed subsequently, and after the operations to be processed currently are completed, the memory management circuit 51 immediately sends a reply to the host system 11 to indicate that the data erasure instruction is complete. Accordingly, the response time of the data erasure instruction can be significantly reduced, that is, the waiting time of the host system 11 for the data erasure operation is reduced, thereby improving the performance of the host system 11.

[0074] Figure 8 is a schematic diagram of a target mapping table shown according to an exemplary embodiment of the present invention; Figure 9 is a flowchart of a data erasure method shown according to an exemplary embodiment of the present invention.

[0075] Please refer to Figure 8 and Figure 9 , in step S901, in response to the data erasure instruction, the memory management circuit 51 can determine multiple target mapping tables according to the target logical address of the data erasure instruction. In an exemplary embodiment, when receiving a data erasure instruction and its logical address (i.e., the target logical address) from the host system 11, the memory management circuit 51 can determine the target mapping tables from the mapping tables TMT(0) to TMT(Z) according to the target logical address. As Figure 8 shown, the target mapping tables include the mapping tables TMT(2), TMT(m + 1) (also referred to as the first mapping tables) that partially correspond to the target logical address, and the mapping tables TMT(3) to TMT(m + 1) (also referred to as the second mapping tables) that completely correspond to the target logical address.

[0076] In step S902, the memory management circuit 51 can perform a data erasure operation on the first mapping tables TMT(2), TMT(m + 1). Specifically, the memory management circuit 51 can perform a data erasure operation on the first mapping tables TMT(2), TMT(m + 1) to erase the mapping information corresponding to the target logical address in the first mapping tables TMT(2), TMT(m + 1).

[0077] In an exemplary embodiment, the memory management circuit 51 may read the first mapping tables TMT(2), TMT(m + 1) and their corresponding index tables SMT(0), SMT(1) and index table FMT(0) from the memory module 43 (that is, the index tables SMT(0) and SMT(1) for recording the physical addresses of the first mapping tables TMT(2), TMT(m + 1) in the memory module 43, and the index table FMT(0) for recording the physical addresses of the index tables SMT(0) and SMT(1) in the memory module 43). Then, the memory management circuit 51 may erase the mapping information corresponding to the target logical address in the first mapping tables TMT(2), TMT(m + 1) to complete the data erasure operation for the first mapping tables TMT(2), TMT(m + 1). The memory management circuit 51 rewrites the first mapping tables TMT(2), TMT(m + 1) into the memory module 43 and updates the physical addresses of the first mapping tables TMT(2), TMT(m + 1) recorded in the index tables SMT(0), SMT(1) to complete the first data erasure operation.

[0078] In step S903, the memory management circuit 51 may perform a data pre-erasure operation on the second mapping tables TMT(3) to TMT(m). Specifically, the memory management circuit 51 may perform a data pre-erasure operation on the second mapping tables TMT(3) to TMT(m) to mark the second mapping tables TMT(3) to TMT(m) in the target index tables SMT(0), SMT(1) among the index tables SMT(0) to SMT(Y), where the target index tables SMT(0), SMT(1) are used to record the physical addresses of the second mapping tables TMT(3) to TMT(m). In an exemplary embodiment, the memory management circuit 51 may, for example, set the most significant bit of the physical addresses of the second mapping tables TMT(3) to TMT(m) recorded in the target index tables SMT(0), SMT(1) to 1 to mark the physical addresses as invalid addresses to complete the data pre-erasure operation for the second mapping tables TMT(3) to TMT(m). In an exemplary embodiment, the memory management circuit 51 may also, for example, record in the target index tables SMT(0), SMT(1) the information indicating that the second mapping tables TMT(3) to TMT(m) are to be erased to complete the data pre-erasure operation for the second mapping tables TMT(3) to TMT(m). In an exemplary embodiment, the memory management circuit 51 may, for example, generate data erasure tasks corresponding to the second mapping tables TMT(3) to TMT(m) and suspend them to indicate that the second mapping tables TMT(3) to TMT(m) are to be erased.

[0079] In an embodiment, after completing the first erasing operation and the second pre-erasing operation, the memory management circuit 51 may write the index tables SMT(0) and SMT(1) back to the memory module 43, and the memory management circuit 51 may also update the physical addresses of the index tables SMT(0) and SMT(1) in the index table FMT(0).

[0080] In step S904, the memory management circuit 51 may send a reply. Specifically, the memory management circuit 51 may send a reply to the host system 11 to indicate that the data erasing instruction is completed.

[0081] It should be noted that in the conventional approach, the memory management circuit 51 directly reads (or loads) all the target mapping tables TMT(2) to TMT(m + 1) and erases the mapping information corresponding to the target logical addresses in the target mapping tables TMT(2) to TMT(m + 1), and then sends a reply indicating that the data erasing instruction is completed to the host system 11.

[0082] However, in Figure 9 the data erasing method, the memory management circuit 51 only performs data erasing operations and data pre-erasing operations on the first mapping tables TMT(2) and TMT(m + 1) and the second mapping tables TMT(3) to TMT(m) respectively, and notifies the host system 11 that the data erasing instruction has been completed without reading (or loading) the second mapping tables TMT(3) to TMT(m) and erasing the mapping information corresponding to the target logical addresses therein. Since the memory management circuit 51 has marked the physical addresses of the second mapping tables TMT(3) to TMT(m) recorded in the target index tables SMT(0) and SMT(1), for the host system 11, the data corresponding to the second mapping tables TMT(3) to TMT(m) has been marked as invalid data, and the host system 11 will not read the data to be erased. Accordingly, while improving the performance of the host system 11, the correctness of data reading can be ensured.

[0083] In step S905, the memory management circuit 51 may perform a data erasure operation on the second mapping tables TMT(3) to TMT(m). Specifically, the memory management circuit 51 may perform a data erasure operation on the second mapping tables TMT(3) to TMT(m) to erase all mapping information in the second mapping tables TMT(3) to TMT(m). In an exemplary embodiment, after sending a reply to the host system 11, the memory management circuit 51 may determine the true physical addresses of the second mapping tables TMT(3) to TMT(m) according to the invalid addresses in the target index tables SMT(0) and SMT(1), so as to read (or load) the second mapping tables TMT(3) to TMT(m) and perform a data erasure operation. In an exemplary embodiment, after sending a reply to the host system 11, the memory management circuit 51 may execute the suspended data erasure task to perform a data erasure operation on the second mapping tables TMT(3) to TMT(m). In an exemplary embodiment, after sending a reply to the host system 11, the host system 11 may continue to issue other operation instructions for the memory storage device 10. Therefore, the memory management circuit 51 may first execute other operation instructions, and when the memory storage device 10 is in an idle state (for example, there are no operation instructions to be executed), then execute the suspended data erasure task to perform a data erasure operation on the second mapping tables TMT(3) to TMT(m).

[0084] In an exemplary embodiment, the memory management circuit 51 may read the second mapping tables TMT(3) to TMT(m) (and the target index tables SMT(0) and SMT(1)) from the memory module 43, and erase all the mapping information recorded in the second mapping tables TMT(3) to TMT(m). Specifically, since the second mapping tables TMT(3) to TMT(m) completely correspond to the target logical addresses, the memory management circuit 51 will modify the valid data count in the physical units corresponding to these physical addresses according to the physical addresses corresponding to all the mapping information in the second mapping tables TMT(3) to TMT(m), and erase all the mapping information in the second mapping tables TMT(3) to TMT(m) to complete the second data erasure operation.

[0085] According to the above, the memory management circuit 51 can preferentially process the data erasure operations of part of the first mapping tables TMT(2) and TMT(m + 1) corresponding to the target logical address (i.e., the operations to be processed currently), and after sending a reply to the host system 11, then process the data erasure operations of the second mapping tables TMT(3) to TMT(m) that completely correspond to the target logical address (i.e., the operations to be processed subsequently), so as to improve the performance of the host system 11. That is to say, the memory management circuit 51 can use "whether it completely corresponds to the target logical address" as a basis to divide the data erasure operations corresponding to the data erasure instruction into the operations to be processed currently and the operations to be processed subsequently, and after the operations to be processed currently are completed, immediately send a reply to the host system 11 to indicate that the data erasure instruction is completed, which can greatly reduce the response time of the data erasure instruction (i.e., reduce the waiting time of the host system 11 for the data erasure operation), thereby improving the performance of the host system 11.

[0086] Figure 10 It is a flowchart of the data erasure method shown in an exemplary embodiment of the present invention. Please refer to Figure 10 . In step S1001, in response to the data erasure instruction, multiple target mapping tables are determined from multiple mapping tables according to the target logical address of the data erasure instruction, where the multiple target mapping tables include a first mapping table and a second mapping table. In step S1002, a data erasure operation is performed on the first mapping table to erase the mapping information corresponding to the target logical address in the first mapping table. In step S1003, a data pre-erasure operation is performed on the second mapping table to mark the second mapping table in the target index table among the multiple index tables. In step S1004, a reply is sent to indicate that the data erasure instruction is completed.

[0087] However, Figure 10 each step in Figure 10 has been described in detail above and will not be repeated here. It should be noted that Figure 10 each step in

[0088] In summary, the data erasure method and the memory storage device according to the exemplary embodiments of the present invention can determine a first mapping table partially corresponding to the target logical address and a second mapping table completely corresponding to the target logical address according to the target logical address of the data erasure instruction. After completing the data erasure operation performed on the first mapping table and the data pre-erasure operation performed on the second mapping table, the host system is immediately notified that the data erasure instruction has been completed, so as to significantly reduce the response time of the data erasure instruction (that is, reduce the waiting time of the host system for the data erasure operation), while improving the performance of the host system and ensuring that the host system does not read old (that is, data that should be erased) data.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data erasure method, characterized in that, For a memory module that stores multiple mapping tables and multiple index tables, the data erasure method includes: In response to a data erasure instruction, determine multiple target mapping tables from the multiple mapping tables according to the target logical address of the data erasure instruction, where the multiple target mapping tables include a first mapping table and a second mapping table; Perform a data erasure operation on the first mapping table to erase the mapping information corresponding to the target logical address in the first mapping table; Perform a data pre-erasure operation on the second mapping table to mark the second mapping table in a target index table among the multiple index tables; and Send a reply to indicate completion of the data erasure instruction.

2. The data erasure method according to claim 1, wherein the first mapping table partially corresponds to the target logical address, and the second mapping table completely corresponds to the target logical address.

3. The data erasure method according to claim 1, wherein after sending the reply to indicate completion of the data erasure instruction, the data erasure method further includes: Perform the data erasure operation on the second mapping table to erase all mapping information in the second mapping table.

4. The data erasure method according to claim 3, wherein before sending the reply to indicate completion of the data erasure instruction, the data erasure method further includes: Generate a data erasure task corresponding to the second mapping table and suspend it.

5. The data erasure method according to claim 3, wherein the step of performing the data pre-erasure operation on the second mapping table to mark the second mapping table in the target index table further includes: Set the most significant bit of the physical address of the second mapping table recorded in the target index table to 1 to mark the physical address as an invalid address.

6. The data erasure method according to claim 5, wherein the step of performing the data erasure operation corresponding to the second mapping table further includes: Determine the second mapping table according to the invalid address in the target index table to perform the data erasure operation on the second mapping table.

7. The data erasure method according to claim 1, wherein each of the mapping tables is used to record the physical address of data in the memory module, and each of the index tables is used to record the physical address of the index table or the mapping table in the memory module.

8. A memory storage device, characterized in that, Includes: A connection interface unit for coupling to a host system; A memory module that stores multiple mapping tables and multiple index tables; And A memory control circuit unit coupled to the connection interface unit and the memory module, where In response to a data erasure instruction, the memory control circuit unit determines multiple target mapping tables from the multiple mapping tables according to the target logical address of the data erasure instruction, where the multiple target mapping tables include a first mapping table and a second mapping table, The memory control circuit unit performs a data erasure operation on the first mapping table to erase the mapping information corresponding to the target logical address in the first mapping table, The memory control circuit unit performs a data pre-erasure operation on the second mapping table to mark the second mapping table in a target index table among the multiple index tables. The memory control circuit unit sends a reply to indicate completion of the data erasure instruction.

9. The memory storage device according to claim 8, wherein the first mapping table partially corresponds to the target logical address, and the second mapping table completely corresponds to the target logical address.

10. The memory storage device according to claim 8, wherein after sending the reply to indicate completion of the data erasure instruction, the memory control circuit unit performs the data erasure operation on the second mapping table to erase all mapping information in the second mapping table.

11. The memory storage device according to claim 10, wherein before sending the reply to indicate completion of the data erasure instruction, the memory control circuit unit generates a data erasure task corresponding to the second mapping table and suspends it.

12. The memory storage device according to claim 10, wherein the memory control circuit unit sets the most significant bit of the physical address of the second mapping table recorded in the target index table to 1 to mark the physical address as an invalid address.

13. The memory storage device according to claim 12, wherein the memory control circuit unit determines the second mapping table according to the invalid address in the target index table to perform the data erasure operation on the second mapping table.

14. The memory storage device according to claim 8, wherein each mapping table is used to record the physical address of data in the memory module, and each index table is used to record the physical address of the index table or the mapping table in the memory module.

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