Processor system

Abstract

The invention discloses a processor system, and relates to the technical field of computers, the system comprises a processor node, a scheduler and a system storage space in which a third task set is constructed, and the processor node comprises a processor and a node storage space; the scheduler is used for screening out a reference processor from the processors; according to task quantity information of a reference task set, a target task set is screened out from the candidate task set, and the reference task set is a first task set in a processor storage space of a reference processor; the candidate task set comprises a reference task set, and a second task set and a third task set in a processor node where a reference processor is located; distributing the reference task to a target task set; and the reference processor is used for executing the tasks stored in the candidate task set. Through the method and the device, the technical problem of relatively low processing efficiency of the read-write request in related technologies is solved, and the technical effect of improving the processing efficiency of the read-write request is achieved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and particularly to a processor system. Background Art

[0002] With the continuous development of modern technologies, the process of a processor handling read / write requests has drawn increasing attention. In a multi-processor system, read / write requests are usually processed by the processor that generates the request (or task). However, in a NUMA (Non-Uniform Memory Access) architecture, this request allocation method has obvious problems. Due to the transmission delay between the storage device and the processor, read / write requests easily cross NUMA nodes for data transmission, resulting in a decline in processing efficiency. In addition, when each processor processes read / write requests, there is also an easy accumulation of requests to be processed, further affecting the processing efficiency of read / write requests. Summary of the Invention

[0003] This application provides a processor system to at least solve the problem of low processing efficiency of read / write requests in related technologies.

[0004] This application provides a processor system, including: multiple processor nodes, a scheduler, and a system storage space. Each processor node includes: one or more processors and a node storage space. Each processor has a processor storage space, a first task set is built in the processor storage space, a second task set is built in the node storage space, and a third task set is built in the system storage space;

[0005] The scheduler is configured to screen out a reference processor corresponding to a received reference task from the processors; screen out a target task set from a candidate task set according to the task quantity information of the reference task set, where the reference task set is the first task set in the processor storage space of the reference processor, and the candidate task set includes: the reference task set, the second task set in the processor node where the reference processor is located, and the third task set; and distribute the reference task to the target task set;

[0006] The reference processor is configured to execute the tasks stored in the candidate task set.

[0007] With this application, since the processor system includes multiple processor nodes, a scheduler, and system storage space, each processor node includes: one or more processors and a node memory. Each processor has a processor storage space in which a first task set is constructed, a second task set is constructed in the node storage space, and a third task set is constructed in the system storage space. The scheduler is used to screen out a reference processor corresponding to a received reference task from the processors, and replaces the way that the reference task is directly processed by the processor that generates the reference task with the way that the scheduler screens the corresponding reference processor to process the reference task, avoiding unnecessary cross-NUMA node transmission of the reference task in the processor system; the scheduler then screens out a target task set from a candidate task set including the reference task set, the second task set, and the third task set in the processor node where the reference processor is located according to the task volume information of the reference task set. The reference processor is used to execute the tasks stored in the candidate task set, avoiding that only a single fixed processor can process read and write tasks, and further improving the processing efficiency of read and write tasks. Therefore, the technical problem of low processing efficiency of read and write requests can be solved, and the technical effect of improving the processing efficiency of read and write requests can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To more clearly illustrate the embodiments of the present application, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0009] Figure 1 is a schematic diagram of a processor system according to an embodiment of the present application;

[0010] Figure 2 is a schematic diagram of a processor system combined with a user-mode storage mechanism according to an embodiment of the present application;

[0011] Figure 3 is a flowchart of a processing method for a reference task according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0013] It should be noted that in the description of this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects and not to describe a specific order or sequence.

[0014] To enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific embodiments.

[0015] In this embodiment, a processor system is provided. Figure 1 It is a schematic diagram of a processor system according to an embodiment of this application, as Figure 1 shown. The processor system includes:

[0016] Multiple processor nodes, a scheduler, and a system storage space. Each processor node includes: one or more processors and a node storage space. Each processor has a processor storage space in which a first task set is constructed, a second task set is constructed in the node storage space, and a third task set is constructed in the system storage space;

[0017] The scheduler is used to screen out a reference processor corresponding to a received reference task from the processors; screen out a target task set from a candidate task set according to the task volume information of the reference task set, where the reference task set is the first task set in the processor storage space of the reference processor, and the candidate task set includes: the reference task set, the second task set and the third task set in the processor node where the reference processor is located; distribute the reference task to the target task set;

[0018] The reference processor is used to execute the tasks stored in the candidate task set.

[0019] Through the above content, since the processor system includes multiple processor nodes, a scheduler, and system storage space, each processor node includes: one or more processors and a node memory. Each processor has a processor storage space, in which a first task set is constructed, a second task set is constructed in the node storage space, and a third task set is constructed in the system storage space. The scheduler is used to screen out a reference processor corresponding to the received reference task from the processors, and replaces the method of directly processing the reference task by the processor that generates the reference task with the method of scheduling the corresponding reference processor to process the reference task, avoiding unnecessary cross-NUMA node transmission of the reference task in the processor system. Then, the scheduler screens out a target task set from a candidate task set including the reference task set, the second task set in the processor node where the reference processor is located, and the third task set according to the task volume information of the reference task set. The reference processor is used to execute the tasks stored in the candidate task set, avoiding that only a single fixed processor can process read and write tasks, and further improving the processing efficiency of read and write tasks. Therefore, the technical problem of low processing efficiency of read and write requests can be solved, and the technical effect of improving the processing efficiency of read and write requests can be achieved.

[0020] Optionally, in this embodiment, the processor system may but is not limited to including multiple processor nodes. Each processor node may but is not limited to including one or more processors. For example, a multi-core CPU (Central Processing Unit) may be regarded as a processor system, and multiple cores (i.e., processors) in the multi-core CPU may but is not limited to be divided into multiple core sets (i.e., processor nodes).

[0021] Optionally, in this embodiment, the processor system may but is not limited to including system storage space, each processor node may but is not limited to including node storage space, and each processor may but is not limited to having processor storage space. Among them, each processor in the processor system can access its own processor storage space with low latency, and can also access the node storage space in the processor node where each processor is located with low latency. However, the access latency of each processor to the system storage space is higher than the access latency to the node storage space in the processor node where each processor is located, and also higher than the access latency to the processor storage space in each processor.

[0022] Optionally, in this embodiment, a first task set may be built, but is not limited to, in the processor storage space of each processor, a second task set may be built, but is not limited to, in the node storage space of each processor node, and a third task set may be built, but is not limited to, in the system storage space. Each first task set may, but is not limited to, correspond to each processor one by one, and each second task set may, but is not limited to, correspond to multiple processors. For example, in a processor system, the first task set a corresponds to processor A, the first task set b corresponds to processor B, the first task set c corresponds to processor C, the second task set d corresponds to processor A and processor B, and the second task set e corresponds to processor C.

[0023] Optionally, in this embodiment, each processor may, but is not limited to, first extract tasks from the corresponding first task set for execution. In the case where there are no tasks to be executed in the corresponding first task set, tasks are extracted from the corresponding second task set for execution. In the case where there are also no tasks to be executed in the corresponding second task set, tasks are extracted from the third task set for execution.

[0024] Optionally, in this embodiment, the scheduler may, but is not limited to, be used to determine the scope of the execution entity for the received reference task. The scheduler may, but is not limited to, be used to screen out the reference processors corresponding to the received reference task from the processors, and first determine the reference processors and the processors in the same processor node as the reference processors as the processors that can execute the reference task (that is, first distribute the reference task to the second task set in the reference task set and the processor node where the reference processor is located). To avoid the reference task being completely unable to be executed due to the failure of the processor node where the reference processor is located, the scheduler may, but is not limited to, determine all the processors in the processor system as the processors that can execute the reference task in the case where the processor node where the reference processor is located is completely unable to process the reference task or has a large load pressure (that is, distribute the reference task to the third task set).

[0025] Optionally, in this embodiment, it is possible but not limited to construct a storage device-core (or processor) binding matrix that minimizes the NUMA distance cost function according to the topological relationship and NUMA distance cost function between the PCIe (Peripheral Component Interconnect Express) position of the storage device and the CPU socket, that is, establish the corresponding relationship between the storage device and the processor. The scheduler is used to screen out the reference processor corresponding to the received reference task from the processors, which may but is not limited to including the scheduler matching the corresponding processor for the reference storage device corresponding to the reference task from the storage device and the processor with the corresponding relationship to obtain the reference processor, where the reference task may but is not limited to be used to request access to the reference storage device.

[0026] Optionally, in this embodiment, the task volume information may but is not limited to be used to indicate the task volume of the tasks in the reference task set. It is possible but not limited to determine the reference task set as the target task set when the task volume information is used to indicate that the task volume of the tasks in the reference task set is less than or equal to the task volume threshold; when the task volume information is used to indicate that the task volume of the tasks in the reference task set is greater than the task volume threshold, determine the second task set or the third task set in the processor node where the reference processor is located as the target task set.

[0027] Optionally, in this embodiment, it is possible but not limited to migrate some of the tasks included in the first task set to the corresponding second task set when there are too many tasks included in the first task set.

[0028] Optionally, in this embodiment, it is possible but not limited to migrate some of the tasks included in the second task set to the third task set when there are too many tasks included in the second task set.

[0029] Optionally, in this embodiment, it is possible but not limited to apply the processor system of the present application to a task processing flow that does not require switching between the user mode and the kernel mode, so that when the reference processor executes the tasks stored in the candidate task set, it only needs to interact with the storage device using the user-mode driver without having to switch to the kernel mode, further improving the processing efficiency of read and write requests.

[0030] Figure 2It is a schematic diagram of a processor system incorporating a user-space storage mechanism according to an embodiment of the present application. Among them, the top layer of the user-space storage system is the application layer, usually applications that require high-performance storage, such as databases, caches, distributed file systems, etc. The application layer relies on the user-space storage library / engine to handle storage requirements. The User-space Storage Library / Engine is the core part of the user-space storage system, responsible for providing storage-related interfaces and implementations, such as data block management, file system implementation, database storage engine, etc. It is responsible for handling the reading, writing, allocation, management, and data recovery of stored data. The User-space Storage Management manages the use of storage resources, including memory allocation, data caching, persistent storage, space optimization, data compression, etc. It coordinates the data block operations in the storage library / engine and determines when to persist data to the underlying storage device. In a multi-tasking environment, the I / O Request Scheduling is responsible for managing storage requests from applications, ensuring that requests are allocated to storage devices in an orderly and reasonable manner. It usually implements strategies such as I / O queues, priority scheduling, and load balancing. The User-space Drivers component at this level is responsible for communicating with the underlying hardware storage device. The drivers of traditional storage devices are usually in the kernel space, but in the user-space storage system, the drivers can also run in the user space and control the storage device through special technologies (such as DPU (Data Processing Unit), RDMA (Remote Direct Memory Access), SPDK (Storage Performance Development Kit), etc.). The bottom layer is the actual Storage Devices, including disks, SSDs (Solid State Drives), NVMe (Non-Volatile Memory Express) devices, network storage (such as iSCSI (Internet Small Computer Systems Interface), NFS (Network File System), Ceph (distributed storage system), etc.). These devices provide physical storage space for the user-space storage system to use.

[0031] As an alternative embodiment, the processor system further includes a plurality of storage devices; a scheduler for matching a corresponding processor for a target storage device from the processors and storage devices with a corresponding relationship to obtain a reference processor, where the target storage device is the storage device requested to be accessed by a reference task among the plurality of storage devices; a scheduler for detecting a first state of a reference task set indicated by task volume information; in the case where the first state is that the task volume of the reference task set is less than a first threshold, determining the reference task set as a target task set; in the case where the first state is that the task volume of the reference task set is greater than or equal to the first threshold, detecting a second state of a second task set in the processor node where the reference processor is located; in the case where the second state is that the task volume of the second task set in the processor node where the reference processor is located is less than a second threshold, determining the second task set in the processor node where the reference processor is located as a target task set; in the case where the second state is that the task volume of the second task set in the processor node where the reference processor is located is greater than or equal to the second threshold, determining a third task set as a target task set.

[0032] Optionally, in this embodiment, the plurality of processors included in the processor system may but are not limited to have different access latency characteristics for the plurality of storage devices included in the processor system, and the plurality of processors located in the same processor node may but are not limited to have the same access latency characteristics for the same storage device; it is possible but not limited to match a corresponding processor for a target storage device from the processors and storage devices with a corresponding relationship, so that the processor with a lower access latency for the target storage device can preferentially execute the reference task, improving the processing efficiency of read and write requests.

[0033] Optionally, in this embodiment, the scheduler may but is not limited to be used to screen out the target task set from the candidate task sets according to the first task state of the reference task set, the second task state of the second task set in the processor node where the reference processor is located, and the third task state of the third task set.

[0034] As an alternative embodiment, the scheduler is further used to aggregate a plurality of processing requests into one or more processing tasks according to the request information of the processing requests and the processing information of each storage device, where the one or more processing tasks include reference tasks, the request information is used to indicate the storage device requested to be accessed by the processing request, the request information corresponding to the processing requests included in the processing task is the same, and the processing information is used to indicate the data access capabilities of each storage device.

[0035] Optionally, in this embodiment, when the scheduler receives a processor request, it may, but is not limited to, not directly distribute the processing request to each task set for processing. Instead, it aggregates multiple processing requests that access the same storage device into an overall processing task, and then distributes each processing task.

[0036] Optionally, in this embodiment, when aggregating processing requests into a processing task, the number of processing requests to be aggregated into one processing task may, but is not limited to, be determined by the data access capabilities of each storage device.

[0037] Through the above content, aggregating multiple processing requests into one processing task and allocating a corresponding processor to the processing task reduces the number of scheduling operations of the scheduler and saves operation resources compared to allocating a corresponding processor to the processing request.

[0038] As an optional implementation manner, a fourth task set is further constructed in the processor storage space; the scheduler is further configured to detect the processing priority of each processing request before aggregating multiple processing requests into one or more processing tasks according to the request information of the processing request and the processing information of each storage device, where the processing priority is used to indicate the importance of the processing request; in the case where it is detected that the processing priority of the target request is used to indicate that the importance of the target request is higher than the degree threshold, distribute the target request to the priority task set, where each processing request includes the target request, and the priority task set is the fourth task set in the processor storage space of the target processor corresponding to the target request; the target processor is configured to, when the priority task set is not empty, preferentially execute the tasks stored in the priority task set; and when the tasks stored in the priority task set are executed, execute the tasks stored in the first task set in the processor storage space of the target processor, or the tasks stored in the second task set in the processor node where the target processor is located, or the tasks stored in the third task set.

[0039] Optionally, in this embodiment, in addition to constructing the first task set, a fourth task set may, but is not limited to, be constructed in each processor storage space, where the execution priority of the tasks in the fourth task set in the same processor storage space is higher than that of the tasks in the first task set.

[0040] Optionally, in this embodiment, the scheduler may, but is not limited to, detect the processing priority of a processing request before aggregating multiple processing requests. Generally speaking, processing requests whose importance indicated by the processing priority is higher than a degree threshold need to be executed at the fastest speed. Therefore, when it is detected that the processing priority of a target request indicates that the importance of the target request is higher than the degree threshold, the target request is distributed to the priority task set so that the target request can be executed quickly.

[0041] Based on the above content, the scheduler does not blindly aggregate processing requests, but distributes processing requests with more urgent execution requirements to the fourth task set with higher execution priority, so that sudden emergency processing requests can be executed quickly, which improves the processing efficiency of read and write requests from another level.

[0042] As an optional implementation manner, the scheduler is further configured to detect the data volume of the data requested to be accessed by a reference task; when the data volume is greater than a data volume threshold, filter out a target task set from an alternative task set, where the alternative task set includes: a second task set and a third task set in the processor node where the reference processor is located; when the data volume is less than or equal to the data volume threshold, perform the step of filtering out a target task set from a candidate task set according to the task volume information of the reference task set.

[0043] Optionally, in this embodiment, the scheduler may, but is not limited to, further detect the data volume of the data requested to be accessed by a reference task. When the data volume is greater than the data volume threshold, that is, when the data volume is too large, the reference task is directly distributed to the second task set or the third task set, because a reference task with a large data volume is likely to trigger task migration, resulting in such a reference task being migrated to the second task set or the third task set after being distributed to the first task set, and the intermediate migration operation increases the useless operation overhead of the system. By no longer allocating such a reference task to the first task set when it is detected that the data volume is greater than the data volume threshold, the waste of operation resources caused by the migration step is reduced.

[0044] As an optional implementation manner, the processor system further includes a regulator; the regulator is configured to, when the task volume parameter in the first adjustment set in each first task set is greater than a third threshold, migrate some of the tasks stored in the first adjustment set to the second task set in the same processor node as the first adjustment set, where the task volume parameter is used to indicate the task volume of the tasks currently stored in the corresponding task set, and the task sets include the first task set, the second task set, and the third task set.

[0045] Optionally, in this embodiment, the processor system may but is not limited to further include a regulator, which may but is not limited to be used to adjust the number of tasks stored in the first task set, the second task set, and the third task set.

[0046] Through the above, when there are too many tasks stored in the first adjustment set, a part of the tasks are migrated to the corresponding second task set, that is, the tasks that the processor corresponding to the first adjustment set cannot process in time are forwarded to other processors on the same processor node for processing, effectively utilizing the processing capabilities of each processor on this processor node.

[0047] As an optional implementation manner, the regulator is further used to, when the task quantity parameter in the second adjustment set in each second task set is greater than the fourth threshold, migrate some of the tasks stored in the second adjustment set to the third task set.

[0048] Optionally, in this embodiment, it may but is not limited to calculate the difference between the task quantity parameter of the second adjustment set and the fourth threshold, and extract the tasks with the difference quantity from the second adjustment set and migrate them to the third task set.

[0049] Optionally, in this embodiment, the fourth threshold may but is not limited to be determined according to the data transmission delay time across processor nodes. It may but is not limited to that when the task quantity parameter in the second adjustment set is equal to the fourth threshold, the time difference between the waiting time before the last task to be executed in the second adjustment set is executed and the migration time of the last task during the process of the last task being executed by a processor across processor nodes in other processor nodes (that is, the time for the second task set to migrate to the third task set) is within a relatively narrow time difference range.

[0050] Through the above, when the task quantity parameter in the second adjustment set is greater than the fourth threshold, by migrating some of the tasks stored in the second adjustment set to the third task set, it is possible to comprehensively consider the delay of data transmission across nodes and the waiting delay of task execution, and better improve the processing efficiency of read and write requests in combination with the actual situation when the load pressure of the processors on the same processor node is relatively large.

[0051] As an optional implementation manner, the regulator is further used to detect the change parameter in the second adjustment set, where the change parameter is used to indicate the execution speed of the tasks stored in the second adjustment set; when it is detected that the change parameter is used to indicate that the execution speed of the tasks stored in the second adjustment set is higher than the speed threshold, cancel or delay the step of migrating some of the tasks stored in the second adjustment set to the third task set.

[0052] Optionally, in this embodiment, it is possible but not limited to delaying or canceling the migration of tasks in the second task set to the third task set when the tasks in the second adjustment set are executed quickly, so as to reduce unnecessary migration operations.

[0053] As an optional implementation manner, the adjuster is further configured to reduce the migration amount of tasks migrated to the third adjustment set when the task amount parameter in the third adjustment set in each second task set is greater than or equal to a fifth threshold, where the fifth threshold is greater than the fourth threshold; the adjuster is further configured to cancel the migration of tasks to the third task set when the task amount parameter in the third task set is greater than or equal to a sixth threshold.

[0054] Optionally, in this embodiment, it is possible but not limited to reducing the task migration from the first task set to the second task set when the task amount parameter in each second task set is greater than the fifth threshold, that is, when the task load to be executed in each second task set is too large.

[0055] Optionally, in this embodiment, it is possible but not limited to canceling the task migration of each second task set to the third task set when the task amount parameter in the third task set is greater than the sixth threshold, that is, when the task load to be executed in each third task set is too large.

[0056] Through the above content, when there are too many tasks in the second task set and the third task set, reducing the corresponding task migration or canceling the corresponding task migration can avoid the operation burden brought by unnecessary migration to the system.

[0057] As an optional implementation manner, the reference processor is configured to execute the tasks stored in the reference task set when the reference task set is not empty; execute the tasks stored in the second task set in the processor node where the reference processor is located when the reference task set is empty and the second task set in the processor node where the reference processor is located is not empty; execute the tasks stored in the third task set when the reference task set is empty and the second task set in the processor node where the reference processor is located is empty.

[0058] Optionally, in this embodiment, when the task volume of the reference task set is greater than or equal to the seventh threshold, the reference processor executes the tasks stored in the reference task set; when the task volume of the reference task set is greater than zero and less than the seventh threshold, the reference processor alternately extracts tasks from the reference task set and the second task set in the processor node where the reference processor is located to execute; when the task volume of the reference task set is equal to zero, and the task volume of the second task set in the processor node where the reference processor is located is greater than zero and less than the eighth threshold, the reference processor alternately extracts tasks from the second task set and the third task set in the processor node where the reference processor is located to execute; when the task volume of the reference task set is equal to zero, and the task volume of the second task set in the processor node where the reference processor is located is greater than or equal to the eighth threshold, the reference processor executes the tasks stored in the second task set in the processor node where the reference processor is located. Through the above content, the reference processor can reasonably utilize its own processing resources, give priority to processing the tasks assigned by the scheduler to the reference processor, improve the cooperation degree of the system, and thus improve the processing efficiency of read / write requests / tasks.

[0059] Optionally, Figure 3 is a flowchart of a processing method for reference tasks according to an embodiment of the present application. As Figure 3 shown, it can, but is not limited to, create a thread or process by an application program to initiate a task. The scheduler (which can be the scheduler of the operating system) is responsible for allocating tasks according to policies such as load and priority. The tasks are queued in each queue (i.e., each task set) and wait for the core (i.e., the processor) to process. The scheduler of the operating system selects an idle core for the task. The task is executed on the allocated core, and during the execution process, the core allocation of other tasks to be executed may be dynamically adjusted for load balancing. The task is completed, and the result is returned and the resources are released.

[0060] As an optional implementation manner, the present application also provides an efficient storage system architecture based on SPDK (Storage Performance Development Kit). By systematically reconstructing the NVMe device control plane and optimizing the user-space I / O interaction paradigm, performance breakthroughs in the entire storage stack path are achieved. An efficient storage system architecture based on SPDK can, but is not limited to, include the following aspects:

[0061] (1) Deep optimization of user-space storage technology:

[0062] Achieve Kernel Bypass and full-stack acceleration through the SPDK user-space driver architecture:

[0063] On the one hand, through non-interrupt polling scheduling, that is, adopting the CPU affinity binding and exclusive core allocation strategies, running a 100% polling loop on dedicated CPU cores to eliminate context switching overhead, and through the design of memory isolation management, that is, constructing a physically continuous memory pool, reducing the TLB Miss (Translation Lookaside Buffer Miss) rate by 75% through pre-allocation of HugePage (large page) (2MB (Megabyte) / 1GB (Gigabyte)), while enabling direct DMA (Direct Memory Access), and through an asynchronous event channel, that is, implementing a hardware interrupt simulation mechanism in the user space, passing the status updates of storage devices through an event notification ring to avoid entering the kernel, strengthening the polling mode drive, effectively reducing the number of kernel switches; on the other hand, through the design of a lightweight TCP / IP (Transmission Control Protocol / Internet Protocol) protocol stack, that is, based on the SPDK iSCSI acceleration framework, stripping redundant protocol header processing logic to achieve zero-copy network transmission, and through the design of metadata bypass, that is, mapping file system metadata operations to an FPGA (Field-Programmable Gate Array) hardware acceleration card for processing, with the user space only handling the data plane, reconstructing the user space protocol stack to achieve a throughput of 40Gbps (Gigabits per second) line speed and reducing the metadata latency to 3μs (microsecond).

[0064] (2) Multi-core parallel acceleration system:

[0065] Design a NUMA-aware fine-grained parallel architecture to achieve linear scalability:

[0066] 1. Lock-free task distribution mechanism:

[0067] Multi-level circular queue: Construct a three-level queue (L1 (i.e., the first task set): in-core cache, L2 (i.e., the second task set): shared within the NUMA node, L3 (i.e., the third task set): cross-node global queue) in the single-producer / multi-consumer mode, and combine atomic operations to achieve lock-free synchronization, resulting in a lock contention rate < 0.1%.

[0068] Then set up a migration mechanism in queues at different levels:

[0069] L1->L2 migration: Dynamically adjust the batch migration volume based on the L1 fill rate;

[0070] batch_size (Batch transfer volume) = max(L1_FILL_RATIO (Ratio of transfer volume to total capacity) × L1_CAPACITY (Capacity of the L1 queue), MIN_BATCH (Minimum allowable transfer volume));

[0071] if (batch_size > L2_FREE_SPACE (Free space in the L2 queue)) batch_size = L2_FREE_SPACE;

[0072] L2->L3 transfer: Triggered by both time window and space threshold;

[0073] Triggered when the L2 fill rate > 60% or no transfer has occurred in the last 100 ms (milliseconds);

[0074] If there is a situation where the data in L2 is quickly consumed by local consumers on the NUMA node, the push to L3 can be delayed or cancelled to reduce unnecessary transmissions. Or when a large amount of data is suddenly generated by the producer, it is allowed to directly bypass L1 and batch-write to L2 or L3, reducing the overhead of intermediate steps.

[0075] Table 1 shows a threshold setting method for a queue transfer mechanism. As shown in Table 1, it is possible but not limited to reducing the storage of tasks to be processed in the L1 queue when the task volume in the L1 queue is greater than the high water mark of the L1 queue (i.e., the first threshold); migrating some tasks in the L1 queue to the L2 queue when the task volume in the L1 queue is greater than the low water mark of the L1 queue (i.e., the third threshold); migrating some tasks in the L2 queue to the L3 queue when the task volume in the L2 queue is greater than the low water mark of the L2 queue (i.e., the fourth threshold); restricting the migration of tasks in the L1 queue to the L2 queue when the task volume in the L2 queue is greater than or equal to the high water mark of the L2 queue (i.e., the fifth threshold); pausing the migration of tasks in the L2 queue to the L3 queue when the task volume in the L3 queue is greater than the high water mark of the L3 queue (i.e., the sixth threshold).

[0076] Table 1

[0077]

[0078] This application also sets up dynamic load feedback regulation: The load metrics of each core are collected in real time through the PMU (Performance Monitoring Unit), and the PID (Proportional-Integral-Derivative) controller is used to dynamically adjust the task shard weights, that is, to adjust the data volume of multiple requests included in a task.

[0079] Before actually processing read and write requests, this application also designs NUMA topology-aware scheduling: Based on the topological relationship between the PCIe location of the device and the CPU socket, an optimal device (i.e., storage device)-core (i.e., processor) binding matrix is constructed (based on the principle of minimizing the NUMA distance cost function), so that the cross-node access ratio is compressed to less than 5%. A secondary cache is also established within the local NUMA node, and the LRU-K (Least Recently Used-K) algorithm is used to manage hot data, so that the cache hit rate > 92%.

[0080] (III) Implementation of the I / O acceleration engine:

[0081] Construct an end-to-end zero-copy pipeline processing architecture:

[0082] This application automatically adjusts the I / O aggregation granularity according to the number of SSD parallel units (range: 64 - 256 requests / batch), and combines a priority preemption mechanism to ensure that the latency of high-priority requests < 50 μs. The host-side application / file system issues discrete I / O requests through the NVMe driver; Request receiving end: The front-end interface layer of the SSD controller (PCIe PHY (Physical Layer) + NVMe protocol parsing module); Processing execution end: Scheduler: Dynamically generates a 64 - 256 variable aggregation window according to the number of SSD parallel units (NAND channels / Chip Enable pins); Priority arbiter: Implements preemptive scheduling. When a high-priority request arrives: Freeze the current low-priority batch processing; Process high-priority requests through a dedicated fast path; Final execution body: The NAND flash management unit (FTL (Flash Translation Layer)) maps the aggregated batch operations to physical blocks:

[0083] The process of aggregating multiple IO requests into a single IO task above can be but is not limited to being implemented through the following code:

[0084] def adjust_batch_size():

[0085] if nand_channels_idle > 4 and pcie_traffic < 50%:

[0086] return 256;# Maximum throughput mode

[0087] elif cache_hit_ratio > 70%:

[0088] return 128;# Cache acceleration mode

[0089] else:

[0090] return 64; # Low-latency priority mode

[0091] # Intelligent learning module injection (predict future 3ms load based on LSTM)

[0092] if neural_engine.predict_load() == "BURSTY":

[0093] apply_prefetch_window(32); # Prefetch some requests

[0094] Regarding the handling of higher-priority IO requests, it will preempt and execute the critical path:

[0095] The hardware filter only allows high-priority requests with an interval ≤ 10μs to trigger preemption; use the Multi-Plane operation pause instruction (0x85h CMD (Command)) of the NAND controller to suspend the processing of ordinary aggregated IO requests; save the breakpoint of the current DMA transfer's PRP linked list to a dedicated cache (On-chip SRAM (On-chip Static Random Access Memory)); design hard real-time constraints: time window isolation: insert a Checkpoint (hardware-enforced checkpoint) every 50μs; worst-case latency modeling: WCL (Worst Case Latency) = (DMA pause cycle × 2) + NAND_resume_latency + PCIe_ACK_time.

[0096] To ensure that higher-priority IO requests can also be executed quickly in the storage device, it is possible but not limited to reserving storage resources in the storage device. Table 2 shows a resource reservation strategy. As shown in Table 2, it is possible but not limited to dividing the storage resources of the storage device into a preemption reservation pool dedicated to higher-priority IO requests and a regular batch provided for the aggregation of ordinary IO requests.

[0097] Table 2

[0098]

[0099] To optimize the processing speed of I / O requests, it is possible but not limited to aggregating scattered I / O requests into a single SG (Scatter-Gather) descriptor chain. A single NVMe submission SQE (Submission Queue Entry) can carry 128 LBAs (Logical Block Addressing) (the SQE utilization rate is increased by 6 times). The DMA engine in the host NVMe driver aggregates the scattered PRP List (Physical Memory Page Address) into a Scatter-Gather descriptor chain. At the protocol encapsulation end: The NVMe submission SQ Controller (Queue Controller) encapsulates the chained descriptor into a single SQE, achieving: a single SQE carrying 128 LBAs (only 21 LBAs in related solutions); the SQE payload is increased by 6 times (effectively reducing the queue depth occupancy); at the processing execution end: The command parsing unit of the SSD controller parses the SG chained structure through a hardware accelerator; during the data flow to the terminal: Write operation: Data is written into multiple parallel NAND Dies (NAND flash chips) through the on-chip SRAM (Static Random Access Memory) buffer pool; Read operation: The aggregated data block is DMA-transferred back to the host memory through the PCIe link.

[0100] Optionally, in this application, zero-copy transmission acceleration is also designed to be achieved through physical address pass-through relay and persistent memory direct write: The application buffer is directly mapped to the SPDK memory pool through mmap (Memory Map), and the NVMe DMA engine directly reads the user space data (eliminating 2 memory copies, with a bandwidth utilization rate of 98%); The PMDK library is used to implement the user-state App Direct (Application Direct) mode to access Persistent Memory (persistent memory), and the data write latency is reduced to the 300 ns (nanosecond) level.

[0101] (IV) Storage protocol and data organization innovation:

[0102] Protocol layer optimization for distributed storage and big data scenarios:

[0103] Compress the traditional 24-byte RPC (Remote Procedure Call) header to 8 bytes (retaining the opcode + sequence number), and replace the full TCP checksum with CRC32C (Cyclic Redundancy Check 32C) hardware checksum (reducing network overhead by 60%) to achieve streamlining of the RPC protocol header. Metadata compression encoding: Use the Delta Encoding + Zstandard algorithm to compress the directory tree structure, reducing the metadata volume to 15% of the original size. Adopt Adaptive Sharding: Dynamically adjust the shard size according to the number of internal parallel units in the SSD (variable granularity from 4KB to 1MB), enabling parallel writes across Dies / Planes (boosting write throughput by 4.2 times). Adopt the erasure code cold and hot tiering technology: Perform EC (Erasure Coding) encoding on cold data and store it sequentially, while keeping hot data in a multi-copy mode, reducing storage costs by 35% while ensuring that the access latency of hot data is no higher than 2ms. Utilize topology-aware data distribution: Based on an improvement of the Ceph CRUSH (Controlled Replication Under Scalable Hashing in a distributed storage system) algorithm, add hardware topology parameters such as NUMA nodes and SSD Channels, increasing the probability of local data access to 85%. Also introduce a machine learning prefetch engine: Predict the access pattern through an LSTM (Long Short-Term Memory) model and preload data into the local NUMA node cache (prefetch accuracy > 80%, boosting random read performance by 3 times).

[0104] The following is the relevant code implementation of this solution:

[0105] Implement user-mode I / O through the SPDK NVMe driver:

[0106] struct spdk_nvme_qpair *qpair = spdk_nvme_get_io_qpair(nvme_device);

[0107] spdk_nvme_cmd cmd;

[0108] cmd.opcode = SPDK_NVME_CMD_READ;

[0109] cmd.nsid = 1;

[0110] cmd.slba = lba;

[0111] cmd.dlen = data_len;

[0112] cmd.metadata_len = metadata_len;

[0113] / / Submit the command to the queue

[0114] spdk_nvme_submit_cmd(qpair, &cmd, data_buf, metadata_buf, cb_fn, cb_arg);

[0115] Implement task distribution through a lock-free circular queue:

[0116] / / Define the lock-free circular queue structure

[0117] struct ring_buffer {

[0118] uint64_t head;

[0119] uint64_t tail;

[0120] void *buffer[];

[0121] };

[0122] / / Initialize the circular queue

[0123] void init_ring_buffer(struct ring_buffer *rb, size_t size) {

[0124] rb->head = 0;

[0125] rb->tail = 0;

[0126] / / Allocate memory and initialize the buffer

[0127] }

[0128] / / The producer adds tasks to the queue

[0129] bool enqueue_task(struct ring_buffer *rb, void *task) {

[0130] uint64_t next_head = (rb->head + 1) % RING_BUFFER_SIZE;

[0131] if (next_head == rb->tail) {

[0132] / / The queue is full, return failure

[0133] return false;

[0134] }

[0135] rb->buffer[rb->head] = task;

[0136] rb->head = next_head;

[0137] return true;

[0138] }

[0139] / / The consumer retrieves a task from the queue

[0140] bool dequeue_task(struct ring_buffer *rb, void **task) {

[0141] if (rb->head == rb->tail) {

[0142] / / The queue is empty, return failure

[0143] return false;

[0144] }

[0145] *task = rb->buffer[rb->tail];

[0146] rb->tail = (rb->tail + 1) % RING_BUFFER_SIZE;

[0147] return true;

[0148] }

[0149] Each CPU core has an independent task queue. The system distributes tasks to each queue through polling or load balancing algorithms:

[0150] / / Multi-core task distribution

[0151] void distribute_task(void *task, struct ring_buffer **queues, intnum_cores) {

[0152] / / Select the target core according to the current load

[0153] int target_core = select_target_core(queues, num_cores);

[0154] enqueue_task(queues[target_core], task);

[0155] }

[0156] int select_target_core(struct ring_buffer **queues, int num_cores){

[0157] / / Polling algorithm

[0158] static int current_core = 0;

[0159] return current_core++;

[0160] }

[0161] Through the above solution, through the innovation of the full-stack architecture and deep hardware collaboration, an order-of-magnitude improvement is achieved in dimensions such as performance, resource efficiency, and reliability.

[0162] From the description of the above implementation manners, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation manner.

[0163] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0164] The above has introduced in detail a processor system provided by the present application. Specific examples are used in this text to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A processor system, characterized in that, Including: Multiple processor nodes, a scheduler, and a system storage space. Each processor node includes one or more processors and a node storage space. Each of the processors has a processor storage space, in which a first task set is constructed, a second task set is constructed in the node storage space, and a third task set is constructed in the system storage space; The scheduler is configured to screen out a reference processor corresponding to a received reference task from the processors; screen out a target task set from a candidate task set according to the task amount information of the reference task set, where the reference task set is the first task set in the processor storage space of the reference processor, and the candidate task set includes: the reference task set, the second task set in the processor node where the reference processor is located, and the third task set; distribute the reference task to the target task set; The reference processor is configured to execute the tasks stored in the candidate task set.

2. The processor system according to claim 1, wherein The processor system further includes a plurality of storage devices; The scheduler is configured to match a corresponding processor for a target storage device from the processors and storage devices with a corresponding relationship to obtain the reference processor, where the target storage device is the storage device requested to be accessed by the reference task among the plurality of storage devices; The scheduler is configured to detect a first state of the reference task set indicated by the task amount information; in the case where the first state is that the task amount of the reference task set is less than a first threshold, determine the reference task set as the target task set; in the case where the first state is that the task amount of the reference task set is greater than or equal to the first threshold, detect a second state of the second task set in the processor node where the reference processor is located; in the case where the second state is that the task amount of the second task set in the processor node where the reference processor is located is less than a second threshold, determine the second task set in the processor node where the reference processor is located as the target task set; in the case where the second state is that the task amount of the second task set in the processor node where the reference processor is located is greater than or equal to the second threshold, determine the third task set as the target task set.

3. The processor system according to claim 2, wherein The scheduler is further configured to aggregate a plurality of the processing requests into one or more processing tasks according to the request information of the processing requests and the processing information of each of the storage devices, where the one or more processing tasks include the reference task, the request information is used to indicate the storage device requested to be accessed by the processing request, the request information corresponding to the processing requests included in the processing task is the same, and the processing information is used to indicate the data access capabilities of each of the storage devices.

4. The processor system according to claim 3, wherein A fourth task set is also constructed in the processor storage space; The scheduler is further configured to detect the processing priority of each of the processing requests before aggregating the multiple processing requests into one or more processing tasks according to the request information of the processing requests and the processing information of each of the storage devices, where the processing priority is used to indicate the importance level of the processing request; in the case that the processing priority of the target request is detected to indicate that the importance level of the target request is higher than a level threshold, distribute the target request to the priority task set, where each of the processing requests includes the target request, and the priority task set is the fourth task set in the processor storage space of the target processor corresponding to the target request; The target processor is configured to, when the priority task set is not empty, preferentially execute the tasks stored in the priority task set; after the tasks stored in the priority task set are executed, execute the tasks stored in the first task set in the processor storage space of the target processor, or the tasks stored in the second task set in the processor node where the target processor is located, or the tasks stored in the third task set.

5. The processor system according to claim 1, wherein The scheduler is further configured to detect the data volume of the data requested to be accessed by the reference task; in the case that the data volume is greater than a data volume threshold, screen out the target task set from the alternative task set, where the alternative task set includes: the second task set and the third task set in the processor node where the reference processor is located; in the case that the data volume is less than or equal to the data volume threshold, perform the step of screening out the target task set from the candidate task set according to the task volume information of the reference task set.

6. The processor system according to claim 1, wherein The processor system further includes a regulator; The regulator is configured to, in the case that the task volume parameter in the first adjustment set in each of the first task sets is greater than a third threshold, migrate some of the tasks stored in the first adjustment set to the second task set in the same processor node as the first adjustment set, where the task volume parameter is used to indicate the task volume of the tasks currently stored in the corresponding task set, and the task sets include the first task set, the second task set, and the third task set.

7. The processor system according to claim 6, wherein The regulator is further configured to, in the case that the task volume parameter in the second adjustment set in each of the second task sets is greater than a fourth threshold, migrate some of the tasks stored in the second adjustment set to the third task set.

8. The processor system according to claim 7, wherein The regulator is further configured to detect a change parameter in the second adjustment set, where the change parameter is used to indicate the speed at which the tasks stored in the second adjustment set are executed; in the case where it is detected that the change parameter is used to indicate that the speed at which the tasks stored in the second adjustment set are executed is higher than a speed threshold, cancel or delay the execution of the step of migrating some of the tasks stored in the second adjustment set to the third task set.

9. The processor system according to claim 7, wherein the regulator is further configured to reduce the migration amount of tasks migrated to the third adjustment set when the task amount parameter in the third adjustment set in each of the second task sets is greater than or equal to a fifth threshold, where the fifth threshold is greater than the fourth threshold; the regulator is further configured to cancel migrating tasks to the third task set when the task amount parameter in the third task set is greater than or equal to a sixth threshold.

10. The processor system according to claim 1, wherein the reference processor is configured to execute the tasks stored in the reference task set when the reference task set is not empty; execute the tasks stored in the second task set in the processor node where the reference processor is located when the reference task set is empty and the second task set in the processor node where the reference processor is located is not empty; and execute the tasks stored in the third task set when the reference task set is empty and the second task set in the processor node where the reference processor is located is empty.

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