Forward error correction coding circuit and FPGA chip
By adopting alternating writing and parallel processing in the FEC encoding circuit, the problem of inefficient encoding efficiency of traditional FEC encoder is solved, and efficient data processing and stable high-speed FEC encoding are realized.
Patent Information
- Application Number
- CN202510186260.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-19
- Publication Date
- 2025-07-04
AI Technical Summary
Traditional FEC encoder based on hard-core logic has low encoding efficiency due to serial processing mode, making it difficult to meet the high-speed FEC encoding requirements.
Two storage modules are used to write the data to be encoded alternately and process it in parallel. Two independent encoding modules are used to process the data read by the storage module separately. By setting an alternating read and write mechanism with different clock frequencies, data continuity and efficient processing are achieved.
It improves encoding efficiency and encoding rate, meets the requirements of high-speed FEC encoding, and reduces energy consumption and error rates, ensuring the stability and reliability of the system.
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Figure CN120263196A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of signal fitting processing, and specifically relates to a forward error correction coding circuit and an FPGA chip. Background Art
[0002] Forward error correction (FEC) coding is one of the important mechanisms to ensure the reliability of data transmission. With the continuous growth of data transmission rate, the demand for efficient and fast FEC encoders is also increasing. However, traditional FEC encoders based on hard-core logic often adopt a frame-by-frame processing method. This serial processing mode leads to low coding efficiency, especially in the case of needing to process a large amount of data streams in real time, and because of the low coding efficiency, traditional FEC encoders are difficult to meet the requirements of high-speed FEC coding. Summary of the Invention
[0003] In view of the above problems, the present application provides a forward error correction coding circuit and an FPGA chip to solve the above technical problems.
[0004] In a first aspect, a forward error correction coding circuit provided by the present application includes:
[0005] A first storage module and a second storage module, both of which are used to write the data to be encoded according to a first clock frequency and read the data to be encoded according to a second clock frequency, wherein the data to be encoded is alternately written into the first storage module and the second storage module in frames;
[0006] A first coding module, which is used to receive the data to be encoded read by the first storage module according to the second clock frequency and encode it into first encoded data, and output the first encoded data according to the second clock frequency;
[0007] A second coding module, which is used to receive the data to be encoded read by the second storage module according to the second clock frequency and encode it into second encoded data, and output the second encoded data according to the second clock frequency;
[0008] A third storage module, which is used to write the first encoded data according to the second clock frequency and read the first encoded data according to the first clock frequency;
[0009] A fourth storage module, which is used to write the second encoded data according to the second clock frequency and read the second encoded data according to the first clock frequency;
[0010] The first clock frequency is twice the second clock frequency.
[0011] In a second aspect, the present application provides an FPGA chip, which includes the forward error correction coding circuit described in the first aspect above.
[0012] The forward error correction coding circuit and FPGA chip provided by this application set the first storage module and the second storage module to alternately write the data to be encoded frame by frame according to the first clock frequency, and continuously read the data to be encoded according to the second clock frequency. At the same time, two independent first coding modules and second coding modules are used to process the data received from the first storage module and the second storage module in parallel, solving the problems of low data processing efficiency in the traditional single clock frequency architecture and the coding bottleneck caused by a single coding module, realizing efficient data processing, improving the coding efficiency and coding rate, and meeting the high-speed FEC coding requirements. Description of the Drawings
[0013] In order to more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0014] Figure 1 Shows a schematic diagram of the forward error correction coding circuit provided by the embodiment of this application.
[0015] Figure 2 Shows a timing diagram of the forward error correction coding circuit provided by the embodiment of this application.
[0016] Figure 3 Shows another schematic diagram of the forward error correction coding circuit provided by the embodiment of this application.
[0017] Figure 4 Shows another schematic diagram of the forward error correction coding circuit provided by the embodiment of this application.
[0018] Figure 5 Shows another schematic diagram of the forward error correction coding circuit provided by the embodiment of this application.
[0019] Figure 6 Shows another schematic diagram of the forward error correction coding circuit provided by the embodiment of this application.
[0020] Figure 7 Shows another schematic diagram of the forward error correction coding circuit provided by the embodiment of this application.
[0021] Figure 8 Shows another schematic diagram of the forward error correction coding circuit provided by the embodiment of this application.
[0022] Figure 9 Shows another timing diagram of the forward error correction coding circuit provided by the embodiment of this application. Detailed Embodiments
[0023] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.
[0024] In the embodiments of the present application, it should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
[0025] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents an "or" relationship between the associated objects before and after.
[0026] It should be pointed out that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection of two electrical components can be a direct or indirect connection between the two electrical components. For example, when A is connected to B, it can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.
[0027] In programmable logic devices, encoders based on hard-core logic are widely used for FEC encoding operations, and they usually adopt a frame-by-frame processing mode for encoding operations. This means that each frame of data must be encoded in sequence before the data processing of the next frame can start. This serial processing method greatly limits the overall throughput and real-time processing ability of the system. Therefore, traditional hard-core logic-based FEC encoders are difficult to meet the high-speed FEC encoding requirements. In view of this, there have been some attempts in the industry to improve the encoding efficiency by optimizing the encoder architecture. For example, some solutions optimize the architecture of the hard-core logic in order to increase the encoding rate. Another example is that some solutions attempt to achieve higher encoding flexibility through software-defined methods, but these methods often require high resource consumption, increase the design complexity of the system, and may increase challenges in terms of compatibility and stability during actual deployment.
[0028] In view of the above technical problems, the embodiments of the present application provide a forward error correction coding circuit. Figure 1 The schematic diagram of the forward error correction coding circuit provided by the embodiments of the present application is shown, as Figure 1As shown in the figure, the forward error correction coding circuit provided by the embodiment of the present application includes a first storage module Ram1, a first coding module Encode1, and a third storage module Ram3 that are connected in sequence; and a second storage module Ram2, a second coding module Encode2, and a fourth storage module Ram4 that are arranged in parallel with the first storage module Ram1, the first coding module Encode1, and the third storage module Ram3.
[0029] Among them, the first storage module is configured to write the data to be encoded according to the first clock frequency and read the data to be encoded according to the second clock frequency. The first coding module is configured to receive the data to be encoded read by the first storage module according to the second clock frequency, encode it into the first encoded data, and output the first encoded data according to the second clock frequency. The third storage module is configured to write the first encoded data according to the second clock frequency and read the first encoded data according to the first clock frequency. The second storage module is configured to write the data to be encoded according to the first clock frequency and read the data to be encoded according to the second clock frequency. The data to be encoded is configured to be alternately written into the first storage module and the second storage module in frames. The second coding module is configured to receive the data to be encoded read by the second storage module according to the second clock frequency, encode it into the second encoded data, and output the second encoded data according to the second clock frequency. The fourth storage module is configured to write the second encoded data according to the second clock frequency and read the second encoded data according to the first clock frequency.
[0030] Figure 2 The timing diagram of the forward error correction coding circuit provided by the embodiment of the present application is shown. Next, in combination with Figure 1 and Figure 2 the working principle of the forward error correction coding circuit provided by the embodiment of the present application will be described. As Figure 1 and Figure 2As shown, the data to be encoded transmitted by the external circuit is continuously input to the forward error correction coding circuit in frames. The first storage module Ram1 writes the first frame of data to be encoded at the first clock frequency Clk1. At the same time, the first storage module Ram1 also reads the first frame of data to be encoded at the second clock frequency Clk2 and sends the first frame of data to be encoded to the first encoding module Encode1 for encoding. Since the first clock frequency Clk1 for data writing is twice the second clock frequency Clk2 for data reading, when the first storage module Ram1 reads the first frame of data to be encoded, the second storage module Ram2 also starts writing the second frame of encoded data at the first clock frequency Clk1. When the second storage module Ram2 writes the second frame of data to be encoded, it also reads the second frame of encoded data at the second clock frequency Clk2 and sends the second frame of encoded data to the second encoding module Encode2 for encoding. And so on. The first storage module Ram1 and the second storage module Ram2 alternately write the data to be encoded transmitted by the external circuit in frames to continuously process the data to be encoded, thereby improving the data processing efficiency of the forward error correction coding circuit. After the first encoding module Encode1 and the second encoding module Encode2 encode the data to be encoded in the current frame, they respectively read the first encoded data and the second encoded data at the second clock frequency Clk2. After encoding is completed, the third storage module Ram3 and the fourth storage module Ram4 write the first encoded data and the second encoded data at the second clock frequency Clk2 respectively, so as to be synchronized with the clock frequencies of the first encoding module Encode1 and the second encoding module Encode2. To improve the reading efficiency of the encoded data, the third storage module Ram3 and the fourth storage module Ram4 do not need to wait until all the encoded data is written before reading the data, but read the encoded data at the first clock frequency Clk1 and the second clock frequency Clk2 after the first encoded data and the second encoded data are written to achieve continuous data stream processing.
[0031] It can be understood that the specific values of the first clock frequency and the second clock frequency are not limited in the embodiments of the present application. That is, the forward error correction coding circuit provided in the embodiments of the present application can be applied to low-speed FEC coding operations and can also be applied to high-speed FEC coding operations. Preferably, the forward error correction coding circuit provided in the embodiments of the present application is applied to high-speed FEC coding operations to achieve high-speed FEC coding with fewer resources occupied.
[0032] The forward error correction coding circuit provided by the embodiment of the present application, in view of the technical problem that the traditional hard-core logic-based FEC encoder limits the coding efficiency due to the serial processing mode based on fixed frames, sets the first storage module and the second storage module to alternately write the data to be encoded frame by frame according to the first clock frequency, and continuously reads the data to be encoded according to the second clock frequency. At the same time, two independent first coding modules and second coding modules are used to process the data received from the first storage module and the second storage module in parallel. Finally, the encoded data is read out through the third storage module and the fourth storage module respectively. In the forward error correction coding circuit with this architecture, the first storage module and the second storage module can work alternately. When the first storage module is writing a new frame of data to be encoded, the second storage module reads out a previously written frame of data to be encoded and sends it to the second coding module for processing. Then, in the next cycle, the first storage module and the second storage module swap roles. The first storage module that originally wrote the data to be encoded is now used to output the data to be encoded and send it to the first coding module for processing, while the original second storage module starts to receive a new frame of data to be encoded. This mechanism ensures the continuity of the data stream because it avoids conflicts or delays that may be caused by performing write and read operations on the same storage area simultaneously at the same time. In this way, the forward error correction coding circuit can reduce energy consumption while maintaining high efficiency, and due to the lower frequency read operations, it can also reduce the error rate caused by frequent access to the memory. In this way, the entire forward error correction coding circuit can not only maintain a high throughput, meet the high-speed FEC coding requirements, but also ensure stability and reliability.
[0033] In addition, for the forward error correction coding circuit provided by the embodiment of the present application, since the technical problem that the serial processing mode based on fixed frames of the traditional hard-core logic-based FEC encoder limits the coding efficiency is solved through a parallel transmission architecture, in the forward error correction coding circuit provided by the embodiment of the present application, the first coding module and the second coding module can also use the coding modules in the traditional hard-core logic-based FEC encoder, so that there is no need to re-design the coding modules. In this way, not only the functional characteristics of the original coding modules are retained, the circuit design cost is saved, but also the coding efficiency and data processing ability of the overall system are significantly improved.
[0034] In some embodiments, in the forward error correction encoding circuit provided by the embodiments of the present application, the first storage module Ram1, the second storage module Ram2, the third storage module Ram3, and the fourth storage module Ram4 are all dual-port random access memories (Dual-Port Random Access Memory, DPRAM). Optionally, a dual-port random access memory allows read and write operations to be performed simultaneously from two different addresses at the same time, which means that in the embodiments of the present application, when dealing with complex encoding tasks, such as forward error correction encoding (FEC) that requires frequent data exchange, the dual-port RAM can support more efficient parallel processing capabilities. For example, when one port of the storage module is writing a new data stream, the other port can simultaneously read out the processed data and send it to the next processing stage, thereby further improving the data processing efficiency of the forward error correction encoding circuit. In addition, since each port of the dual-port random access memory can be independently controlled, a certain port can be configured or adjusted without affecting the operations of other ports, thus providing greater design freedom for the forward error correction encoding circuit to optimize the management of the data stream. Further, the forward error correction encoding circuit provided by the embodiments of the present application uses two sets of buffers to work alternately to ensure the continuity of the data stream, and using a dual-port random access memory can further enhance the data throughput and data processing efficiency of the forward error correction encoding circuit without increasing additional hardware complexity, which not only ensures the continuity of data processing but also further improves the response speed of the entire forward error correction encoding circuit.
[0035] In some embodiments, in the forward error correction encoding circuit provided by the embodiments of the present application, the first storage module Ram1, the second storage module Ram2, the third storage module Ram3, and the fourth storage module Ram4 are all single data rate dual-port random access memories (Single Data Rate Dual-Port Random Access Memory).
[0036] In some embodiments, Figure 3 Another schematic diagram of the forward error correction encoding circuit provided by the embodiments of the present application is shown. As Figure 3 shown, the forward error correction encoding circuit provided by the embodiments of the present application further includes a control module Control, and the control module Control is configured to:
[0037] Output a first write enable Wren1 signal to the first storage module Ram1, control the first storage module Ram1 to write the data to be encoded according to the first write enable Wren1 signal, and when the first write enable Wren1 signal is activated, the first storage module Ram1 starts to write the data to be encoded into its memory space.
[0038] Output the first read enable signal Rden1 to the first storage module Ram1, and control the first storage module Ram1 to read the data to be encoded one clock cycle after the data to be encoded is written. By controlling the timing of writing and reading data of the first storage module Ram1, it ensures that there is enough stable time after the data to be encoded is written, thus avoiding the risk of incomplete or damaged data to be encoded caused by premature reading.
[0039] Output the second write enable signal Wren2 to the second storage module Ram2, and control the second storage module Ram2 to write the data to be encoded according to the second write enable signal Wren2. When the second write enable signal Wren2 is activated, the second storage module Ram2 starts to write the data to be encoded into its memory space.
[0040] Output the second read enable signal Rden2 to the second storage module Ram2, and control the second storage module Ram2 to read the data to be encoded one clock cycle after the data to be encoded is written. By controlling the timing of writing and reading data of the second storage module Ram2, it ensures that there is enough stable time after the data to be encoded is written, thus avoiding the risk of incomplete or damaged data to be encoded caused by premature reading.
[0041] In some embodiments, the first write enable signal Wren1, the second write enable signal Wren2, the first read enable signal Rden1, and the second read enable signal Rden2 are all level signals.
[0042] It can be understood that controlling the read and write operations of the storage module through the enable signal is an existing and mature technology, and its basic principle and working mechanism are well-known to those skilled in the art. For example, the control module can generate the enable signal through a state machine, timing logic, programming, etc. to control the write and read operations of each storage module. And the purpose of the embodiments of the present application is to control the timing of writing and reading operations of the data to be encoded, rather than to elaborate or innovate on the control module itself.
[0043] In some embodiments, Figure 4 shows another schematic diagram of the forward error correction coding circuit provided by the embodiments of the present application. As Figure 4 shown, in the forward error correction coding circuit provided by the embodiments of the present application, the control module Control is further configured to:
[0044] Output a third write enable signal Wren3 to the third storage module Ram3, control the third storage module Ram3 to write the first encoded data according to the third write enable signal Wren3, and output a third read enable signal Rden3 to the third storage module Ram3. Control the third storage module Ram3 to read the first encoded data after more than half of the first encoded data is written. Thus, by delaying the reading, it is ensured that there is enough data volume of a frame of the first encoded data to be stored before starting the reading process, avoiding problems of incomplete data or low processing efficiency caused by premature reading.
[0045] Output a fourth write enable signal Wren4 to the fourth storage module Ram4, control the fourth storage module Ram4 to write the second encoded data according to the fourth write enable signal Wren4, and output a fourth read enable signal Rden4 to the fourth storage module Ram4. Control the fourth storage module Ram4 to read the second encoded data after more than half of the second encoded data is written. Thus, by delaying the reading, it is ensured that there is enough data volume of a frame of the second encoded data to be stored before starting the reading process, avoiding problems of incomplete data or low processing efficiency caused by premature reading.
[0046] In some preferred embodiments, Figure 5 Another schematic diagram of the forward error correction coding circuit provided by the embodiment of the present application is shown. As Figure 5 shown, the forward error correction coding circuit further includes:
[0047] A first buffer module Rse1, connected to the first storage module Ram1 and the first encoding module Encode1 respectively, for receiving the data to be encoded read by the first storage module Ram1 at the second clock frequency Clk2 and buffer-transmitting the data to be encoded to the first encoding module Encode1 at the second clock frequency Clk2.
[0048] A second buffer module Rse2, connected to the second storage module Ram2 and the second encoding module Encode2 respectively, for receiving the data to be encoded read by the second storage module Ram2 at the second clock frequency Clk2 and buffer-transmitting the data to be encoded to the second encoding module Encode2 at the second clock frequency Clk2.
[0049] In some embodiments, the forward error correction coding circuit provided by the embodiment of the present application includes the first buffer module Rse1 or the second buffer module Rse2.
[0050] In the forward error correction coding circuit provided by the embodiment of the present application, the first storage module, the first coding module, and the third storage module form a combinational logic circuit, and the second storage module, the second coding module, and the fourth storage module form a combinational logic circuit. The combinational logic circuit is directly connected by logic gates, and the signal transmission path is too long. Therefore, the propagation delay of the signal on the transmission path may exceed the clock cycle, resulting in the data not being stable when the clock edge arrives, thus violating the setup time requirement. In view of this, in the embodiment of the present application, a first buffer module is inserted between the first storage module and the first coding module, and a second buffer module is inserted between the second storage module and the second coding module, so as to divide the long path into multiple short path segments, so that the delay of each short path segment is controlled within an acceptable range, thereby meeting the data stability requirement when the clock edge arrives.
[0051] In some preferred embodiments, Figure 6 Another schematic diagram of the forward error correction coding circuit provided by the embodiment of the present application is shown. As Figure 6 shown, the forward error correction coding circuit further includes:
[0052] A third buffer module Rse3, connected to the third storage module Ram3, for receiving the first coded data read by the third storage module Ram3 at the first clock frequency Clk1 and buffering and outputting the first coded data at the first clock frequency Clk1.
[0053] A fourth buffer module Rse4, connected to the fourth storage module Ram4, for receiving the second coded data read by the fourth storage module Ram4 at the first clock frequency Clk1 and buffering and outputting the second coded data at the first clock frequency Clk1.
[0054] In some embodiments, the forward error correction coding circuit provided by the embodiment of the present application includes the third buffer module Rse3 or the fourth buffer module Rse4.
[0055] In the embodiment of the present application, a third buffer module is inserted between the third storage module and the module that subsequently receives the first coded signal, and a fourth buffer module is inserted between the fourth storage module and the module that subsequently receives the second coded signal, thereby further dividing the long path of the combinational logic circuit, further reducing the delay of each short path segment, and optimizing the data stability requirement when the clock edge arrives.
[0056] In some embodiments, the first buffer module Rse1, the second buffer module Rse2, the third buffer module Rse3, and the fourth buffer module Rse4 are all register devices.
[0057] In some embodiments, Figure 7 Another schematic diagram of the forward error correction coding circuit provided by the embodiment of the present application is shown. AsFigure 7 As shown, the forward error correction coding circuit further includes:
[0058] A selection output module Mux, configured to receive the first coded data and the second coded data, and control the output of the first coded data or the second coded data according to an external selection signal Sel.
[0059] In some embodiments, the external selection signal Sel is a level signal, so as to control the output of the first coded data at the first level and control the output of the second coded data at the second level, where the first level is one of a high level or a low level, and the second level is the other of a high level or a low level.
[0060] In some embodiments, the selection output module Mux controls the alternating output of the first coded data and the second coded data.
[0061] In some embodiments, the selection output module Mux is a multiplexer device.
[0062] In some embodiments, Figure 8 Another schematic diagram of the forward error correction coding circuit provided by the embodiment of the present application is shown. As Figure 8 shown, the forward error correction coding circuit further includes:
[0063] A data verification module Data_Check, configured to receive the first coded data or the second coded data output by the selection output module Mux, verify the first coded data or the second coded data, and output a verification result. Optionally, the verification result Result output by the data verification module Data_Check is a level signal. For example, when the received coded data is incorrect, the verification result Result is a high level, and when the received coded data is correct, the verification result Result is a low level.
[0064] It should be clear that verifying the coded data is a mature solution in the prior art. Therefore, the embodiment of the present application does not limit the specific implementation manner of the data verification module.
[0065] In some embodiments, the forward error correction coding circuit provided by the embodiment of the present application is applied to high-speed coding, the first clock frequency Clk1 is 440 MHZ, and the second clock frequency Clk2 is 220 MHZ.
[0066] In some embodiments, in the forward error correction coding circuit provided by the embodiment of the present application, the first coding module Encode1 and the second coding module Encode2 are configured to perform coding operations on the data to be coded in accordance with the forward error correction coding method.
[0067] Exemplarily, taking the RS544 encoding as an example, the forward error correction encoding circuit provided by the embodiments of the present application is described. The RS544 encoding is a type of forward error correction encoding. Figure 9 Another timing diagram of the forward error correction encoding circuit provided by the embodiments of the present application is shown, as Figure 8 and Figure 9As shown, the data to be encoded transmitted by the external circuit is continuously input to the forward error correction encoding circuit in frames. The first storage module Ram1 writes the first frame of data to be encoded at 440 MHz. After one clock cycle, the first storage module Ram1 reads the first frame of data to be encoded at 220 MHz and sends the first frame of data to be encoded to the first encoding module Encode1. Since the data writing frequency of 440 MHz is twice the data reading frequency of 220 MHz, when the first storage module Ram1 reads the first frame of data to be encoded, the second storage module Ram2 also starts writing the second frame of data to be encoded at 440 MHz. After one clock cycle, while the second storage module Ram2 writes the second frame of data to be encoded, it also reads the second frame of encoded data at 220 MHz and sends the second frame of encoded data to the second encoding module Encode2. And so on, the first storage module Ram1 and the second storage module Ram2 alternately write the data to be encoded transmitted by the external circuit in frames to continuously process the data to be encoded. After the first encoding module Encode1 and the second encoding module Encode2 complete encoding, the third storage module Ram3 and the fourth storage module Ram4 write the first encoded data and the second encoded data at 220 MHz respectively, and read the first encoded data and the second encoded data at 440 MHz. Because the read clock of the third storage module Ram3 and the fourth storage module Ram4 is greater than the write clock, after more than half of a frame of the first encoded data and a frame of the second encoded data are written into the third storage module Ram3 and the fourth storage module Ram4 respectively, the first encoded data and the second encoded data start to be read. For the RS544 encoding method, one frame of data includes 34 clock cycles. Therefore, the third storage module Ram3 and the fourth storage module Ram4 start reading the encoded data after more than 17 clock cycles. Optionally, the first encoding module is an encoding module implemented based on the RS(544,514) encoding rule or the RS(528,514) encoding rule to perform RS544 encoding on the data to be encoded, and the second encoding module is an encoding module implemented based on the RS(544,514) encoding rule or the RS(528,514) encoding rule to perform RS544 encoding on the data to be encoded. The RS(544,514) encoding rule and the RS(528,514) encoding rule define how to convert the original data to be encoded into encoded data containing redundant check information to detect and correct errors during transmission. The RS(544,514) encoding rule defines that each frame of data consists of 544 symbols, of which 514 are information symbols (i.e., the actual data to be transmitted), and the remaining 30 symbols are redundant symbols used for error correction. It can correct up to 15 symbol errors. The RS(528,514) encoding rule defines that each frame of data consists of 528 symbols, of which 514 are information symbols and 14 are redundant symbols. It can correct up to 7 symbol errors.
[0068] It can be understood that for the forward error correction coding circuit provided in the embodiments of the present application, for different types of forward error correction coding methods, the first coding module and the second coding module will implement using coding rules corresponding to the coding methods.
[0069] In view of the technical problem that the traditional hard-core logic-based FEC encoder limits the coding efficiency due to the serial processing mode based on a fixed frame, the forward error correction coding circuit provided in the embodiments of the present application sets the first storage module and the second storage module to alternately write the data to be coded frame by frame according to the first clock frequency, and continuously read the data to be coded according to the second clock frequency. At the same time, two independent first coding modules and second coding modules are used to process the data received from the first storage module and the second storage module in parallel. Finally, the coded data is read out through the third storage module and the fourth storage module respectively. The forward error correction coding circuit under this architecture enables the first storage module and the second storage module to work alternately, ensuring the continuity of the data stream and avoiding conflicts or delays that may be caused by performing write and read operations on the same storage area at the same time. In this way, the forward error correction coding circuit can reduce energy consumption while maintaining high efficiency, and due to the lower frequency read operation, it can also reduce the error rate caused by frequent access to the memory. In this way, the entire forward error correction coding circuit can not only maintain a high throughput, meet the high-speed FEC coding requirements, but also ensure stability and reliability.
[0070] The embodiments of the present application also provide an FPGA chip, which includes the above-mentioned forward error correction coding circuit.
[0071] FPGA (Field-Programmable Gate Array) chips are a type of integrated circuit composed of a large number of programmable logic units (CLBs, Configurable Logic Blocks), which can be used to implement various logic functions. There is a complex programmable interconnect network inside the FPGA. Through these interconnect networks, the logic units can be connected to achieve the required circuit functions. The FPGA contains programmable I / O modules for communicating with external devices. The FPGA also contains various types of storage units, such as RAM, ROM, etc., for storing data and configuration information. The core advantage of the FPGA lies in its programmability. Using a hardware description language (HDL) such as VHDL or Verilog, designers can define the required circuit functions. Then, through a synthesis tool, these descriptions are converted into a configuration file that can be implemented on the FPGA. After the configuration file is loaded into the FPGA, the logic units and interconnect networks of the FPGA will be configured according to the designer's requirements, thus achieving specific circuit functions. That is, in the FPGA chip provided by the embodiments of the present application, the forward error correction coding circuit can be implemented in the form of a SOFT IP. Specifically, some or all of the modules in the forward error correction coding circuit can be implemented by configuring the FPGA through a hardware description language.
[0072] For the chip provided by the embodiments of the present application, the forward error correction coding circuit in the chip can improve the coding rate by sacrificing only a small amount of logic resources compared to the problem that traditional encoders in the FPGA are difficult to meet the high-speed FEC coding requirements. Another coding method in the FPGA can also improve the coding rate by means of pipelining, but the pipelining coding consumes a large amount of resources compared to the forward error correction coding circuit provided by the embodiments of the present application. The following table shows the resource consumption comparison of the forward error correction coding circuit, traditional encoder, and pipelining coding provided by the embodiments of the present application in the FPGA chip:
[0073]
[0074] It can be understood that the above table only shows the resource consumption comparison of the forward error correction coding circuit, traditional encoder, and pipelining coding provided by the embodiments of the present application on an existing FPGA platform. For different FPGA platforms, the resource consumption of the three will vary from the above table based on the design optimization of different FPGA platforms. Even for the same FPGA platform, the resource consumption of the three may also vary from the above table due to errors.
[0075] The above content is a further detailed description of the present application in combination with specific implementation manners. It cannot be determined that the specific implementation of the present application is only limited to these descriptions. For those of ordinary skill in the technical field to which the present application pertains, without departing from the concept of the present application, several simple deductions or substitutions can still be made, which should all be regarded as the protection scope of the present application.
Claims
1. A forward error correction coding circuit, characterized in that, Including: A first storage module and a second storage module, both of which are used to write the data to be encoded according to a first clock frequency and read the data to be encoded according to a second clock frequency, wherein the data to be encoded is alternately written into the first storage module and the second storage module in frames; A first encoding module, which is used to receive the data to be encoded read by the first storage module according to the second clock frequency and encode it into first encoded data, and output the first encoded data according to the second clock frequency; A second encoding module, which is used to receive the data to be encoded read by the second storage module according to the second clock frequency and encode it into second encoded data, and output the second encoded data according to the second clock frequency; A third storage module, which is used to write the first encoded data according to the second clock frequency and read the first encoded data according to the first clock frequency; A fourth storage module, which is used to write the second encoded data according to the second clock frequency and read the second encoded data according to the first clock frequency; The first clock frequency is twice the second clock frequency.
2. The forward error correction encoding circuit according to claim 1, wherein: The first storage module, the second storage module, the third storage module and the fourth storage module are all dual-port random access memories.
3. The forward error correction coding circuit according to claim 2, wherein It further includes a control module, and the control module is configured to: Output a first write enable signal to the first storage module, control the first storage module to write the data to be encoded according to the first write enable signal, and output a first read enable signal to the first storage module, and control the first storage module to read the data to be encoded one clock cycle after the data to be encoded is written according to the first read enable signal; Output a second write enable signal to the second storage module, control the second storage module to write the data to be encoded according to the second write enable signal, and output a second read enable signal to the first storage module, and control the second storage module to read the data to be encoded one clock cycle after the data to be encoded is written according to the second read enable signal.
4. The forward error correction coding circuit according to claim 2, wherein, The control module is further configured to: Output a third write enable signal to the third storage module, control the third storage module to write the first encoded data according to the third write enable signal, and output a third read enable signal to the third storage module, and control the third storage module to read the first encoded data after more than half of the first encoded data is written according to the third read enable signal; Output a fourth write enable signal to the fourth storage module, control the fourth storage module to write the second encoded data according to the fourth write enable signal, and output a fourth read enable signal to the fourth storage module, and control the fourth storage module to read the second encoded data after more than half of the second encoded data is written according to the fourth read enable signal.
5. The forward error correction coding circuit according to claim 1, wherein It further includes: The first buffer module, which is respectively connected to the first storage module and the first encoding module, is configured to receive the data to be encoded read by the first storage module at the second clock frequency, and buffer and transmit the data to be encoded to the first encoding module at the second clock frequency; and / or The second buffer module, which is respectively connected to the second storage module and the second encoding module, is configured to receive the data to be encoded read by the second storage module at the second clock frequency, and buffer and transmit the data to be encoded to the second encoding module at the second clock frequency.
6. The forward error correction coding circuit according to claim 1, wherein It further includes: The third buffer module, which is connected to the third storage module, is configured to receive the first encoded data read by the third storage module at the first clock frequency, and buffer and output the first encoded data at the first clock frequency; and / or The fourth buffer module, which is connected to the fourth storage module, is configured to receive the second encoded data read by the fourth storage module at the first clock frequency, and buffer and output the second encoded data at the first clock frequency.
7. The forward error correction coding circuit according to claim 1, wherein, It further includes: The selection output module, which is configured to receive the first encoded data and the second encoded data, and control the output of the first encoded data or the second encoded data according to an external selection signal.
8. The forward error correction coding circuit according to claim 7, wherein It further includes: The data verification module, which is configured to receive the first encoded data or the second encoded data output by the selection output module, verify the first encoded data or the second encoded data, and output a verification result.
9. The forward error correction coding circuit according to claim 1, characterized in that The first clock frequency is 440 MHZ, and the second clock frequency is 220 MHZ.
10. The forward error correction coding circuit according to claim 1, characterized in that, The first encoding module and the second encoding module are configured to perform an encoding operation on the data to be encoded in a forward error correction encoding manner.
11. An FPGA chip, characterized in that, It includes the forward error correction encoding circuit according to any one of claims 1 to 10 above.