Voltage mode high-speed transmitter fusing digital pre-distortion and serial driving

Abstract

The invention relates to a voltage-mode high-speed transmitter fusing digital pre-distortion and serial driving. The voltage-mode high-speed transmitter comprises a time sequence control unit, a digital signal generation unit, a voltage modulation unit and an output matching unit, the digital signal generation unit is used for generating a pre-modulated digital signal in response to the first clock signal sent by the time sequence control unit; the voltage modulation unit is used for responding to a second clock signal sent by the time sequence control unit and sequentially performing low-speed serialization processing, retiming processing, differential processing and high-speed serialization-output driving processing on the pre-modulated digital signal to obtain a first high-speed level differential signal and a second high-speed level differential signal; and the output matching unit is used for performing impedance matching processing on the first high-speed level differential signal and the second high-speed level differential signal and outputting a corresponding first differential signal and a corresponding second differential signal. The device can be applied to high-order modulation and high-rate application scenes.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuit design, and particularly relates to a voltage-mode high-speed transmitter that combines digital predistortion and serialization driving. Background Art

[0002] As a core component of modern digital communication systems, the high-speed serial data interface (SerDes, Serializer / Deserializer) is driven by the explosive growth of data transmission requirements and the multi-objective constraints of miniaturization, low power consumption, and high reliability in hardware design. Against the backdrop of the leapfrog development of computer and communication technologies, the problems of traditional parallel interfaces, such as physical space occupation, signal integrity degradation (such as timing deviation, electromagnetic interference, and increasing power consumption) caused by the multi-channel synchronous transmission mechanism, have become increasingly prominent, especially becoming a system bottleneck in long-distance transmission and high-speed scenarios. This technical dilemma has directly promoted the innovation of SerDes technology: through a single-channel serialization transmission architecture, combined with signal integrity enhancement technologies such as de-emphasis, and dynamic power management and thermal optimization strategies, SerDes has successfully achieved a coordinated improvement in bandwidth density and energy efficiency. Currently, this technology has deeply penetrated into diversified application scenarios such as in-vehicle vision systems, data center interconnects, storage interfaces (SAS / SATA), high-speed network transmissions, high-definition video links (DisplayPort / HDMI), radio frequency over fiber (RFoF), and aerospace electronics.

[0003] In the SerDes transmitter (TX) architecture, the output driver, as a key module at the end of the signal chain, its performance directly restricts the system bandwidth and energy efficiency. Currently, high-speed TX designs generally adopt current-mode logic (CML) drivers to obtain broadband characteristics, however, the problem of its high power consumption has gradually emerged. In contrast, although the voltage-mode (VM) driver has the advantage of low power consumption and is more suitable for advanced processes, its output impedance is significantly modulated by the MOSFET source-drain voltage (VDS), resulting in deteriorated linearity, especially being more prominent under four-level pulse amplitude modulation (PAM-4 modulation). In addition, the risk of clock-data timing mismatch caused by process-voltage-temperature (PVT) fluctuations further limits the practical application of the VM architecture in high-performance SerDes.

[0004] In short, existing high-speed serial data interface transmitters are difficult to be applicable to high-order modulation and high-speed application scenarios, and there is an urgent need to provide a high-speed serial data interface transmitter that can be used for high-order modulation and high speed. Summary of the Invention

[0005] To solve the above problems existing in the prior art, the present invention provides a voltage-mode high-speed transmitter that combines digital predistortion and serialization driving. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] The present invention provides a voltage-mode high-speed transmitter that combines digital predistortion and serialization driving, including: a timing control unit, a digital signal generation unit, a voltage modulation unit, and an output matching unit; the digital signal generation unit is configured to generate a pre-modulated digital signal in response to a first clock signal sent by the timing control unit; the voltage modulation unit is configured to perform low-speed serialization processing, retiming processing, differential processing, and high-speed serialization-output driving processing on the pre-modulated digital signal in sequence in response to a second clock signal sent by the timing control unit, to obtain a first high-speed level differential signal and a second high-speed level differential signal; the output matching unit is configured to perform impedance matching processing on the first high-speed level differential signal and the second high-speed level differential signal, and output corresponding first differential signal and second differential signal.

[0007] Compared with the prior art, the beneficial effects of the present invention are:

[0008] Aiming at the problem that existing high-speed serial data interface transmitters are difficult to be applicable to high-order modulation and high-speed application scenarios, an embodiment of the present invention provides a voltage-mode high-speed transmitter that combines digital predistortion and serialization driving. The voltage-mode high-speed transmitter uses the digital signal generation unit to generate a pre-modulated digital signal, and uses the voltage modulation unit to perform low-speed serialization processing, retiming processing, differential processing, and high-speed serialization-output driving processing on the pre-modulated digital signal in sequence to generate two high-speed level differential signals, and then uses the output matching unit to perform impedance matching processing on the two high-speed level differential signals and output corresponding two differential signals; this application significantly improves the compatibility with high-order modulation such as PAM-4 by cooperatively calibrating the nonlinear distortion of the voltage-mode driver, and realizes the timing reorganization and signal integrity optimization of the data stream, combines the dynamic impedance matching technology to suppress the output impedance fluctuation, reduces the power consumption and enhances the stability at high speed; integrates the single-ended to differential technology to enhance the anti-interference ability, adapts to the requirements of multiple scenarios such as optical communication, automotive radar, and high-density computing power chips, and has the characteristics of high linearity and low power consumption, providing an efficient and reliable transmission solution for high-speed data interfaces. Description of the Drawings

[0009] Figure 1 is a structural diagram of a voltage-mode high-speed transmitter that combines digital predistortion and serialization driving provided by the present invention;

[0010] Figure 2 is a circuit structural diagram of the timing control unit provided by an embodiment of the present invention;

[0011] Figure 3 is the circuit connection diagram of the digital signal generation unit provided by the embodiment of the present invention;

[0012] Figure 4 is the circuit connection diagram of the digital predistortion module provided by the embodiment of the present invention;

[0013] Figure 5 is the circuit structure diagram of the voltage modulation unit provided by the embodiment of the present invention;

[0014] Figure 6 is the circuit connection schematic diagram of the high-speed 4:1 serializer driver provided by the embodiment of the present invention;

[0015] Figure 7 is the circuit connection schematic diagram of the second output matching sub-unit provided by the embodiment of the present invention. Detailed implementation manners

[0016] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0017] In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0018] In the description of this specification, the description with reference to terms such as "an embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0019] Although the present invention has been described in connection with various embodiments, those skilled in the art will understand and realize other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosure, and the appended claims during the implementation of the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0020] With reference to the accompanying drawings, a voltage-mode high-speed transmitter that combines digital pre-distortion and serialization driving is described in detail.

[0021] Figure 1 FIG. is a structural diagram of a voltage-mode high-speed transmitter that combines digital pre-distortion and serialization driving provided by the present invention. As Figure 1 shown, the voltage-mode high-speed transmitter includes: a timing control unit, a digital signal generation unit, a voltage modulation unit, and an output matching unit; the digital signal generation unit is configured to generate a pre-modulated digital signal in response to a first clock signal sent by the timing control unit; the voltage modulation unit is configured to perform low-speed serialization processing, retiming processing, differential processing, and high-speed serialization-output driving processing on the pre-modulated digital signal in sequence in response to a second clock signal sent by the timing control unit to obtain a first high-speed level differential signal and a second high-speed level differential signal; the output matching unit is configured to perform impedance matching processing on the first high-speed level differential signal and the second high-speed level differential signal and output corresponding first differential signal and second differential signal.

[0022] Here, the specific structure of each unit will be described first. Figure 2 FIG. is a circuit structural diagram of the timing control unit provided by an embodiment of the present invention. As Figure 2As shown in the figure, the timing control unit includes: a CML-four-phase frequency divider by two sub-unit, an inverter chain, a duty cycle detection and calibration sub-unit, and a clock distribution sub-unit; a first input terminal of the CML-four-phase frequency divider by two sub-unit is connected to a first differential clock signal, a second input terminal is connected to a second differential clock signal, an output terminal is connected to an input terminal of the inverter chain, a first output terminal of the inverter chain is connected to the clock distribution sub-unit, a second output terminal is connected to the duty cycle detection and calibration sub-unit, a first to a third output terminal of the clock distribution sub-unit are connected to a first to a third input terminal of the voltage modulation unit, a first output terminal of the clock distribution sub-unit is connected to an input terminal of the digital signal generation unit; an output terminal of the duty cycle detection and calibration sub-unit is connected to a fourth input terminal of the voltage modulation unit; the CML-four-phase frequency divider by two sub-unit is configured to perform frequency division processing on the first differential clock signal and the second differential clock signal to generate a preprocessed four-phase frequency divider by two clock signal, the inverter chain is configured to process the preprocessed four-phase frequency divider by two clock signal to generate a mutually orthogonal four-phase frequency divider by two clock signal and a two-phase frequency divider by two clock signal; the duty cycle detection and calibration sub-unit is configured to perform duty cycle detection and calibration processing on the four-phase frequency divider by two clock signal to generate a calibration signal; the clock distribution sub-unit is configured to perform buffer frequency division processing on the two-phase frequency divider by two clock signal to generate a four-frequency clock signal, an eight-frequency clock signal, and a sixteen-frequency clock signal.

[0023] Here, the CML-four-phase frequency divider by two sub-unit includes a CML circuit and a four-phase frequency divider by two circuit. Among them, the CML circuit refers to a high-speed digital circuit technology based on differential signals and constant current sources, which is commonly used in GHz-level high-frequency scenarios (such as SerDes, radio frequency front-end); the four-phase frequency divider by two circuit is a circuit module that divides the input clock frequency by two and generates 4 signals with a 90° (orthogonal) phase difference. Here, the first differential clock signal CK 2_N and the second differential clock signal CK 2_P are divided by two into a two-phase frequency divider by two clock signal CK 4_IQ and a four-phase frequency divider by two clock signal CK 4_DIV by using the CML-four-phase frequency divider by two sub-unit and the inverter chain. Further, the duty cycle detection and calibration sub-unit performs duty cycle detection and calibration on the four-phase frequency divider by two clock signal CK 4_DIV to generate a calibration signal CK 4_0 / 90 / 180 / 270 , and the clock distribution sub-unit performs buffer frequency division processing on the two-phase frequency divider by two clock signal CK 4_IQ to generate a four-frequency clock signal CK8, an eight-frequency clock signal CK 16 and a sixteen-frequency clock signal CK 32 .

[0024] Here, the clock distribution subunit refers to a combination including a three-stage frequency divider and a clock driver module. The three-stage frequency divider can reduce the frequency of the input clock signal by using three cascaded frequency divisions to generate clock signals with different frequencies. Among them, the frequency division ratio of each stage is the same, all being a division by 2. The function of the clock driver circuit is to ensure the integrity and stability of the clock signal during transmission. Through the clock distribution subunit, it is possible to ensure the output of multi-clock domain signals with low jitter and high stability, meeting the stringent requirements of 5G communication, processors, and multi-rate signal processing systems.

[0025] Figure 3 is the circuit connection diagram of the digital signal generation unit provided by the embodiment of the present invention. As Figure 3 shown, the first clock signal is a 16-divided clock signal; the digital signal generation unit includes: an SPI interface, a PRBS generator, a feed-forward equalizer, and a digital pre-calibration transcoder; the input end of the SPI interface is connected to the output end of the clock distribution subunit; the first output end is connected to the input end of the PRBS generator, the second output end is connected to the first input end of the feed-forward equalizer, the third output end is connected to the first input end of the digital pre-calibration transcoder, and the output end of the digital pre-calibration transcoder is connected to the input end of the voltage modulation unit; the output end of the PRBS generator is connected to the second input end of the feed-forward equalizer; the first to seventh output ends of the feed-forward equalizer are respectively connected to the second to eighth input ends of the digital pre-calibration transcoder; the first to eighth output ends of the digital pre-calibration transcoder are respectively connected to the first to eighth input ends of the voltage modulation unit; the PRBS generator is used to generate the original code of pseudo-random binary data based on the 16-divided clock signal and the initial state information; the feed-forward equalizer is used to generate the original code of data containing equalization information based on the original code of pseudo-random binary data; the digital pre-calibration transcoder is used to sequentially perform digital pre-distortion calibration processing and data code pattern conversion processing on the original code of data containing equalization information to generate a pre-modulated digital signal.

[0026] Here, the PRBS generator refers to a pseudo-random binary sequence generator, and the PRBS generator is a circuit that generates an approximately random but deterministic digital sequence. The feed-forward equalizer refers to a 6-tap feed-forward equalizer based on a look-up table structure, which can optimize the tap coefficients through a predefined look-up table to avoid real-time calculation, reducing the real-time calculation overhead while ensuring the equalization performance.

[0027] Here, the digital pre-calibration transcoder includes: a digital pre-distortion module and a data code pattern conversion module; the digital pre-distortion module is used to receive the original data code containing equalization information, perform digital pre-distortion calibration processing on the original data code containing equalization information, and obtain calibrated data; the data code pattern conversion module performs format conversion processing on the encoding format of the calibrated data to obtain a pre-modulated digital signal. Specifically, the data code pattern conversion module can convert the encoding format of the calibrated data from binary to thermometer encoding.

[0028] Exemplarily, the SPI interface receives a 16-divided clock signal and provides the initial state information of the PRBS generator to the PRBS generator. The PRBS generator receives the signal from the SPI and generates a 64-channel binary pseudo-random sequence and outputs it to the feed-forward equalizer; the feed-forward equalizer receives the signal from the SPI interface and the 64-channel binary pseudo-random sequence and then performs logical processing based on a 6-tap lookup table to generate 32-channel 7-bit data signals and outputs them to the digital pre-calibration transcoder; the digital pre-calibration transcoder receives the 32-channel 7-bit data signals and performs digital pre-distortion calibration on the data signals, and then performs logical operations on the high two bits of each data signal to generate three-bit thermometer codes, and the low five bits of each data signal are not processed. The digital pre-calibration transcoder outputs 32-channel 8-bit data signals.

[0029] Here, Figure 4 is the circuit connection diagram of the digital pre-distortion module provided by the embodiment of the present invention. As Figure 4As shown in the figure, the digital predistortion module includes: a digital predistortion look-up table, a first selector MUX1, a second selector MUX2, a first adder ADD1, a second adder ADD2, a first exclusive-OR gate XOR1, and a second exclusive-OR gate XOR2; all output terminals of the feed-forward equalizer are respectively connected to the first input terminal of the second adder ADD2, the first input terminal of the second selector MUX2, the first input terminal and the second input terminal of the first exclusive-OR gate XOR1, and the first input terminal of the second exclusive-OR gate XOR2; the N input terminals of the digital predistortion look-up table are connected to the N input terminals of the first selector MUX1, the th input terminal of the first selector MUX1 is connected to the output terminal of the first exclusive-OR gate XOR1, the output terminal of the first selector MUX1 is connected to the second input terminal of the second exclusive-OR gate XOR2, the output terminal of the second exclusive-OR gate XOR2 is respectively connected to the second input terminal of the second selector MUX2 and the first input terminal of the first adder ADD1, the second input terminal of the first adder ADD1 is connected to a high level, the output terminal of the first adder ADD1 is connected to the third input terminal of the second selector MUX2, the output terminal of the second selector MUX2 is connected to the second input terminal of the second adder ADD2, and the output terminal of the second adder ADD2 is connected to the input terminal of the data pattern conversion module; the feed-forward equalizer sends the low-order data of the original data code containing the equalization information to the first input terminal of the first exclusive-OR gate XOR1, and sends the highest-order data of the original data code containing the equalization information to the second input terminal of the first exclusive-OR gate XOR1. Exemplarily, N is 64.

[0030] Here, the digital predistortion look-up table refers to a 4-bit DPD LUT. Here, DPD is the abbreviation of Digital Predistortion, which is mainly used for the linearization of the voltage-mode drive output to compensate for its non-linear distortion. And LUT is a Look-Up Table, which is used to store the corresponding predistortion coefficients. 4-bit means that the input signal is quantized into 4 bits.

[0031] Exemplarily, the 4-bit DPD LUT stores the difference between the pre-distortion code and the original code. There are a total of 64 addresses, and each address stores 4-bit data, which is output to MUX1; XOR1 receives the data DATA[6:0] (the original data code containing equalization information), and performs a bitwise exclusive OR on DATA[5:0] (the lower 6 bits of the original data code containing equalization information) and DATA[6] (the highest bit of the original data code containing equalization information) to generate a 6-bit selection signal and output it to MUX1; MUX1 receives the difference stored in the 4-bit DPD LUT and the selection signal from XOR1, and outputs a 4-bit signal to XOR2; XOR2 receives the selected 4-bit data from MUX1, performs a bitwise exclusive OR with DATA[6], and generates a 4-bit data signal and outputs it to ADD1 and MUX2; ADD1 adds one to the data signal from XOR2 and outputs the data to MUX2; MUX2 receives the data signal from XOR2 and the data signal from ADD1, and selects one set of data through DATA[6] and outputs it to ADD2; ADD2 receives the difference data information from MUX2 and the 7-bit data DATA[6:0], adds them together, and outputs the data containing digital pre-distortion calibration information (i.e., the pre-modulated digital signal DPD DATA) to the subsequent circuit.

[0032] Figure 5 is the circuit structure diagram of the voltage modulation unit provided by the embodiment of the present invention. As Figure 5 shown, the second clock signal includes: a quarter-frequency clock signal CK8, an eighth-frequency clock signal CK 16 , a sixteenth-frequency clock signal CK 32 and a calibration signal CK 4_0 / 90 / 180 / 270 ; the voltage modulation unit includes: a low-speed serializer, a retiming signal processor, and a high-speed 4:1 serializer driver; the first to eighth input terminals of the low-speed serializer are connected to the first to eighth output terminals of the digital pre-calibration transcoder, the ninth to eleventh input terminals of the low-speed serializer are connected to the first to third output terminals of the clock distribution sub-unit, the first to eighth output terminals are connected to the first to eighth input terminals of the retiming signal processor, the first to eighth output terminals of the retiming signal processor are connected to the first to eighth input terminals of the high-speed 4:1 serializer driver, the ninth input terminal of the retiming signal processor is connected to the output terminal of the duty cycle detection and calibration sub-unit, the ninth input terminal of the high-speed 4:1 serializer driver is connected to the output terminal of the duty cycle detection and calibration sub-unit, the first output terminal and the second output terminal are connected to the input terminal of the output matching unit; the ninth to eleventh input terminals of the low-speed serializer are connected to the first to third output terminals of the clock distribution sub-unit; the ninth input terminal of the retiming signal processor and the ninth input terminal of the high-speed 4:1 serializer driver are both connected to the output terminal of the duty cycle detection and calibration sub-unit.

[0033] Specifically, the low-speed serializer includes a first 32:4 serializer, a second 32:4 serializer, a third 32:4 serializer, a fourth 32:4 serializer, a fifth 32:4 serializer, a sixth 32:4 serializer, a seventh 32:4 serializer, and an eighth 32:4 serializer; wherein, the first input end of each 32:4 serializer is connected to an output end of the digital pre-calibration transcoder, the first output end of each 32:4 serializer is connected to an input end of the retiming signal processor, and the second to fourth input ends of each 32:4 serializer are connected to the first to third output ends of the clock distribution sub-unit.

[0034] Here, the 32:4 serializer is a digital circuit module that converts 32-bit parallel data into 4-channel serial data streams. This device can achieve high-performance and low-complexity data conversion in medium- and high-speed transmission scenarios by balancing the number of channels and the single-channel rate, reducing the number of physical channels required for transmission and increasing the data rate.

[0035] Here, the retiming signal processor includes: a first retiming signal processing module, a second retiming signal processing module, a third retiming signal processing module, a fourth retiming signal processing module, a fifth retiming signal processing module, a sixth retiming signal processing module, a seventh retiming signal processing module, and an eighth retiming signal processing module; wherein, the output end of each retiming signal processing module is connected to an input end of a high-speed 4:1 serialization driver, the first input end of each retiming signal processing module is connected to the first output end of a 32:4 serializer, and the second input end is connected to the output end of the duty cycle detection and calibration sub-unit.

[0036] Here, the retiming signal processor includes: a retiming module and a single-ended to differential module. The retiming module can ensure signal timing and integrity, and solve problems such as jitter, attenuation, and inter-symbol interference (ISI) in signal transmission.

[0037] Here, the high-speed 4:1 serialization driver includes: a first high-speed 4:1 serialization driving module, a second high-speed 4:1 serialization driving module, a third high-speed 4:1 serialization driving module, a fourth high-speed 4:1 serialization driving module, a fifth high-speed 4:1 serialization driving module, a sixth high-speed 4:1 serialization driving module, a seventh high-speed 4:1 serialization driving module, and an eighth high-speed 4:1 serialization driving module; wherein, the first output ends of each high-speed 4:1 serialization driving module are combined into the first output end of the high-speed 4:1 serialization driver, the second output ends of each high-speed 4:1 serialization driving module are combined into the second output end of the high-speed 4:1 serialization driver, and the second input ends of each high-speed 4:1 serialization driving module are connected to the output end of the duty cycle detection and calibration sub-unit.

[0038] Figure 6It is a schematic circuit connection diagram of the high-speed 4:1 serializer driver provided by the embodiments of the present invention. As Figure 6 shown, the high-speed 4:1 serializer driver includes 8 high-speed 4:1 serializer driver modules, and each high-speed 4:1 serializer driver module includes a 1UI pulse generation circuit and a voltage-mode drive circuit; wherein, the voltage-mode drive circuit consists of four groups of switching transistors (Mp1, Mp2, Mn1, Mn2) and 16 transistors (Mn_0 / Mp_0, Mn_0' / Mp_0', Mn_1 / Mp_1, Mn_1' / Mp_1', Mn_2 / Mp_2, Mn_2' / Mp_2', Mn_3 / Mp_3, Mn_3' / Mp_3') that receive the 1UI pulse signals generated by the 1UI pulse generation circuit.

[0039] The high-speed 4:1 serializer driver receives eight data signals sent by the retiming signal processor Since the circuit structures of each slice are exactly the same, the path through which D[0] passes is described during the introduction. Among them, the 1UI pulse generation circuit receives the data signal D[0] and the clock signal CK 4_0 / 90 / 180 / 270, the low-speed data signal is converted into a 1UI pulse, generating two 1UI pulse data signals (DA[0] and DB[0]) and inputting them into the voltage-mode output driving circuit. DA[0] is input to the gate of Mp_0, and DB[0] is input to the gate of Mn_0; the gate of the switch transistor group Mp1 receives the switching information TUNEP<3:0> from the external circuit, controls its own switching state, and adjusts the impedance of the output drive to achieve impedance matching of the circuit. The source is connected to VDD, and the drain is connected to the sources of the four transistors Mp_0, Mp_1, Mp_2, and Mp_3; the gate of the transistor Mp_0 receives the 1UI pulse data signal DA[0] from the 1UI pulse generation circuit. Its source is connected to the drain of the switch transistor group Mp1 and the sources of the three transistors Mp_1, Mp_2, and Mp_3. The drain is connected to the output node OUTP', as well as the drains of the four transistors Mn_0, Mn_1, Mn_2, Mn_3 and the drains of the three transistors Mp_1, Mp_2, Mp_3; the gate of the transistor Mn_0 receives the 1UI pulse data signal DB[0] from the 1UI pulse generation circuit. Its source is connected to the drain of the switch transistor group Mn1 and the sources of the three transistors Mn_1, Mn_2, and Mn_3. The drain is connected to the output node OUTP', as well as the drains of the four transistors Mp_0, Mp_1, Mp_2, Mp_3 and the drains of the three transistors Mn_1, Mn_2, Mn_3; the gate of the switch transistor group Mn1 receives the switching information TUNEN<3:0> from the external circuit, controls its own switching state, and adjusts the impedance of the output drive to achieve impedance matching of the circuit. The source is connected to VSS, and the drain is connected to the sources of the four transistors Mn_0, Mn_1, Mn_2, and Mn_3; the connection methods of the remaining seven data signals are similar to D[0]. The data passes through the 1UI pulse signal generated by the 1UI pulse generation circuit, and the 1UI pulse signal is serially multiplexed at a high speed of 4:1 through the voltage-mode output driving circuit to generate the first high-speed level differential signal OUTP' and the second high-speed level differential signal OUTN'.

[0040] Here, the output matching unit includes: a first output matching subunit and a second output matching subunit. The first output matching subunit is used to perform impedance matching processing on the first high-speed level differential signal and output a first differential signal. The second output matching subunit is used to perform impedance matching processing on the second high-speed level differential signal and output a second differential signal. The first output matching subunit includes: an inductor LP1, an inductor LP2, a first electrostatic protection diode, and a second electrostatic protection diode. The first end of the inductor LP1 is connected to the first output end of the high-speed 4:1 serialization driver. The second end of the inductor LP1 is respectively connected to the positive electrode of the first electrostatic protection diode, the negative electrode of the second electrostatic protection diode, and the first end of the inductor LP2. The negative electrode of the first electrostatic protection diode is connected to the power supply. The positive electrode of the second electrostatic protection diode is grounded. The second end of the inductor LP2 serves as the output end of the first output matching subunit. The second output matching subunit includes: an inductor LN1, an inductor LN2, a third electrostatic protection diode, and a fourth electrostatic protection diode. The first end of the inductor LN1 is connected to the first output end of the high-speed 4:1 serialization driver. The second end of the inductor LN1 is respectively connected to the positive electrode of the third electrostatic protection diode, the negative electrode of the fourth electrostatic protection diode, and the first end of the inductor LN2. The negative electrode of the third electrostatic protection diode is connected to the power supply. The positive electrode of the fourth electrostatic protection diode is grounded. The second end of the inductor LN2 serves as the output end of the second output matching subunit.

[0041] It should be noted that the circuit connection structures of the first output matching subunit and the second output matching subunit are the same, and the corresponding equivalent circuits are also the same. Figure 7 is a schematic diagram of the circuit connection of the second output matching subunit provided by the embodiment of the present invention. For the sake of simplicity here, only the circuit of one output matching subunit is described. As Figure 7 shown, on the left is the circuit connection relationship of the second output matching subunit, and on the right is the equivalent circuit connection relationship of the second output matching subunit.

[0042] Aiming at the problem that existing high-speed serial data interface transmitters are difficult to be applied to high-order modulation and high-speed application scenarios, an embodiment of the present invention provides a voltage-mode high-speed transmitter that combines digital predistortion and serialization driving. The voltage-mode high-speed transmitter uses a digital signal generation unit to generate a pre-modulated digital signal, and uses a voltage modulation unit to perform low-speed serialization processing, retiming processing, differential processing, and high-speed serialization-output driving processing on the pre-modulated digital signal in sequence to generate two high-speed level differential signals. Subsequently, an output matching unit is used to perform impedance matching processing on the two high-speed level differential signals and output the corresponding two differential signals. Through the innovative integration of the digital predistortion look-up table and the high-speed serialization driving fusion architecture, the present invention has achieved a technological breakthrough in the field of voltage-mode high-speed transmitters, effectively solving the industry problem of the difficulty in synergistically optimizing high-order modulation compatibility, high-speed transmission, and system energy efficiency. This solution takes a 4-bit precision digital predistortion look-up table as the core, combines feed-forward equalization technology, and dynamically compensates for the non-linear characteristics of the voltage-mode driver, significantly broadening the support range of the transmitter for high-order modulation formats such as PAM-4 and PAM-8, and still maintaining excellent signal fidelity in complex channel environments; through the unique three-level collaborative architecture of a 32:4 low-speed serializer, a retiming signal processor, and a 4:1 high-speed serialization driver, combined with a duty cycle calibration circuit to suppress timing phase deviation, a highly stable timing link is constructed to ensure the precise synchronization of high-speed data streams; in the physical layer design, a voltage-mode high-speed switching transistor group and a dynamic impedance matching network are innovatively introduced, and the driving impedance is adjusted in real time through a programmable switch array, and the impedance matching characteristics can still be maintained under nanoscale process fluctuations and wide temperature range environments, significantly improving the output signal integrity; at the same time, the single-ended to differential technology is deeply integrated, the eye diagram quality is optimized by using common-mode noise suppression, and an SPI configurable interface is integrated to realize the dynamic tuning of digital predistortion parameters, enabling a single chip to adapt to diverse high-speed scenarios such as SerDes interfaces, optical network units (ONUs), and 5G fronthaul.

[0043] The above content is a further detailed description of the present invention in combination with specific preferred implementation manners, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A voltage-mode high-speed transmitter that combines digital predistortion and serialization driving, characterized in that Comprising: A timing control unit, a digital signal generation unit, a voltage modulation unit, and an output matching unit; The digital signal generation unit is configured to generate a pre-modulated digital signal in response to a first clock signal sent by the timing control unit; The voltage modulation unit is configured to perform low-speed serialization processing, retiming processing, differential processing, and high-speed serialization-output driving processing on the pre-modulated digital signal in sequence in response to a second clock signal sent by the timing control unit, and obtain a first high-speed level differential signal and a second high-speed level differential signal; The output matching unit is configured to perform impedance matching processing on the first high-speed level differential signal and the second high-speed level differential signal, and output corresponding first and second differential signals.

2. The voltage-mode high-speed transmitter adopting the fusion of digital predistortion and serialization driving according to claim 1, wherein The timing control unit includes: a CML-four-phase frequency divider sub-unit, an inverter chain, a duty cycle detection and calibration sub-unit, and a clock distribution sub-unit; A first input end of the CML-four-phase frequency divider sub-unit is connected to a first differential clock signal, a second input end is connected to a second differential clock signal, an output end is connected to an input end of the inverter chain, a first output end of the inverter chain is connected to the clock distribution sub-unit, a second output end is connected to the duty cycle detection and calibration sub-unit, first to third output ends of the clock distribution sub-unit are connected to first to third input ends of the voltage modulation unit, and a first output end of the clock distribution sub-unit is connected to an input end of the digital signal generation unit; an output end of the duty cycle detection and calibration sub-unit is connected to a fourth input end of the voltage modulation unit; The CML-four-phase frequency divider sub-unit is configured to perform frequency division processing on the first differential clock signal and the second differential clock signal to generate a preprocessed four-phase frequency divided clock signal; The inverter chain is configured to process the preprocessed four-phase frequency divided clock signal to generate a mutually orthogonal four-phase frequency divided clock signal and a two-phase frequency divided clock signal; The duty cycle detection and calibration sub-unit is configured to perform duty cycle detection and calibration processing on the four-phase frequency divided clock signal to generate a calibration signal; The clock distribution sub-unit is configured to perform buffer frequency division processing on the two-phase frequency divided clock signal to generate a four-frequency divided clock signal, an eight-frequency divided clock signal, and a sixteen-frequency divided clock signal.

3. The voltage-mode high-speed transmitter adopting the fusion of digital pre-distortion and serialization driving according to claim 2, characterized in that The first clock signal is the sixteen-frequency divided clock signal; The digital signal generation unit includes: an SPI interface, a PRBS generator, a feedforward equalizer, and a digital pre-calibration transcoder; An input end of the SPI interface is connected to an output end of the clock distribution sub-unit; a first output end is connected to an input end of the PRBS generator, a second output end is connected to a first input end of the feedforward equalizer, a third output end is connected to a first input end of the digital pre-calibration transcoder, and an output end of the digital pre-calibration transcoder is connected to an input end of the voltage modulation unit; An output end of the PRBS generator is connected to a second input end of the feedforward equalizer; First to seventh output ends of the feedforward equalizer are respectively connected to second to eighth input ends of the digital pre-calibration transcoder; The first to eighth output terminals of the digital pre-calibration transcoder are respectively connected to the first to eighth input terminals of the voltage modulation unit; The PRBS generator is used to generate a pseudo-random binary data original code based on the sixteen-frequency divided clock signal and the initial state information; The feed-forward equalizer is used to generate a data original code containing equalization information based on the pseudo-random binary data original code; The digital pre-calibration transcoder is used to sequentially perform digital pre-distortion calibration processing and data code pattern conversion processing on the data original code containing equalization information to generate the pre-modulated digital signal.

4. The voltage-mode high-speed transmitter adopting the fusion of digital pre-distortion and serialization driving according to claim 3, wherein The digital pre-calibration transcoder includes: a digital pre-distortion module and a data code pattern conversion module; The digital pre-distortion module is used to receive the data original code containing equalization information, perform digital pre-distortion calibration processing on the data original code containing equalization information to obtain calibrated data; the data code pattern conversion module performs format conversion processing on the encoding format of the calibrated data to obtain the pre-modulated digital signal.

5. The voltage-mode high-speed transmitter adopting the fusion of digital pre-distortion and serialization driving according to claim 4, wherein The digital pre-distortion module includes: a digital pre-distortion look-up table, a first selector MUX1, a second selector MUX2, a first adder ADD1, a second adder ADD2, a first exclusive-OR gate XOR1, and a second exclusive-OR gate XOR2; All output terminals of the feed-forward equalizer are respectively connected to the first input terminal of the second adder ADD2, the first input terminal of the second selector MUX2, the first input terminal and the second input terminal of the first exclusive-OR gate XOR1, and the first input terminal of the second exclusive-OR gate XOR2; The N input terminals of the digital pre-distortion look-up table are connected to the N input terminals of the first selector MUX1, the (N + 1)-th input terminal of the first selector MUX1 is connected to the output terminal of the first exclusive-OR gate XOR1, the output terminal of the first selector MUX1 is connected to the second input terminal of the second exclusive-OR gate XOR2, the output terminal of the second exclusive-OR gate XOR2 is respectively connected to the second input terminal of the second selector MUX2 and the first input terminal of the first adder ADD1, the second input terminal of the first adder ADD1 is connected to a high level, the output terminal of the first adder ADD1 is connected to the third input terminal of the second selector MUX2, the output terminal of the second selector MUX2 is connected to the second input terminal of the second adder ADD2, and the output terminal of the second adder ADD2 is connected to the input terminal of the data code pattern conversion module.

6. The voltage-mode high-speed transmitter adopting the fusion of digital pre-distortion and serialization driving according to claim 3, characterized in that, The second clock signal includes: the four-frequency divided clock signal, the eight-frequency divided clock signal, the sixteen-frequency divided clock signal, and the calibration signal; the voltage modulation unit includes: a low-speed serializer, a retiming signal processor, and a high-speed 4:1 serializer driver; The first to eighth input ends of the low-speed serializer are connected to the first to eighth output ends of the digital pre-calibration transcoder. The ninth to eleventh input ends of the low-speed serializer are connected to the first to third output ends of the clock distribution sub-unit. The first to eighth output ends are connected to the first to eighth input ends of the retiming signal processor. The first to eighth output ends of the retiming signal processor are connected to the first to eighth input ends of the high-speed 4:1 serializer driver. The ninth input end of the retiming signal processor is connected to the output end of the duty cycle detection and calibration sub-unit. The ninth input end of the high-speed 4:1 serializer driver is connected to the output end of the duty cycle detection and calibration sub-unit. The first output end and the second output end are connected to the input end of the output matching unit; The ninth to eleventh input ends of the low-speed serializer are connected to the first to third output ends of the clock distribution sub-unit; The ninth input end of the retiming signal processor and the ninth input end of the high-speed 4:1 serializer driver are both connected to the output end of the duty cycle detection and calibration sub-unit.

7. The voltage-mode high-speed transmitter adopting the fusion of digital pre-distortion and serialization driving according to claim 6, wherein The low-speed serializer includes a first 32:4 serializer, a second 32:4 serializer, a third 32:4 serializer, a fourth 32:4 serializer, a fifth 32:4 serializer, a sixth 32:4 serializer, a seventh 32:4 serializer, and an eighth 32:4 serializer; Among them, the first input end of each 32:4 serializer is connected to an output end of the digital pre-calibration transcoder. The first output end of each 32:4 serializer is connected to an input end of the retiming signal processor. The second to fourth input ends of each 32:4 serializer are connected to the first to third output ends of the clock distribution sub-unit.

8. The voltage-mode high-speed transmitter adopting the fusion of digital predistortion and serialization driving according to claim 7, wherein The retiming signal processor includes: a first retiming signal processing module, a second retiming signal processing module, a third retiming signal processing module, a fourth retiming signal processing module, a fifth retiming signal processing module, a sixth retiming signal processing module, a seventh retiming signal processing module, and an eighth retiming signal processing module; Among them, the output end of each retiming signal processing module is connected to an input end of the high-speed 4:1 serializer driver. The first input end of each retiming signal processing module is connected to the first output end of a 32:4 serializer. The second input end is connected to the output end of the duty cycle detection and calibration sub-unit.

9. The voltage-mode high-speed transmitter adopting the fusion of digital predistortion and serialization driving according to claim 6, wherein The high-speed 4:1 serializer driver includes: a first high-speed 4:1 serializer driving module, a second high-speed 4:1 serializer driving module, a third high-speed 4:1 serializer driving module, a fourth high-speed 4:1 serializer driving module, a fifth high-speed 4:1 serializer driving module, a sixth high-speed 4:1 serializer driving module, a seventh high-speed 4:1 serializer driving module, and an eighth high-speed 4:1 serializer driving module; The second input end of each high-speed 4:1 serializer driving module is connected to the output end of the duty cycle detection and calibration sub-unit.

10. The voltage-mode high-speed transmitter adopting the fusion of digital pre-distortion and serialization driving according to claim 6, characterized in that The output matching unit includes: a first output matching sub-unit and a second output matching sub-unit. The first output matching sub-unit is used to perform impedance matching processing on the first high-speed level differential signal and output the first differential signal. The second output matching sub-unit is used to perform impedance matching processing on the second high-speed level differential signal and output the second differential signal; Among them, the first output matching sub-unit includes: an inductor LP1, an inductor LP2, a first electrostatic protection diode, and a second electrostatic protection diode. The first end of the inductor LP1 is connected to the first output end of the high-speed 4:1 serializer driver. The second end of the inductor LP1 is respectively connected to the positive electrode of the first electrostatic protection diode, the negative electrode of the second electrostatic protection diode, and the first end of the inductor LP2. The negative electrode of the first electrostatic protection diode is connected to the power supply. The positive electrode of the second electrostatic protection diode is grounded. The second end of the inductor LP2 serves as the output end of the first output matching sub-unit; The second output matching sub-unit includes: an inductor LN1, an inductor LN2, a third electrostatic protection diode, and a fourth electrostatic protection diode. The first end of the inductor LN1 is connected to the first output end of the high-speed 4:1 serializer driver. The second end of the inductor LN1 is respectively connected to the positive electrode of the third electrostatic protection diode, the negative electrode of the fourth electrostatic protection diode, and the first end of the inductor LN2. The negative electrode of the third electrostatic protection diode is connected to the power supply. The positive electrode of the fourth electrostatic protection diode is grounded. The second end of the inductor LN2 serves as the output end of the second output matching sub-unit.

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