Multi-jitter profile signal generation

Abstract

The invention relates to multi-jitter profile signal generation. At least some aspects of the present disclosure provide a system (104). In some examples, the system includes a pulse width modulated (PWM) generator (218) configured to generate a PWM signal (PWM1). The PWM generator generates the PWM signal by: generating a first signal having a first jitter profile and a first frequency bandwidth; generating a second signal having a second jitter profile and a second frequency bandwidth greater than the first frequency bandwidth; modulating the second signal with the first signal to generate a double random spread spectrum signal; and generating the pulse width modulation signal according to the double random spread spectrum signal.

Description

[0001] Relevant information on divisional applications

[0002] This application is a divisional application. Its parent application is a patent application for invention titled "Multi-Dither Contour Signal Generation" with an application date of May 18, 2020, an application number of 202080035987.4. Technical Field

[0003] This application relates to multi-dither contour signal generation. Background Art

[0004] A switched-mode power supply (SMPS) transfers power from an input power supply to a load by switching one or more power transistors coupled to an energy storage element (such as an inductor / transformer and / or capacitor) via a switching node / terminal, and the energy storage element can be coupled to the load. The power transistors can be included in a power converter that includes or can be coupled to the energy storage element. The SMPS can include an SMPS controller to provide one or more gate drive signals to the power transistors. The SMPS operates at a switching frequency that can generate noise, resulting in electromagnetic interference (EMI) at the switching frequency and its harmonic frequencies. Summary of the Invention

[0005] At least some aspects of the present disclosure provide a circuit. In at least some instances, the circuit includes a linear feedback shift register (LFSR), a clock divider, a ramp generator, an adder, and an oscillator. The LFSR includes a clock input terminal configured to receive a clock signal, a first output terminal, and a second output terminal. The clock divider includes a clock input terminal configured to receive the clock signal, a first input terminal coupled to the first output terminal of the LFSR, a second input terminal coupled to the second output terminal of the LFSR, and an output terminal. The ramp generator includes an input terminal and an output terminal coupled to the output terminal of the clock divider. The adder includes a first input terminal coupled to the output terminal of the ramp generator, a second input terminal coupled to the first output terminal of the LFSR, and an output terminal. The oscillator includes a first input terminal and an output terminal coupled to the output terminal of the adder.

[0006] Other aspects of the present disclosure provide a circuit. In at least some instances, the circuit includes a linear feedback shift register (LFSR), a clock divider, a ramp generator, an adder, and an oscillator. The LFSR is clocked by a clock signal and configured to output a pseudo-random value in a digital data format. The clock divider is configured to receive the clock signal and divide the clock signal by the pseudo-random value to generate and output a divided clock signal. The ramp generator is configured to receive the divided clock signal, generate a ramp signal based on the divided clock signal, and output the ramp signal in a digital data format. The adder is configured to modulate the ramp signal with the pseudo-random value to generate a dual-random spread spectrum signal. The oscillator is configured to receive the dual-random spread spectrum signal and generate a pulse-width modulation signal based on the dual-random spread spectrum signal.

[0007] At least some aspects of the present disclosure provide a system. In some instances, the system includes a pulse-width modulation (PWM) generator configured to generate a PWM signal. The PWM generator generates the PWM signal by: generating a first signal having a first jitter profile and a first frequency bandwidth; generating a second signal having a second jitter profile and a second frequency bandwidth greater than the first frequency bandwidth; modulating the second signal with the first signal to generate a dual-random spread spectrum signal; and generating a pulse-width modulation signal based on the dual-random spread spectrum signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To describe the various examples in detail, reference will now be made to the accompanying drawings, in which:

[0009] Figure 1 A block diagram of an illustrative system in accordance with various examples is shown;

[0010] Figure 2 A schematic diagram of an illustrative switched-mode power supply (SMPS) in accordance with various examples is shown;

[0011] Figure 3 A schematic diagram of an illustrative pulse-width modulation (PWM) generator in accordance with various examples is shown;

[0012] Figure 4 A graph showing illustrative signal waveforms in accordance with various examples is shown;

[0013] Figure 5 A graph showing illustrative signal waveforms in accordance with various examples is shown;

[0014] Figure 6 A graph showing illustrative signal waveforms in accordance with various examples is shown;

[0015] Figure 7 A flowchart showing an illustrative method in accordance with various examples is shown; and

[0016] Figure 8 A table showing illustrative pseudocode in accordance with various embodiments is shown. DETAILED DESCRIPTION

[0017] In a switched-mode power supply (SMPS), a power transistor is controlled (e.g., switched) to turn on and off at a specific frequency called the switching frequency. The nature of the switching behavior of the power transistor causes and / or generates spectral frequency spurs of electromagnetic energy (e.g., conducted and / or radiated) at each of the switching frequency and its harmonic frequencies. These spectral frequency spurs are referred to as electromagnetic interference (EMI) having a maximum amount of energy at the switching frequency. The generation of this noise may sometimes be undesirable. In at least some instances, the maximum amount of EMI energy permitted in a particular system at a particular frequency is limited. For example, various standards or government regulations limit the maximum amount of EMI energy permitted at a particular frequency in systems such as automotive, audio equipment, or other applications, where excessive EMI at the particular frequency may be undesirable and / or inhibit the normal or expected operation of the system.

[0018] There are some techniques for reducing the peak energy of EMI at the switching frequency. For example, various dithering techniques spread the EMI energy over multiple frequencies (e.g., frequency bands). These dithering techniques are sometimes referred to as spread-spectrum dithering. Spread-spectrum dithering changes the switching frequency between multiple values over a predetermined bandwidth, thereby spreading the spectral energy of the EMI over the predetermined bandwidth. This prevents the focusing of spectral energy at the switching frequency and reduces the peak spectral energy at the switching frequency. Some dithering techniques are more suitable for specific frequency ranges than others. For example, an analog dithering technique that generates a triangular ramp signal may provide optimal performance for dithering at low frequencies. A digital dithering technique such as pseudo-random spread-spectrum (PRSS) dithering may provide optimal performance for dithering at high frequencies. However, a dithering technique that provides optimal performance for one frequency range (e.g., high or low) may not provide optimal performance for other frequency ranges and may, in some instances, degrade the system performance in other frequency ranges.

[0019] Aspects of the present disclosure provide for using multiple dither profiles (e.g., dither signal shapes) or techniques simultaneously to generate a dual random spread spectrum (DRSS) signal. For example, a first signal is generated to represent an analog or digital signal and is a first modulation signal for modulating the output of an oscillator and the output is a plurality of digital bits. Alternatively, in some instances, the first signal is output in analog format. In some instances, the first signal represents an analog triangle ramp as discussed above. A second signal is generated to represent an analog or digital signal, and the first signal is modulated by the second signal to generate a DRSS signal. In some instances, the second signal is a PRSS signal. In some instances, the first signal is modulated by the second signal by adding the first signal and the second signal. In some instances, the DRSS signal is output as a plurality of digital bits (e.g., data in digital data format). In at least one instance, generating a DRSS signal by modulating the first signal with the second signal is referred to as DRSS dithering. In another instance, the result of modulating the first signal with the second signal is further modulated by another signal to generate a DRSS signal. In yet other instances, any number of signals each optimized for a varying frequency are modulated together or otherwise combined to form a DRSS signal. When a DRSS signal is generated by combining more than two signals, the DRSS signal may be renamed to reflect the multiple combined signals. An oscillator is controlled in accordance with the DRSS signal to generate a pulse width modulation (PWM) clock signal for controlling another component (e.g., such as for controlling a power converter, setting a latch for controlling a power converter or another component, or other components). For consistency and clarity of description, in the present disclosure, the first signal comprises digital bits representing a triangular wave form and the second signal is a PRSS signal. However, the teachings of the present disclosure are not limited to this single instance, and the first signal and the second signal may each be any signal suitable for use in modulation and / or dithering. For example, in various embodiments, the first signal is a triangular wave form and the second signal is a triangular wave form, the first signal is a triangular wave form and the second signal is a PRSS signal, the first signal and the second signal are each a PRSS signal, the first signal is a PRSS signal and the second signal is a triangular wave form, either the first signal or the second signal is an adaptive random spread spectrum signal (ARSS), a periodic analog type waveform, etc. In at least some instances, ARSS is defined as a modulation profile having a triangular shape with a modulation period (e.g., triangle width) that is modulated over time. In some instances, the modulation period changes at the end of each ramp or at any other point in the cycle. Additionally, in some instances, the modulation period is a fixed value. In at least some instances, a periodic analog type waveform is an analog or digital representation of an analog signal and can occur in a variety of shapes, including triangular, sinusoidal, exponential, etc.

[0020] In some instances, the first signal is optimized for performing spread spectrum dithering in a low frequency band, such as a frequency band from about 150 kilohertz (kHz) to about 30 megahertz (MHz). Similarly, in some instances, the second signal is optimized for performing spread spectrum dithering in a high frequency band, such as a frequency band from about 30 MHz to about 108 MHz. Thus, in at least some instances, modulating the first signal with the second signal to produce a DRSS signal causes the DRSS signal to be optimized for the low frequency band and the high frequency band. For example, when switching a device according to a PWM signal, generating the PWM signal according to the DRSS signal reduces the peak energy of EMI in the low frequency band (e.g., generated by the first signal) and the high frequency band (e.g., generated by modulating the first signal with the second signal).

[0021] Turning now to Figure 1 , a block diagram of an illustrative system 100 is shown. In at least some instances, system 100 is an electronic device that includes a power supply 102, an SMPS 104, and a load 106. In at least some instances, system 100 represents a consumer electronic device, such as a laptop computer, a smart phone, an audio device, a wearable device, etc. In other instances, system 100 represents a system or subsystem in a transportation vehicle, such as an automobile, an airplane, a ship, etc. Generally, system 100 represents any system that desires and / or requires compliance with a specific control specification or standard that limits the peak energy of EMI at a specific frequency. One such standard is Comité International Spécial des Perturbations Radioélectriques (CISPR) 25, which specifies peak energy limits for various transportation vehicles at specific frequencies. Other such standards or peak energy limits may be specified in emission standards established and / or promulgated by the Federal Communications Commission or other regulatory agencies in the United States.

[0022] In some instances, power supply 102 is a rechargeable or non-rechargeable battery or a depletable power supply that outputs VIN. In other instances, power supply 102 is in the form of a mains power supply, such as the output of a direct current (DC) transformer that receives alternating current (AC) or other mains power and produces a DC output signal as VIN. In some instances, load 106 is any one or more electrical and / or mechanical components that receive VOUT from SMPS 104 and operate at least partially in accordance with VOUT. In at least one instance, SMPS 104 includes controller 108 and power converter 110. Power converter 110 is any suitable power converter, such as a buck power converter, a boost power converter, or a buck-boost power converter. Controller 108 generates a PWM that at least partially controls the operation of power converter 110. In at least some instances, controller 108 generates the PWM based on the DRSS signal to limit the electromagnetic interference (EMI) generated by power converter 110 when producing VOUT, as described herein.

[0023] Turning now to Figure 2 , a schematic diagram illustrating an illustrative SMPS 104 is shown. Although described as a component of system 100, in various instances, SMPS 104 is suitable for implementation in other systems or devices that receive VIN and produce VOUT by switching one or more components. In at least some instances, SMPS 104 includes controller 108 and power converter 110. In at least some instances, power converter 110 includes field effect transistors (FETs) 202, FET 204, and inductor 206. As Figure 2 shown, power converter 110 is a current mode buck switch converter. However, the teachings of the present disclosure are equally applicable to boost switch converters and buck-boost switch converters, as well as voltage mode converters of buck, boost, or buck-boost topologies or any other suitable power converter topologies. In at least some instances, controller 108 includes resistor 208, resistor 210, amplifier 212, comparator 214, latch 216, PWM generator 218, and adder 220.

[0024] In the example architecture, the FET 202 has a drain terminal coupled to node 224, a source terminal coupled to node 226, and a gate terminal. The FET 204 has a drain terminal coupled to node 226, a source terminal coupled to ground node 230, and a gate terminal. The inductor 206 is coupled between node 226 and node 228. The resistor 208 is coupled between node 228 and node 232. The resistor 210 is coupled between node 232 and ground node 230. The amplifier 212 has a first input terminal (e.g., negative or inverting input terminal) coupled to node 232, a second input terminal (e.g., positive or non-inverting input terminal) coupled to node 234, and an output terminal. The comparator 214 has a first input terminal (e.g., positive or non-inverting input terminal), a second input terminal (e.g., negative or inverting input terminal) coupled to the output terminal of the amplifier 212, and an output terminal. The latch 216 has a reset input terminal, a set input terminal, and an output terminal coupled to the output terminal of the comparator 214. The PWM generator 218 has an input terminal coupled to node 238, a first output terminal coupled to the set input terminal of the latch 216, and a second output terminal coupled to an input terminal of the adder 220. The adder 220 further has another input terminal configured to receive a signal (IL) indicative of the current flowing through the power converter 110. The output terminal of the latch 216 is coupled to the gate terminal of the FET 202. The output terminal of the latch 216 is further coupled to the gate terminal of the FET 204 through an inverter 222. In other examples, the inverter 222 is omitted, and the inverted output terminal (not shown) of the latch 216 is coupled to the gate terminal of the FET 204.

[0025] In an example of operation, the controller 108 controls the power converter to generate an output voltage (VOUT) at node 228 based at least in part on an input voltage (VIN) received at node 224. Based on the PWM output signal (PWM2) of the latch 216, the FETs 202 and 204 are controlled to be conductive or non-conductive, thereby generating VOUT from VIN. The resistor 208 and the resistor 210 together form a voltage divider having an output at node 232. The signal present at node 232 is a feedback signal (FB), which is a scaled representation of VOUT scaled based on the ratio of the resistances of the resistor 208 and the resistor 210. The amplifier 212 is an error amplifier, and its output indicates a signal ERROR that is the difference between FB and a reference voltage (VREF) received at node 234 that indicates the desired value of VOUT. The adder 220 receives IL and a slope compensation signal (COMP) and generates an output signal. The comparator 214 receives ERROR and the output signal of the adder 220, and compares the received signals. When the output signal of the adder 220 exceeds ERROR, the comparator 214 outputs a signal (COMP2) having a logic high value. When the output signal of the adder 220 is less than ERROR, the comparator 214 outputs COMP2 having a logic low value. The latch 216 receives COMP2 at a reset input terminal and receives a signal PWM1 at a set input terminal. When PWM1 is asserted, the latch 216 outputs PWM2 having an asserted value. When COMP2 is asserted, the latch 216 outputs PWM2 having a de-asserted value. When PWM2 is asserted, the FET 202 is controlled to be conductive, and the FET 204 is controlled to be non-conductive. Similarly, when PWM2 is de-asserted, the FET 202 is controlled to be non-conductive, and the FET 204 is controlled to be conductive.

[0026] The PWM generator 218 is configured to receive a clock signal (CLK) at node 238 and generate PWM1 and COMP. For example, based on CLK, the PWM generator 218 generates PWM1 as a modulation of at least two signals. CLK is generated according to any suitable circuit and according to any suitable process, the scope of which is not limited herein. As Figure 2As described, in at least some embodiments, PWM1 is a dither clock signal and COMP is a dither compensation signal. In one example, the PWM generator 218 receives CLK and divides the frequency of CLK to generate a divided clock signal. In at least one embodiment, the PWM generator 218 generates a triangular ramp signal or a signal having any other suitable profile based on the divided clock signal. In some examples, the PWM generator 218 generates another triangular ramp signal or a signal having any other suitable profile based on CLK or based on a second divided clock signal. In other examples, the PWM generator 218 generates a PRSS signal such as output by a register (such as a linear feedback shift register (LFSR)). The PWM generator 218 then adds the generated signals (e.g., ramp signal + ramp signal, ramp signal + PRSS signal, etc.) to generate a DRSS signal. In some examples, the DRSS signal is output as COMP by the PWM generator 218. The PWM generator 218 further generates PWM1 based on the DRSS signal, e.g., fine-tuning an oscillator (not shown) that generates PWM1 based on the DRSS signal.

[0027] Turning now to Figure 3 , a schematic diagram illustrating an exemplary PWM generator 300 is shown. In at least some examples, the PWM generator 300 is suitable for implementation in any device or system that receives CLK and generates a dithered PWM signal. For example, the PWM generator 300 is suitable for implementation in some SMPS architectures, such as being implemented as the PWM generator 218 in the SMPS104 of the present disclosure. In other examples, the PWM generator 300 is suitable for implementation in other systems that generate a PWM signal based on CLK but are not SMPS. For example, in a device that includes an input pin (such as a clock synchronization or sync pin or input) for providing a clock signal, the PWM generator 300 is suitable for being coupled to the input pin for providing the PWM signal at an output terminal. Additionally, at least some of the signals present in the PWM generator 300 are described in Figure 4 FIG. 400 of Figure 4 . Thus, by viewing the signals described in Figure 3 , the understanding of the operation of the PWM generator 300 illustrated in the schematic diagram of Figure 4 is further enhanced. The signals described in

[0028] In at least one instance, the PWM generator 300 includes a clock divider 302, a ramp generator 304, a register 306, an adder 308, and an oscillator 310. In at least some instances, the register 306 is a linear feedback shift register that is clocked by CLK and has multiple output taps each outputting a digital data bit. In at least some instances, the register 306 is not included within the PWM generator 300 but rather is a component of a system that implements the PWM generator 300 and to which the PWM generator 300 is configured to couple. In at least one instance, the clock divider 302 is configured to receive CLK and generate CLK_DIV. The clock divider 302 is further configured to receive one or more data bits output by the register 306. In at least some instances, which particular data bits of the output register 306 (e.g., which positions in the register 306) is a matter of design choice. In at least some instances, the clock divider 302 generates CLK_DIV by dividing CLK according to at least some of the data bits received from the register 306. Because the clock divider 302 generates CLK_DIV based on the data bits received from the register 306, the frequency of CLK_DIV varies as the value of the data bits output by the register 306 changes. In this way, the frequency of CLK_DIV varies with the clock cycle.

[0029] The ramp generator 304 is coupled to the clock divider 302 and is configured to receive CLK_DIV. Based on CLK_DIV, the ramp generator 304 generates a ramp signal and outputs multiple data bits (e.g., RAMP_BIT0, RAMP_BIT1... RAMP_BITX) representing the value of the ramp signal for each clock cycle of CLK_DIV. In at least some instances, the data bits output by the ramp generator 304 include a digital representation of an analog signal (e.g., a digital representation of a triangular waveform). However, in other instances, the ramp generator 304 outputs the ramp signal in analog format. The adder 308 receives at least some of the data bits output by the ramp generator 304 and the data bits output by the register 306, adds the data bits output by the register 306 to the data bits output by the ramp generator 304 to generate a DRSS signal, and outputs the DRSS signal as multiple data bits (DRSS_BIT0, DRSS_BIT1... DRSS_BITX). In at least some instances, the data bits output by the register 306 (e.g., PR_BIT0, PR_BIT1, etc.) include a PRSS signal.

[0030] Oscillator 310 is configured to receive a plurality of data bits output by adder 308. In at least some instances, oscillator 310 generates a PWM signal by charging and discharging a capacitor (not shown). In this manner, in at least some instances, the output terminal of oscillator 310 is coupled to the output node of PWM generator 300, or is the output node of PWM generator 300. In at least some instances, oscillator 310 charges the capacitor by supplying current to the capacitor via a programmable current source (not shown). The current output by the variable current source is determined according to the plurality of data bits output by adder 308, and thus the charging rate of the capacitor is determined. In this manner, a PWM signal is generated according to the plurality of data bits output by adder 308 such that it varies according to the ramp signal generated by ramp generator 304 and the output bits of register 306.

[0031] Temporarily turning to Figure 5 , illustration diagram 500 showing signal waveforms is presented. Diagram 500 illustrates signal 505, signal 510, and signal 515. In at least one instance, signal 505 is a ramp signal generated by Figure 3 ramp generator 304, signal 510 is a PRSS signal output by Figure 3 register 306, and signal 515 is the output of Figure 3 adder 308. In at least some instances, signal 515 further indicates the output of oscillator 310 such that signal 515 indicates the switching frequency (f_sw) of a power converter that will control the output of oscillator 310. The y-axis of diagram 500 represents frequency, and the x-axis of diagram 500 represents time. During the time period shown as t1 in diagram 500, f_sw remains substantially constant. During this time period, dithering according to the present disclosure is deactivated. During the time period shown as t2 in diagram 500, dithering is enabled according to the present disclosure, and the value of the switching frequency f_sw during t2 varies within a bandwidth that is approximately 0.156 times that of f_sw during t1. Additionally, in at least some instances, signal 505 varies in frequency within a bandwidth of f_h, and signal 510 varies in frequency within a bandwidth of f_l, where f_l is less than f_h.

[0032] Returning to Figure 3, in at least some instances, the PWM generator 300 includes one or more components (not shown) configured to bypass the adder 308. For example, in some cases, it may be preferable to bypass the adder 308 to characterize, monitor, or otherwise observe the data bits output by the ramp generator 304. In other instances, the components configured to bypass the adder 308 enable the PWM generator 300 to be selectively configured to operate in DRSS mode or ARSS mode. For example, in one implementation, a multiplexer is coupled between each output terminal of the register 306 and the adder 308. For example, each multiplexer receives the corresponding data bit output by the register 306 at a first input terminal, the second input terminal of the multiplexer is coupled to a ground node, and the output terminal of the multiplexer is coupled to the adder 308. Each multiplexer is configured to receive the same select signal such that the PWM generator 300 can be configured to bypass the generation of the DRSS signal and instead generate a periodic analog-type waveform by selecting the second input of each of the multiplexers, as described above. In another instance, a multiplexer is coupled between each output terminal of the ramp generator 304 and the oscillator 310. For example, each multiplexer receives the corresponding data bit output by the ramp generator 304 at a first input terminal, the second input terminal of the multiplexer is coupled to the corresponding output of the adder 308, and the output terminal of the multiplexer is coupled to the oscillator 310. Each multiplexer is configured to receive the same select signal such that the PWM generator 300 can be configured to bypass the generation of the DRSS signal and instead generate a periodic analog-type waveform by selecting the second input of each of the multiplexers, as described above.

[0033] In some instances, such as a current mode power converter, a slope compensation signal is generated by a controller for compensating an error signal generated by the controller for controlling the power converter. In such instances, the slope compensation signal is fine-tuned based on the same input as the input received by the oscillator 310 (e.g., Figure 3 the DRSS_BIT0, DRSS_BIT1... DRSS_BITX, collectively referred to as signal COMP in Figure 2 ). Fine-tuning the signal includes modifying and / or generating the value of the signal at a particular time point based on the value of the signal on which the fine-tuning is based. Fine-tuning the slope compensation signal based on the same input as the input received by the oscillator 310 minimizes the ripple in the output voltage of the power converter. In other instances, such as a voltage mode power converter, instead, the voltage ramp is fine-tuned based on the same input as the input received by the oscillator 310, thereby again minimizing the ripple in the output voltage of the power converter.

[0034] Additionally, in at least some instances, although not shown in Figure 3 the PWM generator 300 includes a second ramp generator and may further include a second clock divider. The second ramp generator and / or the second clock divider generate a second ramp signal together in a manner generally similar to the clock divider 302 and the ramp generator 304. In some instances, the output of the second ramp generator has a higher frequency than the output of the ramp generator 304. In such instances, the output of the second ramp generator is provided to the adder 308 in place of the output of the register 306 (e.g., in place of PR_BIT0 and PR_BIT1).

[0035] Turning now to Figure 6 , an illustrative diagram 600 of signal waveforms is shown. In at least some instances, diagram 600 illustrates a plurality of signals present in the Figure 3 circuit 300. Thus, at least some components and / or signals of the Figure 3 may be referred to when describing diagram 600. Diagram 600 illustrates signal 605, signal 610, and signal 615. In at least one instance, signal 605 is a ramp signal generated by the Figure 3 ramp generator 304, signal 610 is another ramp signal, and signal 615 is the output of the Figure 3 adder 308 (e.g., when the adder 308 receives signal 605 and signal 610 as inputs, receiving signal 610 in place of the PRSS signal). In at least some instances, signal 615 further indicates the output of the oscillator 310 such that signal 615 indicates the f_sw of a power converter controlled at least in part based on the output of the oscillator 310. The y-axis of diagram 600 represents frequency, and the x-axis of diagram 600 represents time. As illustrated in diagram 600, in at least some instances, the bandwidth of signal 605 is greater than the bandwidth of signal 610, and the bandwidth of signal 615 is approximately equal to the bandwidth of signal 605 and 610 added together.

[0036] Turning now to Figure 7 , a flowchart of an illustrative method 700 is shown. In at least some instances, method 700 is a method for generating a PWM signal. In some instances, the frequency of the PWM signal changes with each clock cycle. For example, in at least some embodiments, the PWM signal is generated according to combining multiple spread spectrum schemes or modulating DRSS dithering when generating the PWM signal. In some instances, method 700 is implemented in a PWM generator of the PWM generator 300 as in Figure 3 .

[0037] At operation 705, a clock signal is received. In at least some instances, the clock signal is CLK, as described above. In some instances, the clock signal is the output of an oscillator, a PWM generator, or another circuit capable of generating a clock signal. At operation 710, the clock signal is divided to form a divided clock signal. In at least some instances, the divided clock signal is CLK_DIV, as described above. In at least some instances, the clock signal is divided according to the output of a linear feedback shift register. In other instances, the clock signal is divided by any other suitable value. In at least some instances, the value varies with the clock period to prevent the divided clock signal from remaining at the same frequency for multiple consecutive clock periods.

[0038] At operation 715, a first signal is generated according to a dithering scheme. The first signal is, for example, an analog ramp, or a plurality of data bits representing an analog ramp. In other instances, the first signal is an ARSS signal or a periodic analog-type waveform, as described above. In still other instances, the first signal is a PRSS signal. In at least one implementation, the first signal is generated by a ramp generator. The first signal is generated according to the divided clock signal generated at operation 710 such that the frequency of the first signal changes with the clock period.

[0039] At operation 720, a second signal is generated according to a dithering scheme. The second signal is, for example, an analog ramp, or a plurality of data bits representing an analog ramp. In other instances, the second signal is an ARSS signal or a periodic analog-type waveform, as described above. In still other instances, the second signal is a PRSS signal. In some instances, the dithering scheme at operation 720 is the same as the dithering scheme at operation 715. In other instances, the dithering scheme at operation 720 is different from the dithering scheme at operation 715. In at least one implementation, for example, the second signal is generated based on one or more bits output by a linear feedback shift register such that the one or more bits form a PRSS signal.

[0040] At operation 725, the first signal is modulated by or with the second signal. In some instances, the first signal is modulated by the second signal by adding the second signal to the first signal. In some instances, the modulated first signal is a DRSS signal. In at least some instances, modulating the first signal with the second signal combines the dithering scheme of the first signal with the dithering scheme of the second signal. In some instances, combining the dithering scheme of the first signal with the dithering scheme of the second signal results in a greater variation in the switching frequency between consecutive clock periods than an alternative method using a single dithering scheme (e.g., ARSS, PRSS, or analog dithering).

[0041] At operation 730, an oscillator is fine-tuned according to the DRSS signal generated at operation 725 to generate a PWM signal. In at least some instances, fine-tuning the oscillator according to the DRSS signal causes the oscillator to generate a PWM signal having a frequency that changes as the value of the DRSS signal changes. The frequency changes according to a first signal generated at operation 715 and a second signal generated at operation 720. Changing the frequency of the PWM signal according to the first signal and the second signal enables a switching component controlled according to the PWM signal to improve EMI performance within a frequency range in which the first signal is optimized and within a frequency range in which the second signal is optimized. For example, when the first signal is an analog ramp signal, the first signal is optimized for improving EMI performance at low frequencies. Similarly, when the second signal is a PRSS signal, the second signal is optimized for improving EMI performance at high frequencies. Thus, by modulating the first signal with the second signal at operation 725 and generating a PWM signal according to the modulated signal at operation 730, the PWM signal becomes optimized for improving EMI performance at low and high frequencies.

[0042] At operation 735, a power converter is controlled according to the PWM signal to generate an output voltage from an input voltage. For example, the PWM signal drives a gate terminal of at least one power transistor of the power converter (or drives a gate driver that in turn drives the gate terminal) such that the power transistor is turned on and off, thereby enabling or disabling current flowing through the power transistor to generate VOUT.

[0043] Now turning to Figure 8 , Table 800 showing illustrative pseudocode is presented. In at least some instances, the present disclosure may be implemented, at least in part, via software. For example, Figure 7 at least some operations of method 700 may be performed by programming a processor to perform specific tasks. Table 800 illustrates an example of pseudocode for performing such programming. However, the pseudocode of Table 800 is merely one way to program a processor to perform the functions of the present disclosure, and other methods for achieving the same or similar results are also covered by the present disclosure.

[0044] As illustrated in Table 800, variables clk_frequency, clk_divided_frequency, clk_divided_frequency_2, and pseudo_random are defined. A random number (rand) is generated. Subsequently, a first ramp signal (ramp) is generated and a second ramp signal (ramp_2) is generated. Subsequently, DRSS is generated by adding ramp to rand (e.g., to modulate ramp according to rand, which is a PRSS signal in some examples) or by adding ramp to ramp_2. Based on DRSS, the frequency of a clock signal is modified.

[0045] In the foregoing discussion, the terms "comprising" and "including" are used in an open-ended manner and are thus to be interpreted as meaning "including but not limited to". The term "coupled" is used throughout this specification. The term can encompass a connection, communication, or signal path that implements a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B, or in a second instance, where intervening component C does not substantially change the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A, device A is coupled to device B via intervening component C. A device "configured to" perform a task or function can be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by the manufacturer, and / or can be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof. Additionally, a circuit or device that is described as including certain components can alternatively be configured to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) can alternatively include only semiconductor elements (e.g., semiconductor die and / or integrated circuit (IC) packages) within a single physical device and can be configured to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.

[0046] Although certain components are described herein as belonging to a particular processing technology (e.g., FET, metal oxide semiconductor FET (MOSFET), n-type, p-type, etc.), these components can be exchanged with components of other processing technologies (e.g., replacing a FET and / or MOSFET with a BJT, replacing an n-type with a p-type or vice versa, etc.) and the circuit including the replacement components can be reconfigured to provide a desired functionality that is at least partially similar to the functionality available prior to the component replacement. Unless otherwise stated, a component described as a resistor generally represents any one or more elements that are coupled in series and / or in parallel to provide the amount of impedance represented by the stated resistor. Additionally, the use of the phrase "ground voltage potential" in the foregoing discussion is intended to include chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of the present disclosure. Unless otherwise stated, "about", "substantially", or "generally" in front of a value means + / - 10% of the stated value.

[0047] The foregoing discussion is intended to illustrate the principles and various examples of the present disclosure. Once the foregoing disclosure is fully understood, many variations and modifications will become obvious to those skilled in the art. The present disclosure is intended to embrace all such variations and modifications.

Claims

1. A circuit, comprising: A clock divider having a clock divider input, a first signal input, and a clock output; A ramp generator having a ramp clock input and a ramp generator output, wherein the ramp clock input is coupled to the clock output; And An adder having a first adder input, a second adder input, and an adder output, wherein the first adder input is coupled to the first signal input, and the second adder input is coupled to the ramp generator output.

2. The circuit according to claim 1, further comprising an oscillator having an oscillator input and a pulse width modulation (PWM) output, wherein the oscillator input is coupled to the adder output.

3. The circuit according to claim 2, having a clock terminal, a slope compensation terminal, and a PWM terminal, wherein the clock terminal is coupled to the clock divider input, the slope compensation terminal is coupled to the adder output, and the PWM terminal is coupled to the PWM output.

4. The circuit according to claim 1, further comprising a register having a register clock input and a register output, wherein the register clock input is coupled to the clock divider input, and the register output is coupled to the first signal input and the first adder input.

5. The circuit according to claim 4, wherein the register is a linear feedback shift register.

6. The circuit according to claim 1, wherein the adder is configured to generate a dual random spread spectrum (DRSS) signal at the adder output based on a triangular signal at the second adder input and a pseudo random spread spectrum (PRSS) signal at the first adder input.

7. The circuit according to claim 1, wherein the clock divider is configured to: Receive an input clock signal at the clock divider input; Receive a data value at the first signal input; and Generate an output clock signal at the clock output by dividing the input clock signal by the data value.

8. The circuit according to claim 1, wherein the ramp generator is configured to: Receive the output clock signal at the ramp clock input; Generate a ramp signal; and Generate data representing the value of the ramp signal at the ramp generator output.

9. A pulse width modulation (PWM) generator configured to: Generate a first signal having a first jitter profile and a first frequency bandwidth; Generate a second signal having a second jitter profile and a second frequency bandwidth greater than the first frequency bandwidth; Modulate the first signal with the second signal to generate a third signal; and Generate a PWM signal in response to the third signal.

10. The PWM generator according to claim 9, wherein the first signal performs spread spectrum jitter in a low frequency band, and the second signal performs spread spectrum jitter in a high frequency band.

11. The PWM generator according to claim 10, wherein the first signal is a triangular signal, the second signal is a pseudo random spread spectrum (PRSS) signal, and the third signal is a dual random spread spectrum (DRSS) signal.

12. The PWM generator according to claim 9, wherein modulating the first signal with the second signal includes adding the first signal to the second signal.

13. The PWM generator according to claim 9, wherein generating the PWM signal in response to the third signal includes: modulating the third signal with a fourth signal to generate a fifth signal; and generating the PWM signal based on the fifth signal.

14. The PWM generator according to claim 9, wherein the first signal is a first digital signal representing an analog signal, the second signal is a second digital signal, and the third signal is a third digital signal.

15. A power supply, comprising: a power converter; and a controller coupled to the power converter, wherein the controller includes a pulse width modulation (PWM) generator configured to: generate a first signal and a second signal; modulate the first signal with the second signal to generate a third signal; and generate a PWM signal in response to the third signal, wherein the power converter is configured to generate an output voltage in response to an input voltage and the PWM signal; and an adder having a first adder input, a second adder input, and an adder output, wherein the first adder input is coupled to the power converter, and the second adder input is configured to receive the third signal; a comparator having a first comparator input, a second comparator input, and a comparator output, wherein the first comparator input is coupled to the adder output; and a latch having a reset input, a set input, and a latch output, wherein the reset input is coupled to the comparator output, the set input is configured to receive the PWM signal, and the latch output is coupled to the power converter.

16. The power supply according to claim 15, wherein the first signal performs spread spectrum jitter in a low frequency band, and the second signal performs spread spectrum jitter in a high frequency band.

17. The power supply according to claim 16, wherein the first signal is a triangular signal, the second signal is a pseudo-random spread spectrum (PRSS) signal, and the third signal is a double random spread spectrum (DRSS) signal.

18. The PWM generator according to claim 15, wherein modulating the first signal with the second signal includes adding the first signal to the second signal.

19. The PWM generator according to claim 15, wherein generating the PWM signal in response to the third signal includes: modulating the third signal with a fourth signal to generate a fifth signal; and generating the PWM signal based on the fifth signal.

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