Controller of DCDC converter with ultra-low static power consumption and low output voltage ripple

Abstract

The invention discloses a controller of a DCDC converter with ultralow static power consumption and low output voltage ripples, and belongs to the technical field of controllers of DCDC converters, the bias current of a comparator and the falling edge of a triangular wave are adjusted through a control word LD [2: 0] of a self-adaptive triangular wave module, the punch-through current of the comparator is greatly reduced, and meanwhile, the output voltage ripple of the comparator is reduced. An extra load current detection module is removed, and unnecessary power consumption sources are reduced, so that the static power consumption of the DCDC controller can meet the mu A-level static power consumption requirement of the Internet of Things terminal equipment, the battery life of the equipment is effectively prolonged, the trouble of frequent charging is reduced, the user experience is improved, and by taking a common wearable bracelet as an example, the user experience is improved. After the controller is adopted, the standby time is prolonged by several times compared with that of a traditional PWM controller, the practicability of equipment is remarkably improved, self-adaptive triangular waves and output voltage are superposed, a stable voltage feedback mechanism is constructed, subharmonic oscillation is effectively eliminated through the design, and output voltage ripples are strictly controlled.

Description

Technical Field

[0001] The present invention relates to a controller for a DCDC converter, and particularly to a controller for a DCDC converter with ultra-low static power consumption and low output voltage ripple, belonging to the technical field of controllers for DCDC converters. Background Art

[0002] In the era of rapid technological development today, various electronic devices have increasingly stringent requirements for power management, especially in the fields of Internet of Things (IoT) terminal devices and medical implant devices.

[0003] For IoT terminal devices, products such as wearable devices and wireless sensor nodes usually need to be in a standby state for a long time.

[0004] To extend the battery life of the device, strict requirements in the μA level are put forward for the static power consumption of the power system.

[0005] However, traditional PWM (Pulse Width Modulation) controllers are difficult to meet this requirement, and their static power consumption is often greater than 50 μA.

[0006] This means that IoT terminal devices using traditional PWM controllers will consume more power during standby, greatly limiting the usage duration and application scenario expansion of the devices.

[0007] In the field of medical implant devices, the situation is even more special.

[0008] Such devices are directly implanted into the human body and have extremely high requirements for safety and stability.

[0009] Among them, the output voltage ripple is a key indicator. For example, medical implant devices require that the output voltage ripple must be less than 10 mVpp. Existing power management solutions using the PFM (Pulse Frequency Modulation) mode have serious output voltage ripple deterioration under light load, with a typical value greater than 50 mVpp, far exceeding the safety standards of medical implant devices.

[0010] Moreover, the PFM mode may also have interference problems of subharmonic oscillation.

[0011] This subharmonic oscillation will affect the normal operation of the device and may even pose a potential threat to human health.

[0012] To solve the above problems, researchers have made many attempts.

[0013] However, there are many difficulties in reducing the static power consumption and controlling the output voltage ripple.

[0014] For example, when attempting to reduce the static current of a comparator, it often leads to an increase in the output voltage ripple; while when striving to control the output voltage ripple, it may increase the through-current of the comparator, thereby increasing the static power consumption of the entire system.

[0015] In addition, in traditional solutions, in order to detect the load current, an additional load current detection module needs to be set up, which not only increases the complexity of the circuit but also brings additional power consumption.

[0016] These problems severely restrict the development of power management technology in related fields and urgently require a new solution to break through the existing dilemma. Therefore, a controller for a DCDC converter with ultra-low static power consumption and low output voltage ripple is designed to solve the above problems. Summary of the Invention

[0017] The main object of the present invention is to provide a controller for a DCDC converter with ultra-low static power consumption and low output voltage ripple.

[0018] The object of the present invention can be achieved by adopting the following technical solutions: A controller for a DCDC converter with ultra-low static power consumption and low output voltage ripple, an adaptive triangular wave group, and the adaptive triangular wave group is added to the output voltage to form VRAMP and input it to the comparator CMP1; The comparator CMP1 outputs VON; The output end of the adaptive triangular wave group is also coupled to the comparator CMP2, and the positive pole of the comparator CMP2 is coupled to the output voltage; The comparator CMP2 outputs VOFF.

[0019] Preferably, the output voltage is also coupled to the adaptive triangular wave group; The adaptive triangular wave group and the comparator CMP1 perform current acquisition through the IB current acquisition table.

[0020] Preferably, the adaptive triangular wave group includes an adaptive triangular wave logic module, and the adaptive triangular wave logic module is coupled to the output ends of the comparator CMP3 and the comparator CMP4.

[0021] Preferably, the positive pole of the comparator CMP3 is coupled to VOS, and the negative pole of the comparator CMP3 inputs VRAMP2; The positive pole of the comparator CMP4 is also coupled to VOS, and the negative pole of the comparator CMP4 inputs VRAMP.

[0022] Preferably, one end of the adjustment resistor R1 is connected to the ammeter I2 through a switch, the other end of the adjustment resistor R1 is electrically connected to the S end of the mos tube M5, the D end of the mos tube M5 outputs the current IB, and the G end of the mos tube M5 is electrically connected to the G end of the mos tube M4 and connected to the S end of the mos tube M3.

[0023] Preferably, the S terminal of MOS transistor M4 is electrically connected to the S terminal of MOS transistor M5 and the S terminal of MOS transistor M1; The G terminal of MOS transistor M1 is electrically connected to the D terminal of MOS transistor M3, and the G terminal of MOS transistor M3 is electrically connected to the G terminal of MOS transistor M2 and connected to an ammeter.

[0024] Preferably, the S terminal of MOS transistor M2 is electrically connected to the D terminal of MOS transistor M1 and the Gdaunt of MOS transistor M1, the G terminal of MOS transistor M4 is electrically connected to one end of capacitor C1, and the other end of capacitor C1 is electrically connected to the S terminal of MOS transistor M6.

[0025] Preferably, the D terminal of MOS transistor M6 is electrically connected to the D terminal of MOS transistor M4 and the G terminal of MOS transistor I3.

[0026] Preferably, the S terminal of MOS transistor I3 is electrically connected to one end of capacitor CR and connected to a switch, and the other end of MOS transistor I3 is electrically connected to the negative pole of comparator CMP4.

[0027] Advantageous technical effects of the present invention: The controller of the DCDC converter provided by the present invention with ultra-low static power consumption and low output voltage ripple adjusts the comparator bias current through the control word LD[2:0] of the adaptive triangular wave module, greatly reducing the comparator punch-through current.

[0028] At the same time, the extra load current detection module is removed, reducing unnecessary power consumption sources.

[0029] This enables the static power consumption of the DCDC controller to meet the μA-level static power consumption requirements of Internet of Things terminal devices, effectively extending the battery life of the device, reducing the trouble of frequent charging, and improving the user experience.

[0030] Taking a common wearable bracelet as an example, after adopting this controller, its standby time is extended several times compared with using a traditional PWM controller, significantly improving the practicality of the device.

[0031] The adaptive triangular wave is superimposed on the output voltage to construct a stable voltage feedback mechanism.

[0032] This design effectively eliminates subharmonic oscillations, enabling strict control of the output voltage ripple.

[0033] In application scenarios with extremely high requirements for output voltage ripple such as medical implant devices, it can ensure that the output voltage ripple is less than 10mVpp, meet the strict standards of medical devices for power supply stability, reduce the potential risks caused by voltage fluctuations to the human body, and ensure the safe and reliable operation of medical devices.

[0034] The introduced Transient Enhancement (TE) mechanism plays a key role during the transient process. When the load undergoes a mutation, the adaptive bias circuit rapidly generates an instantaneous large current I3 to quickly discharge the capacitor CR, causing VO + VRAMP to rapidly drop to intersect with VREF.

[0035] This significantly improves the dynamic response characteristics of the system, ensuring that the output voltage can still quickly stabilize and maintain the normal operation of the system under the condition of rapid load changes.

[0036] In some Internet of Things devices with high real-time requirements, such as industrial wireless sensors, they can still work stably, accurately collect and transmit data even in a complex environment with frequent load changes.

[0037] Removing the additional load current detection module not only reduces power consumption but also simplifies the circuit structure.

[0038] This makes the chip have a higher integration level, reduces the space occupied on the circuit board, lowers the production cost, and improves the production efficiency.

[0039] For mass-produced electronic devices, it can effectively control costs and enhance the competitiveness of products in the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A circuit diagram of a preferred embodiment of the controller of a DCDC converter with ultra-low static power consumption and low output voltage ripple according to the present invention; Figure 2 A circuit diagram of a preferred embodiment of the controller of a DCDC converter with ultra-low static power consumption and low output voltage ripple according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] To make the technical solutions of the present invention clearer and more definite for those skilled in the art, the present invention will be further described in detail below in conjunction with the embodiments and the drawings, but the embodiments of the present invention are not limited thereto.

[0042] This embodiment will elaborate in detail on the specific implementation manner and working process of the controller of a DCDC converter with ultra-low static power consumption and low output voltage ripple.

[0043] In terms of building the hardware circuit, it mainly includes core parts such as an adaptive triangular wave module, a comparator CMP1, a circuit for generating VRAMP, and a circuit related to the Transient Enhancement (TE) mechanism, etc.

[0044] The adaptive triangular wave module is composed of a comparator, a switch, a current mirror, MOS transistors, etc. connected in a specific manner. Its main function is to adaptively detect the inductor charging and discharging states and generate a triangular wave with a falling slope matching the load.

[0045] Taking the VRAMP generation circuit as an example, it is closely synchronized with the inductor charging process.

[0046] When the inductor is in the energy storage stage, the current I1 charges the capacitor CR, causing the VRAMP voltage to rise.

[0047] Starting from the TOFF moment, CR enters the discharge stage and discharges through the small current I2 to extend the falling time of VRAMP.

[0048] The precise control of this falling time is extremely crucial as it directly affects the static power consumption of the comparator and the regulation accuracy of the output voltage VO.

[0049] To achieve the best falling time control, the digital signal LD[2:0] is used to control the programmable current source I2.

[0050] To ensure the precise matching of LD[2:0] with the load current ILOAD, the circuit also generates a second ramp signal VRAMP2 with a longer falling time, and its falling time is controlled by LD[2:0]+1.

[0051] The controller continuously adjusts the value of LD[2:0] through an automatic successive approximation algorithm until it detects that VRAMP = VO and VRAMP2 > VO at the moment when the pulse is generated at VON, thereby determining the optimal value of LD[2:0] and achieving the automatic adaptation of the VRAMP falling time.

[0052] During the actual operation, the output voltage VO and the adaptive triangular wave are added to obtain VRAMP, and the always-active comparator CMP1 continuously compares the magnitudes of VREF and VRAMP in real time.

[0053] When VRAMP is less than VREF, the comparator CMP1 outputs the high-level VON voltage flag, which is used to start a new cycle of charging the inductor by DCDC.

[0054] At the same time, VO is also compared with the adaptive triangular wave to output the hysteresis voltage VOFF, and when VOFF reaches a specific condition, it drives DCDC to end the inductor charging process.

[0055] Regarding the possible problem of slow transient response in the VRAMP scheme; This embodiment adopts a transient enhancement (TE) mechanism.

[0056] During the transient process, the adaptive bias circuit comes into play and generates an instantaneous large current I3. I3 quickly discharges CR, causing VO+VRAMP to quickly drop and quickly intersect with the reference voltage VREF, significantly improving the dynamic response characteristics of the system.

[0057] Through the above embodiments, the controller of this DCDC converter has achieved excellent results in actual tests.

[0058] In terms of maintaining a low output voltage ripple, the output voltage ripple has been successfully controlled at an extremely low level, meeting the strict requirements for ripple in medical implant devices and the like.

[0059] In terms of static power consumption, the punch-through current of the comparator has been greatly reduced, and at the same time, an additional load current detection module has been removed, making the static power consumption of the entire controller reach the μA level, meeting the long-term standby requirements of Internet of Things terminal devices and effectively solving the problems existing in the prior art.

[0060] Working principle: Principle of adaptive triangular wave generation: The adaptive triangular wave module continuously monitors the charging and discharging states of the inductor.

[0061] When the inductor is charging, current flows into the inductor and the inductor current increases; when discharging, the inductor current decreases.

[0062] Based on these state changes, the adaptive triangular wave module generates a triangular wave with a falling slope corresponding to the charging and discharging states of the inductor through the cooperation of internal components such as comparators, switches, current mirrors, and MOS transistors.

[0063] The generated triangular wave control word LD[2:0] has a dual role. On the one hand, it is used to adjust the bias current of the comparator, thereby affecting the power consumption of the comparator; on the other hand, it is fed back to the control logic to provide key parameters for the operation of subsequent circuits.

[0064] Principle of VRAMP voltage comparison: The output voltage VO and the adaptive triangular wave are added to obtain the VRAMP signal, and this signal is compared with the reference voltage VREF.

[0065] Comparator CMP1 continuously monitors the magnitude relationship between VREF and VRAMP. When VRAMP is less than VREF, comparator CMP1 outputs the high-level VON voltage flag, and this flag is used to start the charging process of the inductor by the DCDC, opening a new inductor charging cycle.

[0066] At the same time, VO is also compared with the adaptive triangular wave alone to output the hysteresis voltage VOFF.

[0067] When VOFF meets specific conditions, it will prompt the DCDC to end the charging of the inductor, thus completing a complete inductor charging and discharging cycle and realizing the regulation of the output voltage.

[0068] Principle of Transient Enhancement Mechanism: Under normal circumstances, it may take a long time for VO + VRAMP to intersect with the reference voltage VREF, which can lead to sluggish transient response of the system. To solve this problem, a transient enhancement (TE) mechanism is introduced.

[0069] During the transient process, the adaptive bias circuit will quickly respond and generate an instantaneous large current I3.

[0070] I3 will quickly discharge the capacitor CR, causing the voltage of VO + VRAMP to drop rapidly, enabling it to intersect with VREF faster, thereby significantly improving the dynamic response characteristics of the system and ensuring that the output voltage can quickly stabilize and maintain the stable operation of the system under transient conditions such as sudden load changes.

[0071] As described above, it is only a further embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the scope disclosed by the present invention, according to the technical solution and concept of the present invention, makes equivalent substitutions or changes, all belong to the protection scope of the present invention.

Claims

1. A controller for a DCDC converter with ultra-low static power consumption and low output voltage ripple, characterized in that: An adaptive triangular wave group, which is added to the output voltage to form VRAMP and input to comparator CMP1; Comparator CMP1 outputs VON; The output terminal of the adaptive triangular wave group is also coupled to comparator CMP2, and the positive terminal of this comparator CMP2 is coupled to the output voltage; Comparator CMP2 outputs VOFF.

2. The controller of the DCDC converter with ultra-low static power consumption and low output voltage ripple according to claim 1, wherein: The output voltage is also coupled to the adaptive triangular wave group; The adaptive triangular wave group and comparator CMP1 perform current acquisition through an IB current acquisition meter.

3. The controller of the DCDC converter with ultra-low static power consumption and low output voltage ripple according to claim 2, characterized in that: The adaptive triangular wave group includes an adaptive triangular wave logic module, which is coupled to the output terminals of comparator CMP3 and comparator CMP4.

4. The controller of the DCDC converter with ultra-low static power consumption and low output voltage ripple according to claim 3, characterized in that: The positive terminal of comparator CMP3 is coupled to VOS, and the negative terminal of comparator CMP3 inputs VRAMP2; The positive terminal of comparator CMP4 is also coupled to VOS, and the negative terminal of comparator CMP4 inputs VRAMP.

5. The controller of the DCDC converter with ultra-low static power consumption and low output voltage ripple according to claim 4, characterized in that: One end of the adjusting resistor R1 is connected to the ammeter I2 through a switch, the other end of the adjusting resistor R1 is electrically connected to the S terminal of the MOS transistor M5, the D terminal of the MOS transistor M5 outputs the current IB, and the G terminal of the MOS transistor M5 is electrically connected to the G terminal of the MOS transistor M4 and connected to the S terminal of the MOS transistor M3.

6. The controller of the DCDC converter with ultra-low static power consumption and low output voltage ripple according to claim 5, characterized in that: The S terminal of the MOS transistor M4 is electrically connected to the S terminal of the MOS transistor M5 and the S terminal of the MOS transistor M1; The G terminal of the MOS transistor M1 is electrically connected to the D terminal of the MOS transistor M3, and the G terminal of the MOS transistor M3 is electrically connected to the G terminal of the MOS transistor M2 and connected to the ammeter.

7. The controller of the DCDC converter with ultra-low static power consumption and low output voltage ripple according to claim 6, characterized in that: The S terminal of the MOS transistor M2 is electrically connected to the D terminal of the MOS transistor M1 and the Gdaunt of the MOS transistor M1, the G terminal of the MOS transistor M4 is electrically connected to one end of the capacitor C1, and the other end of the capacitor C1 is electrically connected to the S terminal of the MOS transistor M6.

8. The controller of the DCDC converter with ultra-low static power consumption and low output voltage ripple according to claim 7, characterized in that: The D terminal of the MOS transistor M6 is electrically connected to the D terminal of the MOS transistor M4 and the G terminal of the MOS transistor I3.

9. The controller of the DCDC converter with ultra-low static power consumption and low output voltage ripple according to claim 8, characterized in that: The S terminal of the MOS transistor I3 is electrically connected to one end of the capacitor CR and connected to the switch, and the other end of the MOS transistor I3 is electrically connected to the negative terminal of comparator CMP4.

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