An ultra-wideband high-power load chip based on a dual-coupled feedback network

Abstract

The present invention belongs to the field of monolithic microwave integrated circuits, specifically an ultra-wideband, high-power load chip based on a dual-coupled feedback network. The chip comprises a first coupled feedback network, a second coupled feedback network, four parallel resistors, and two matching transmission lines; the four parallel resistors and the two matching transmission lines are disposed between the first and second coupled feedback networks. By arranging the four parallel resistors between the first and second coupled feedback networks, the present invention collaborates with the first, second, coupled feedback networks, and the two matching transmission lines to achieve a wider bandwidth and higher power capacity, while maintaining excellent heat dissipation characteristics within a minimal footprint.

Description

Technical Field

[0001] The invention belongs to the field of monolithic microwave integrated circuits, and in particular relates to an ultra-wideband high-power load chip based on a double-coupled feedback network. Background Art

[0002] Modern microwave systems are facing increasing power requirements. This is reflected not only in a significant increase in the system's active output power but also in a corresponding increase in the passive input power they must withstand. For example, even after 17dB of isolation, coupling, and attenuation, a residual power of 20W (43dBm) remains. This power level is still too high for modern chip-based microwave systems, requiring the energy to be absorbed and dissipated by the load. However, conventional chip-based loads cannot handle such high power, necessitating the use of discrete loads as an alternative. However, discrete loads are significantly larger than chip-based loads and require additional interface conversion for system interconnection, further increasing the size of the microwave system. Consequently, discrete loads are no longer able to meet the miniaturization requirements of modern high-power microwave systems.

[0003] The basic load circuit structure is as follows Figure 1 As shown (a high-frequency, broadband, high-power load chip disclosed in Chinese utility model patent CN206451801U adopts this structure). In this structure, Figure 1 As shown, a 50-ohm resistor is used to match a standard 50-ohm characteristic impedance microwave network. Input power is dissipated directly into this resistor. As input power increases, the length and width of the resistor need to be increased proportionally to prevent breakdown or burnout. Figure 2 is the equivalent circuit of the parasitic effect of the resistor under microwave conditions, Figure 2 Where c represents parasitic capacitance and R represents intrinsic resistance. Figure 2 As shown in the figure, due to the existence of parallel parasitic capacitance of the resistor in the microwave frequency band, Figure 1The performance of the structure shown deteriorates rapidly at high frequencies, failing to meet the requirements of broadband, high-frequency applications. The paper "A Design of a Broadband, High-Power Matched Load Circuit" (authors Hao Qing and Huang Xiquan, included in the China Institute of Electronics' 2024 National Microwave and Millimeter Wave Conference Proceedings (Volume 2), DOI: 10.26914 / c.cnkihy.2024.015943) proposes improving frequency response by connecting two resistor groups in parallel, but the maximum power capacity and bandwidth still have certain limitations. Chinese invention patent CN118075989A discloses a load structure with multiple groups connected in parallel and connected in series within each group. This structure distributes heat more evenly and improves high-frequency response through internal matching. Furthermore, Chinese invention patent CN106410341A discloses a load structure with a gradient spiral layout. While this improves high-frequency response, the processing method is specialized and not universally applicable.

[0004] Therefore, it is of great significance to study a load chip based on a universal process that can achieve larger bandwidth and greater power capacity in the smallest possible chip area and has good heat dissipation characteristics. Summary of the Invention

[0005] In view of this, the present invention proposes an ultra-wideband high-power load chip based on a dual-coupled feedback network to solve the technical problems existing in the above-mentioned existing loads.

[0006] The technical solutions adopted in the present invention are as follows:

[0007] An ultra-wideband, high-power load chip based on a dual-coupled feedback network includes a substrate and a load circuit disposed on the substrate; the load circuit includes: a first coupled feedback network and a second coupled feedback network, each having a first port, a second port, a third port, and a fourth port; four parallel resistors and two matching transmission lines are disposed between the first coupled feedback network and the second coupled feedback network, the four parallel resistors being resistors R1, R2, R3, and R4, and the two matching transmission lines being a first matching transmission line and a second matching transmission line, wherein:

[0008] The resistor R1 is provided between the first port of the first coupling matching network and the third port of the second coupling matching network, the resistor R2 is provided between the second port of the first coupling matching network and the fourth port of the second coupling matching network, the resistor R3 is provided between the third port of the first coupling matching network and the first port of the second coupling matching network, and the resistor R4 is provided between the fourth port of the first coupling matching network and the second port of the second coupling matching network, and the end thereof connected to the fourth port of the first coupling matching network is grounded;

[0009] The first end of the first matching transmission line is connected to the second port of the first coupling matching network, and the second end is connected to the first port of the second coupling matching network; the first end of the second matching transmission line is connected to the third port of the first coupling matching network, and the second end is connected to the fourth port of the second coupling matching network.

[0010] Furthermore, each coupled feedback network is composed of a primary coupled transmission line and a secondary coupled transmission line.

[0011] Furthermore, each resistor is implemented by a thin film resistor process, and its corresponding unit square resistance is 50Ω.

[0012] Furthermore, the substrate is made of a material with high thermal conductivity, preferably a silicon carbide substrate or a diamond substrate.

[0013] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0014] 1. Using a low-pass distributed structure, that is, both ends of each resistor are connected to the inductive transmission line to absorb the parasitic capacitance of the resistor, which can achieve high-frequency ultra-wideband response;

[0015] 2. The present invention avoids heat concentration by rationally arranging four parallel resistors between two adjacent sets of coupled feedback networks, thereby improving the thermal stability of the chip;

[0016] 3. The present invention adopts a coupled feedback network to replace the transmission matching transmission line, which shortens the transmission line length while balancing the power dissipation of each sub-circuit channel and avoiding the premature burning of a single sub-resistor;

[0017] 4. The present invention is based on a high thermal conductivity substrate, such as silicon carbide, diamond, etc., which makes it have more superior heat dissipation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The load circuit structure of the prior art;

[0019] Figure 2 is the equivalent circuit of the parasitic effect of the resistor under microwave conditions;

[0020] Figure 3 This is a schematic diagram of the circuit of the ultra-wideband high-power silicon carbide load chip of Example 1;

[0021] Figure 4 This is the distributed broadband power load circuit structure of Comparative Example 1;

[0022] Figure 5 For Example 1 and Figure 1 Comparison results of return loss of conventional single resistor structure;

[0023] Figure 6When the input power is 20W (43dBm), the Figure 1 Comparison results of reflected power of conventional single resistor structure;

[0024] Figure 7 is the power dissipated by each sub-resistance channel in Example 1 when the input power is 20 W (43 dBm);

[0025] Reference numerals: 1 is the first coupling feedback network, and 2 is the second coupling feedback network. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0027] Example 1, as Figure 3 As shown, this embodiment provides an ultra-wideband high-power load chip based on a dual-coupled feedback network, including:

[0028] Two sets of coupled feedback networks, the two sets of coupled feedback networks are the first coupled feedback network 1 and the second coupled feedback network 2; the first coupled feedback network 1 is composed of a primary coupled transmission line TL1a and a secondary coupled transmission line TL1b, and has a first port, a second port, a third port and a fourth port corresponding to Figure 3 a, b, g and h points; the second coupling feedback network 2 is composed of a primary coupling transmission line TL2a and a secondary coupling transmission line TL2b, and its specific first port, second port, third port and fourth port correspond to Figure 3 Points c, d, e, and f in .

[0029] Four resistors connected in parallel, namely resistor R1, resistor R2, resistor R3 and resistor R4;

[0030] Two matching transmission lines, namely a first matching transmission line TLm1 and a second matching transmission line TLm2;

[0031] Resistor R1 is connected between points a and e, resistor R2 is connected between points b and f, resistor R3 is connected between points c and g, and resistor R4 is connected between points d and h. Point h is also grounded. A first matching transmission line TLm1 is connected between points b and c, and a second matching transmission line TLm2 is connected between points f and g.

[0032] In this embodiment, resistors R1 and R2 are connected to the matching transmission line between the ports on one side of the first coupled feedback network 1, implemented by a primary coupled transmission line TL1a. Resistors R1 and R2 are connected to the ports on the one side of the second coupled feedback network 2, implemented by a secondary coupled transmission line TL2b. Resistors R3 and R4 are connected to the matching transmission line between the ports on one side of the first coupled feedback network 1, implemented by a secondary coupled transmission line TL1b. Resistors R3 and R4 are connected to the matching transmission line between the ports on one side of the second coupled feedback network, implemented by a primary coupled transmission line TL2a. This allows the high-power input signal RFin on the left side of the circuit to be cross-coupled and then fed back to the right side of the circuit, achieving power transfer and equalization and preventing premature burnout of the input-side sub-resistor R1. Furthermore, the mutual inductance within the two coupled feedback networks enhances the inductance, effectively increasing the electrical length of the microstrip line and shortening the required transmission line length. In addition, the inductive matching transmission lines and coupling lines mentioned above, together with the parasitic capacitance of the four resistors, form an LC low-pass network with ultra-wideband characteristics. Therefore, the parasitic capacitance no longer becomes a factor limiting the high-frequency response but is "absorbed" in disguise, thereby allowing the size of each sub-resistor to be further increased to meet greater power requirements.

[0033] Based on the above principles and structure, this embodiment uses a silicon carbide process to manufacture an ultra-wideband, high-power silicon carbide load chip based on a dual-coupled feedback network. Its operating frequency range is DC-38GHz. The sizes of the four resistors are determined based on the required power. That is, the width of each of the four resistors is 150μm, and theoretically, they can withstand a total effective current of 0.6A. According to the calculation formula of current, resistance and power: Where P is power (unit is W), R is resistance (unit is Ohm), I is the effective value of current (unit is A), and the maximum tolerable RF power can reach (45.5dBm).

[0034] Comparative Example 1, such as Figure 4 As shown, Comparative Example 1 shows a distributed broadband power load circuit, including: four resistors arranged in parallel, a first matching transmission line group and a second matching transmission line group. The four resistors arranged in parallel are resistor R1, resistor R2, resistor R3 and resistor R4; the first matching transmission line group is composed of matching transmission lines TL1, TL2 and TL3 connected in sequence, and the second matching transmission line group is composed of matching transmission lines TL4, TL5 and TL6 connected in sequence. As can be seen from the figure, the parasitic capacitance of each resistor is connected in parallel between the first matching transmission line group and the second matching transmission line group, and constitutes a low-pass match, so the parasitic effect can be absorbed and broadband characteristics are achieved. However, there are two problems with this structure: one is that the length of the matching transmission line is too long, resulting in an increase in the overall area of ​​the chip; the other is that the power consumed by each sub-resistance channel is uneven, which makes the first resistor easy to burn out prematurely.

[0035] Comparing Comparative Example 1 with Example 1, it can be seen that this embodiment replaces the matching transmission lines TL1 and TL6 in Comparative Example 1 with a first coupled feedback network 1, and replaces the matching transmission lines TL3 and TL4 in Comparative Example 1 with a second coupled feedback network 2. The two coupled feedback networks cross-feed back the microwave signals at both ends. This coupling introduces mutual inductance, which increases the electrical length of the equivalent microstrip line and shortens the required transmission line length. Furthermore, it forms a negative feedback loop for the signal, balancing the power distribution within each sub-resistor channel and preventing premature burnout of the first sub-resistor.

[0036] Figure 5 For Example 1 and Figure 1 Comparison results of return loss of conventional single resistor structure, Figure 5 The blue curve in the middle represents a single resistor structure, and the red curve represents the structure of the present invention. The horizontal axis is frequency (in GHz), and the vertical axis is return loss (in dB). Figure 5 As can be seen from the figure, Example 1 achieves a return loss of less than -12.5dB in the DC-12.5GHz range and less than -15dB in the 12.5-38GHz range. In contrast, the return loss of a conventional single-resistor structure fluctuates around -10dB across the entire frequency range and is only -9.1dB at 22.8GHz, far from meeting the requirements for a good load.

[0037] Figure 6 When the input power is 20W (43dBm), the Figure 1 Comparison results of reflected power of conventional single resistor structure; Figure 6 The blue curve in the middle represents a single resistor structure, the red curve represents the structure of the present invention, the horizontal axis is the frequency (unit is GHz), and the vertical axis is the reflected power (unit is W). Figure 6 As can be seen from the figure, the overall reflected power of the ultra-wideband, high-power SiC load chip in Example 1 is typically 0.5W, approximately 2.5% of the total power; while the overall reflected power of a conventional single resistor structure is typically 2W, approximately 10% of the total power. This shows that the ultra-wideband, high-power SiC load chip in Example 1 significantly reduces reflected power.

[0038] Figure 7 is the power dissipated by each sub-resistance channel in Example 1 when the input power is 20 W (43 dBm); Figure 7The red curve represents resistor R1, the blue curve represents resistor R2, the purple curve represents resistor R3, and the green curve represents resistor R4. The horizontal axis represents frequency (in GHz), and the vertical axis represents dissipated power (in W). As can be seen from the figure, the power dissipated by each subchannel does not exceed the maximum allowable power of the corresponding channel and is evenly distributed, which is beneficial for improving thermal stability.

[0039] In summary, the present invention discloses an ultra-wideband, high-power load chip based on a dual-coupled feedback network, comprising four large-size resistors, two sets of coupled feedback networks, two matching transmission lines, and one ground connection. The chip is manufactured based on a high-thermal-conductivity silicon carbide substrate process and can be integrated on a single chip, with a small size and high integration. The four sub-resistors are connected in parallel, thereby dispersing heat dissipation and improving the thermal reliability of the load. The width and length of each sub-resistor can be large enough, so the parasitic capacitance caused by them can be absorbed by the two sets of coupled feedback networks and two matching transmission lines, ensuring ultra-wideband characteristics.

[0040] Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of the present invention and are not intended to be limiting. The ultra-wideband, high-power load chip based on the dual-coupled feedback network is not only applicable to silicon carbide processes, but can also be applied to processes using other high-thermal-conductivity substrates, such as diamond, and is not limited to a specific frequency band. In addition to the DC-38GHz 20W load chip described in the examples, the present invention encompasses applications across a variety of process types, frequency bands, and power capacities.

[0041] Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that any modification or equivalent substitution of the technical solution without departing from the spirit and scope of the technical solution of the present invention shall fall within the scope of the claims of the present invention. The embodiments are intended to help understand the principles of the present invention, and the scope of protection of the present invention is not limited to the specific embodiments described. Based on the technical enlightenment disclosed by the present invention, those skilled in the art may make various modifications and combinations without departing from the essence of the present invention, and these improvements shall still fall within the scope of protection of the present invention.

Claims

1. An ultra-wideband high-power load chip based on a dual-coupled feedback network, comprising a substrate and a load circuit disposed on the substrate, characterized in that: The load circuit includes a first coupled feedback network and a second coupled feedback network, each of which has a first port, a second port, a third port, and a fourth port. Four resistors arranged in parallel and two matching transmission lines are provided between the first coupled feedback network and the second coupled feedback network. The four resistors arranged in parallel are respectively a resistor R1, a resistor R2, a resistor R3, and a resistor R4. The two matching transmission lines are respectively a first matching transmission line and a second matching transmission line, wherein: The resistor R1 is provided between the first port of the first coupling matching network and the third port of the second coupling matching network, the resistor R2 is provided between the second port of the first coupling matching network and the fourth port of the second coupling matching network, the resistor R3 is provided between the third port of the first coupling matching network and the first port of the second coupling matching network, and the resistor R4 is provided between the fourth port of the first coupling matching network and the second port of the second coupling matching network, and the end thereof connected to the fourth port of the first coupling matching network is grounded; The first end of the first matching transmission line is connected to the second port of the first coupling matching network, and the second end is connected to the first port of the second coupling matching network; the first end of the second matching transmission line is connected to the third port of the first coupling matching network, and the second end is connected to the fourth port of the second coupling matching network.

2. The ultra-wideband high-power load chip based on a dual-coupled feedback network according to claim 1, characterized in that: The first coupling feedback network and the second coupling feedback network are both composed of a primary coupling transmission line and a secondary coupling transmission line.

3. The ultra-wideband high-power load chip based on a dual-coupled feedback network according to claim 1, characterized in that: The resistors R1 , R2 , R3 and R4 are all implemented using a thin film resistor process, and their corresponding unit square resistance is 50Ω.

4. The ultra-wideband high-power load chip based on a dual-coupled feedback network according to any one of claims 1 to 3, characterized in that: The substrate is a silicon carbide substrate or a diamond substrate.

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