Method for automatically generating chip integration script and program product
By automatically generating chip integration scripts, the problems of low efficiency and high error rate of traditional manual IP integration are solved, and an efficient and reliable chip design process is realized, supporting flexible IP integration and rapid iteration.
Patent Information
- Application Number
- CN202510407657.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2025-07-11
AI Technical Summary
In traditional chip design, IP integration relies on manual writing of RTL code, resulting in low efficiency, high error rate, poor reusability and high iteration costs, which cannot meet the efficiency, reliability and flexibility requirements of modern chip designs.
By automatically generating chip integration scripts, the port, address and interrupt configuration information in the configuration file are read, the low-speed port submodule, APB bus interface and top-level files are generated, and RTL code generation is automatically processed using Python script programs.
Significantly reduce the burden on engineers, quickly generate high-quality RTL code, reduce development costs, improve chip design efficiency and reliability, and support flexible IP integration and iteration.
Smart Images
Figure CN120295610A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip design, and in particular to a method and program product for automatically generating chip integration scripts. Background Art
[0002] Traditional IP integration methods mainly rely on engineers to manually write RTL (Register Transfer Level) code. The specific process is as follows: According to the design requirements, engineers write the instantiation code of each IP module one by one, manually allocate the address space, configure the interrupt signals, and ensure the timing and protocol consistency of the bus interface. For example, if a certain chip needs to integrate 4 UART modules, the engineer needs to manually instantiate 4 UART IPs, allocate the base address and interrupt number respectively, and write the address decoding logic to generate the corresponding chip select signal (such as the PSEL signal of APB). This process not only involves a large amount of code (usually tens of thousands of lines of Verilog code), but also requires repeated verification to avoid address conflicts, signal omissions or protocol errors. However, the traditional manual integration method has significant defects: 1) Low efficiency and high error rate: Manually writing code takes an extremely long time and is extremely prone to errors due to human negligence. For example, incorrect address allocation may cause bus access conflicts, and omission of interrupt configuration may lead to function failures. 2) Poor reusability: The requirements for the type, quantity and address configuration of IPs vary greatly in different chip projects. Engineers need to rewrite the integration code for each project, and it is difficult to reuse existing results, resulting in an extended development cycle. 3) High iteration cost: When requirements change in the later stage of the project (such as increasing the number of IPs or adjusting the address space), the code needs to be modified again and comprehensively verified, significantly increasing the time and resource costs.
[0003] In summary, the traditional manual integration technology can no longer meet the requirements of modern chip design for efficiency, reliability and flexibility. There is an urgent need for a highly automated and configurable solution to reduce the development cost and accelerate the product listing cycle. Summary of the Invention
[0004] In view of the above problems, the present invention proposes the following technical solutions:
[0005] A method for automatically generating a chip integration script, comprising the following steps:
[0006] Read the content of the configuration file, which is written by the user and includes the port configuration, address configuration, and interrupt configuration of each low-speed port; the port configuration includes the name, quantity, and the clock domain to which it belongs;
[0007] Generate an integration script:
[0008] 1) Generate the top-level files of the sub-modules for all low-speed ports:
[0009] For low-speed ports with a quantity of 0, do not process;
[0010] A low-speed port with a quantity of 1 is directly integrated from the IP to generate corresponding single-port instantiation code, which serves as the top-level file of the sub-module for the corresponding low-speed port.
[0011] For low-speed ports with a quantity greater than 1, corresponding single-port instantiation code and interconnection logic are generated and encapsulated into the top-level file of the sub-module for the corresponding low-speed port.
[0012] 2) Generate the APB bus interface file:
[0013] Generate one APM bus interface file for each clock domain. Each APM bus interface file corresponding to a clock domain is generated according to the address configuration of each low-speed port in that clock domain.
[0014] 3) Generate the top-level file:
[0015] Generate the top-level file according to the APB bus interface files corresponding to each clock domain, the top-level files of the sub-modules corresponding to each low-speed port, and the interrupt configuration in the configuration file.
[0016] Preferably, the address configuration includes the base address, start address, and end address.
[0017] Preferably, the interrupt configuration is saved in the configuration file in the form of Verilog code.
[0018] Preferably, when generating the APB bus interface file, a verification process is first performed. The specific content of the verification process is as follows:
[0019] Verify whether the quantity of low-speed ports in the configuration file matches the corresponding address configuration. If not, report an error to the user.
[0020] The present invention also provides a computer program product, including a computer program, characterized in that when the computer program is executed by a processor, it implements the method described in any one of claims 1 to 4.
[0021] Advantageous effects: The present invention is generated through a script program, greatly reducing the burden on engineers and enabling the rapid generation of an integration script in the form of RTL code. Description of the Drawings
[0022] Figure 1 It is the integration block diagram of the low-speed port module of the chip in the embodiment of the present invention;
[0023] Figure 2 It is the specific content diagram of the port configuration in the embodiment of the present invention;
[0024] Figure 3 It is the specific content diagram of the address configuration in the embodiment of the present invention;
[0025] Figure 4 This is the specific content diagram of the interrupt configuration in the embodiment of the present invention;
[0026] Figure 5 This is the flowchart of the script program in the embodiment of the present invention;
[0027] Figure 6 This is the code diagram of the script program in the embodiment of the present invention;
[0028] Figure 7 This is the printed result diagram of the configuration file read by the script program in the embodiment of the present invention;
[0029] Figure 8 This is the specific content of the top-level file of the sub-module of the uart port in the embodiment of the present invention;
[0030] Figure 9 This is the schematic diagram of the incorrect configuration file when verifying the configuration file in the embodiment of the present invention;
[0031] Figure 10 This is the specific content of the APM bus interface file of the lsio clock domain in the embodiment of the present invention Figure 1 ;
[0032] Figure 11 This is the specific content of the APM bus interface file of the lsio clock domain in the embodiment of the present invention Figure 2 ; Detailed implementation manners
[0033] To make the objectives, features, and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0034] In this embodiment, the method described in the present invention is implemented using Python. It can be understood that the programming language is not limited to Python, and the same effect can be achieved using other programming languages.
[0035] Most chips basically contain many low-speed ports, such as uart, spi, i2c, can, etc. Generally, the types and quantities of ports required for the design of these ports are different in different chips; as Figure 1 shown, in this embodiment, the low-speed module of the chip has two clock domains, namely lsio and msio. Each clock domain contains several low-speed ports, and communicates with the host through the APB bus externally.
[0036] First, the user edits the configuration file, and the content of the configuration file is as follows:
[0037] The port configuration of each low-speed port, where the port configuration includes name, quantity, and the clock domain it belongs to;
[0038] The address configuration of each low-speed port, where the address configuration includes the base address, start address, and end address;
[0039] The interrupt configuration of each low-speed port, and the interrupt configuration is saved in the configuration file in the form of Verilog code;
[0040] As Figure 2 shown, it is the specific content of the port configuration in the configuration file of this embodiment. Among them, the one in the front is the port name, and the one in the back is the port quantity. If the quantity is 0, it means that this port is not used in the chip. The port name and quantity are both within the scope of a pair of comments with begin and end respectively, and each pair of comments contains the corresponding clock domain. The integration program automatically identifies the content of the port configuration according to these two comments at both ends.
[0041] As Figure 3 shown, it is the specific content of the address configuration in the configuration file of this embodiment. The address configuration includes the base address, start address, and end address, and these address configurations indicate the position of this module in the overall chip design.
[0042] As Figure 4 shown, it is the specific content of the interrupt configuration in the configuration file of this embodiment. This part of the configuration is directly written in the configuration file in the form of Verilog code, and the script program only needs to read it directly.
[0043] Next is the process of the script program generating the integration script according to the content of the configuration file. Specifically, as Figure 5 、 Figure 6 shown:
[0044] First, the script program reads the content of the configuration file, saves the port configuration and address configuration in the form of a dictionary in Python, and the printed effect is as Figure 7 shown.
[0045] 1) Generate the top-level files of the sub-modules for all low-speed ports:
[0046] For low-speed ports with a quantity of 0, no processing is performed;
[0047] For low-speed ports with a quantity of 1, directly integrate from the IP, generate the corresponding single-port instantiation code, and use it as the top-level file of the corresponding low-speed port sub-module (for example, if the quantity of the LPC port is 1, the generated top-level file is lpc_top.v);
[0048] For low-speed ports with a quantity greater than 1, instantiation code for single ports and interconnection logic corresponding to the quantity are generated, and are encapsulated into the top-level files of sub-modules corresponding to the low-speed ports (for example, if the number of uart ports is 2, the generated top-level file is uart_top.v, and the specific content is as Figure 8 shown);
[0049] 2) Generate APB bus interface files:
[0050] Verify in the configuration file whether the quantity of low-speed ports matches the corresponding address configuration. If not, an error is reported to the user;
[0051] Generate an APM bus interface file for each clock domain. Each APM bus interface file corresponding to a clock domain is generated according to the address configuration of each low-speed port in that clock domain;
[0052] As Figure 9 shown, 4 uarts are set here, but in the address configuration, there are still only two uart addresses. At this time, an error will be reported when running the script program that uart2 and uart3 cannot be found.
[0053] As Figure 10 、 11 shown, the following is the specific content of the APM bus interface file apb_bar_lsio of the lsio clock domain. A define file is generated according to the read address information, and the selected s_psel signal is determined according to the address allocation of each port to send commands to different ports.
[0054] 3) Generate the top-level file:
[0055] Generate the top-level file according to the APM bus interface files corresponding to each clock domain, the top-level files of sub-modules corresponding to each low-speed port, and the interrupt configuration in the configuration file. In this embodiment, the top-level file is lsio_region.v.
[0056] Finally, the script files generated by the script program include the top-level file, all APM bus interface files of clock domains, and the top-level files of sub-modules of all low-speed ports.
[0057] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.
Claims
1. A method for automatically generating a chip integration script, characterized in that, Including the following steps: Read the content of the configuration file written by the user, and the content includes the port configuration, address configuration, and interrupt configuration of each low-speed port; the port configuration includes the name, quantity, and the clock domain to which it belongs. Generate an integration script: 1) Generate the top-level files of the sub-modules for all low-speed ports: For low-speed ports with a quantity of 0, no processing is performed. For low-speed ports with a quantity of 1, directly integrate from the IP, generate the corresponding single-port instantiation code, and use it as the top-level file of the corresponding sub-module of the low-speed port. For low-speed ports with a quantity greater than 1, generate the corresponding number of single-port instantiation codes and interconnection logic, and package them into the top-level files of the corresponding sub-modules of the low-speed ports. 2) Generate the APB bus interface files: Generate one APB bus interface file for each clock domain, and each APB bus interface file corresponding to each clock domain is generated according to the address configuration of each low-speed port corresponding to that clock domain. 3) Generate the top-level file: Generate the top-level file according to the APB bus interface files corresponding to each clock domain, the top-level files of the sub-modules corresponding to each low-speed port, and the interrupt configuration in the configuration file.
2. The method for automatically generating a chip integration script according to claim 1, wherein The address configuration includes the base address, start address, and end address.
3. The method for automatically generating a chip integration script according to claim 1, wherein, The interrupt configuration is saved in the configuration file in the form of Verilog code.
4. A method for automatically generating a chip integration script according to claim 1, wherein When generating the APB bus interface files, a verification process is first performed, and the specific content of the verification process is: Verify whether the quantity of low-speed ports in the configuration file matches the corresponding address configuration. If not, report an error to the user.
5. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the method described in any one of claims 1 to 4.