Display driving apparatus and display apparatus including the same

Abstract

Disclosed herein are a display driving apparatus capable of avoiding the influence of high-voltage noise in driving of a display panel and a display apparatus including the same. The display apparatus includes a timing controller configured to transmit a communication signal including a blank pattern and row data at a horizontal row interval; and a source driver configured to recover the blank pattern and the row data in the communication signal and drive the display panel using the blank pattern and the row data. The timing controller may include the configuration packet in the blank pattern, and may place the configuration packet in an end period of the blank pattern.

Description

[0001] Cross - reference to related applications

[0002] This application is a divisional application of the invention patent application with application number 202010612285.X.

[0003] This application claims the priority and benefit of Korean Patent Application No. 2019 - 0174234, filed on December 24, 2019, the entire disclosure of which is incorporated herein by reference. Technical field

[0004] The present invention relates to a display device, and more particularly, to a display driving device capable of avoiding the influence of high - voltage noise in driving a display panel and a display device including the display driving device. Background art

[0005] Generally, a display device includes a display panel, a source driver, a timing controller, etc.

[0006] The source driver converts digital image data provided from the timing controller into data voltages and provides the data voltages to the display panel. The source driver can be integrated into an integrated circuit chip (IC chip) and can be configured as multiple IC chips considering the size and resolution of the display panel.

[0007] Meanwhile, the source driver drives the horizontal lines of the display panel at each frame time to display an image. When the source driver drives the display panel at horizontal line intervals, high - voltage noise may be periodically generated.

[0008] The high - voltage noise may affect the low - voltage range circuit and cause abnormal operation, and may affect the low - voltage input data input during the horizontal blanking period, thus possibly affecting the driving of the display panel.

[0009] As an example, the problem of the prior art is that when a data packet such as a scrambled reset signal is affected by high - voltage noise, important control data packets may not be received normally, and thus the display panel may not be driven normally. Summary of the invention

[0010] The present disclosure aims to provide a display driving device capable of avoiding the influence of high - voltage noise in driving a display panel and a display device including the display driving device.

[0011] According to an aspect of the present disclosure, there is provided a display device including a timing controller configured to transmit a communication signal including a blank pattern and row data at horizontal line intervals; and a source driver configured to recover the blank pattern and row data in the communication signal and drive the display panel using the blank pattern and row data. The timing controller may include a configuration packet in the blank pattern and may place the configuration packet at an end period of the blank pattern.

[0012] According to another aspect of the present disclosure, a display driving device is provided, including at least one source driver configured to recover a blank pattern and line data in a communication signal transmitted at horizontal line intervals and drive a display panel using the blank pattern and the line data. A configuration packet may be included in the blank pattern, and the configuration packet may be set to be located in an end period of the blank pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by describing exemplary embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0014] Figure 1 is a block diagram of a display device according to an embodiment;

[0015] Figure 2 is a diagram for describing a recovery protocol of a display device according to an embodiment;

[0016] Figure 3 is a diagram for describing a recovery protocol of a display device according to another embodiment;

[0017] Figure 4 is a diagram for describing a configuration protocol of a display device according to an embodiment;

[0018] Figure 5 is a diagram for describing a scrambling protocol of a display device according to an embodiment;

[0019] Figure 6 is a diagram for describing a protocol for defining a position of a configuration packet of a display device according to an embodiment. DETAILED DESCRIPTION

[0020] Embodiments disclose a display driving device and a display device including the display driving device capable of avoiding the influence of high-voltage noise in driving a display panel.

[0021] Embodiments disclose a display driving device and a display device including the display driving device, which can improve the effect of reducing electromagnetic interference (EMI) by converting transmission data into a completely random code sequence.

[0022] Embodiments disclose a display driving device and a display device including the display driving device, which allow reducing the time for operating in a configuration mode at a low frequency by defining the length of a variable data packet in a packet header to support high-speed data communication.

[0023] The embodiment discloses a display driving device and a display device including the display driving device. When a communication anomaly occurs due to an unexpected variable during communication between a timing controller and a source driver, the communication anomaly state can be restored to a normal state.

[0024] In an embodiment, a recovery protocol or a recovery mode may be defined as a protocol or a mode that makes the communication state between the timing controller and the source driver in the same state.

[0025] In an embodiment, a configuration protocol, a configuration mode, or a configuration period may be defined as a protocol, a mode, or a period for setting options of an Internet protocol (IP) for a communication link for high-speed operation in a display mode, options of a clock data recovery circuit of a source driver, options of pre-clock training, and options of an equalizer.

[0026] In an embodiment, a display mode or a display period may be defined as a mode or a period for processing configuration data and image data of a source driver.

[0027] In an embodiment, a pre-clock training or a bandwidth setting period may be defined as a mode or a period for searching and setting an optimal frequency bandwidth of a communication link for high-speed operation in a display mode.

[0028] In an embodiment, an equalizer training or an equalizer period may be defined as a mode or a period for setting an equalizer gain level to improve characteristics of a communication link for high-speed operation in a display mode.

[0029] In an embodiment, a scrambling protocol may be defined as a commitment protocol between a timing controller and a source driver, in which the timing controller scrambles transmission data into a random code sequence and sends the random code sequence to the source driver, and the source driver restores the transmission data by descrambling the random code sequence.

[0030] In an embodiment, the configuration of a horizontal blanking period may include a scrambling reset.

[0031] In an embodiment, terms such as "first", "second", etc. may be used for the purpose of distinguishing multiple elements from each other. Here, terms such as "first", "second", etc. are not intended to limit the elements.

[0032] Figure 1 is a block diagram of a display device according to an embodiment.

[0033] Referring to Figure 1 , the display device may include a timing controller TCON, a plurality of first to fifth source drivers SDIC1 to SDIC5, and a display panel.

[0034] The timing controller TCON can be connected to the first to fifth multiple source drivers SDIC1 to SDIC5 in a point-to-point manner through the first to fifth communication links CL1 to CL5.

[0035] As an example, the timing controller TCON can be connected to the first source driver SDIC1 through the first communication link CL1, and the timing controller TCON can be connected to the second source driver SDIC2 through the second communication link CL2. The timing controller TCON can be connected to the third source driver SDIC3 through the third communication link CL3, and the timing controller TCON can be connected to the fourth source driver SDIC4 through the fourth communication link CL4. The timing controller TCON can be connected to the fifth source driver SDIC5 through the fifth communication link CL5. Additionally, each of the first to fifth communication links CL1 to CL5 can be configured as a pair of differential signal channels.

[0036] The timing controller TCON can provide communication signals CEDS GEN2 + / - to the source drivers SDIC1 to SDIC5 through the first to fifth communication links CL1 to CL5 respectively.

[0037] Additionally, the first to fifth source drivers SDIC1 to SDIC5 can be connected to each other in a cascaded manner through the first to fifth locking links LL1 to LL5.

[0038] As an example, the power supply voltage terminal VCC can be connected to the first source driver SDIC1 through the first locking link LL1. The first source driver SDIC1 can be connected to the second source driver SDIC2 through the second locking link LL2, and the second source driver SDIC2 can be connected to the third source driver SDIC3 through the third locking link LL3. The third source driver SDIC3 can be connected to the fourth source driver SDIC4 through the fourth locking link LL4, and the fourth source driver SDIC4 can be connected to the fifth source driver SDIC5 through the fifth locking link LL5. Additionally, the fifth source driver SDIC5, as the last one, can be connected to the timing controller TCON through the feedback link FL.

[0039] The first source driver SDIC1 can send a first lock signal LOCK1 to the second source driver SDIC2 through the second lock link LL2, and the second source driver SDIC2 can send a second lock signal LOCK2 to the third source driver SDIC3 through the third lock link LL3. The third source driver SDIC3 can send a third lock signal LOCK3 to the fourth source driver SDIC4 through the fourth lock link LL4, and the fourth source driver SDIC4 can send a fourth lock signal LOCK4 to the fifth source driver SDIC5 through the fifth lock link LL5. Additionally, the fifth source driver SDIC5 can send a fifth lock signal RX_LOCK to the timing controller TCON through the feedback link FL. Here, the fifth lock signal RX_LOCK can indicate the communication status of at least one of the first to fifth source drivers SDIC1 to SDIC5. When a lock failure occurs in at least one of the first to fifth source drivers SDIC1 to SDIC5, the fifth lock signal RX_LOCK can be switched to a value indicating a communication abnormal state.

[0040] Figure 2 is a diagram for describing a recovery protocol of a display device according to an embodiment.

[0041] Referring to Figure 2 , when a communication abnormal state occurs due to external noise such as electrostatic discharge (ESD) during the execution of the display mode, the display device can switch from the display mode to the configuration mode.

[0042] As an example, when a lock failure occurs in at least one of the first to fifth source drivers SDIC1 to SDIC5, the fifth source driver SDIC5 can switch the level of the fifth lock signal RX_LOCK from high level to low level and provide the fifth lock signal RX_LOCK to the timing controller TCON.

[0043] When a lock failure occurs, the timing controller TCON can cause a recovery command SYNC_RST for recovering the communication state to be included in the communication signal CEDS GEN2 + / - and send the communication signal CEDS GEN2 + / - to the first to fifth source drivers SDIC1 to SDIC5 through the first to fifth communication links CL1 to CL5.

[0044] As an example, the timing controller TCON can send the recovery command SYNC_RST with a predetermined level within a predetermined time period. Additionally, after sending the recovery command SYNC_RST with a predetermined level within a predetermined time period, the timing controller TCON can send a configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5.

[0045] The first to fifth source drivers SDIC1 to SDIC5 can receive a recovery command SYNC_RST and a configuration data packet RXCFG, and can execute a configuration mode according to the configuration data packet RXCFG. Here, the configuration mode can be defined as a mode for setting IP options of the first to fifth communication links CL1 to CL5 that operate at high speed in a display mode.

[0046] In addition, compared with the display mode, the configuration mode can be set to operate in a low frequency band.

[0047] In addition, after the timing controller TCON sends the entire configuration data packet RXCFG, the timing controller TCON can send configuration completion data CFG DONE to the first to fifth source drivers SDIC1 to SDIC5.

[0048] As an example, the timing controller TCON can send configuration completion data CFG DONE having values that continuously switch between 0 and 1 within a predetermined time period to the first to fifth source drivers SDIC1 to SDIC5.

[0049] In addition, when the first to fifth source drivers SDIC1 to SDIC5 receive the configuration completion data CFG DONE from the timing controller TCON, the first to fifth source drivers SDIC1 to SDIC5 can switch from the configuration mode to the display mode.

[0050] The first to fifth source drivers SDIC1 to SDIC5 can recover a phase-locked loop (PLL) clock of an internal clock data recovery circuit (not shown) by performing clock training in a display period.

[0051] Next, after the clock training in the display period, the first to fifth source drivers SDIC1 to SDIC5 can lock a symbol boundary detection and a symbol clock by performing link training.

[0052] Next, after the link training in the display period, the first to fifth source drivers SDIC1 to SDIC5 can receive frame data sent from the timing controller TCON, convert row data included in the frame data into data voltages, and supply the data voltages to a display panel.

[0053] Figure 3 is a diagram for describing a recovery protocol of a display device according to another embodiment. In the description Figure 3 when, the repeated description of the embodiment described with reference to Figure 2 is replaced by the description of Figure 2 .

[0054] Refer to Figure 3When a communication abnormal state occurs due to external noise, the timing controller TCON can send a recovery command SYNC_RST with a predetermined level to the first to fifth source drivers SDIC1 to SDIC5 within a predetermined time period.

[0055] Next, after sending the recovery command SYNC_RST within a predetermined time period, the timing controller TCON can send a configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5.

[0056] As an example, when sending the configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5, the timing controller TCON can include a pre - clock training option and an equalizer training option in the configuration data packet RX CFG.

[0057] Next, after completing the configuration mode, the first to fifth source drivers SDIC1 to SDIC5 can perform pre - clock training to set the optimal frequency bandwidth of the first to fifth communication links CL1 to CL5 for high - speed operation in the display mode.

[0058] Next, after the pre - clock training is completed, the first to fifth source drivers SDIC1 to SDIC5 can perform equalizer training to set the equalizer gain level that can improve the characteristics of the communication links for high - speed operation in the display mode.

[0059] As an example, the timing controller TCON can repeat the pattern of equalizer clock training and equalizer link training a set number of times during the equalizer period in the previously configured mode.

[0060] The first to fifth source drivers SDIC1 to SDIC5 can change the level of the equalizer gain level by the value set in the previous configuration mode.

[0061] In addition, each of the first to fifth source drivers SDIC1 to SDIC5 can check the number of errors in the lock, symbol lock, and clock data recovery circuits according to its equalizer gain level.

[0062] In addition, the first to fifth source drivers SDIC1 to SDIC5 can compare the number of errors in the lock, symbol lock, and clock data recovery circuits according to the equalizer gain level to select the most effective equalizer gain level and accordingly set the first to fifth communication links CL1 to CL5.

[0063] Here, compared with the configuration mode, the pre - clock training and equalizer training can be set to operate in a high - frequency band.

[0064] In addition, after the equalizer training is completed, the first to fifth source drivers SDIC1 to SDIC5 can be switched to the display mode.

[0065] The first to fifth source drivers SDIC1 to SDIC5 can restore the PLL clock by performing clock training in the display mode, and can lock the symbol boundary detection and symbol clock by performing link training.

[0066] In addition, the first to fifth source drivers SDIC1 to SDIC5 can convert the row data sent from the timing controller TCON into a data voltage and supply the data voltage to the display panel.

[0067] As described above, according to the embodiment, when a communication anomaly occurs between the timing controller and the source driver due to an unexpected variable, the communication anomaly state can be restored to the normal state at a desired time, thereby preventing communication failures.

[0068] Figure 4 is a diagram for describing a configuration protocol of a display device according to an embodiment. Hereinafter, for ease of explanation, the case of performing communication between a timing controller and a source driver will be taken as an example for description.

[0069] Referring to Figure 4 , the source driver can receive a communication signal in a format having a preamble data PREAMBLE, a start data START, a configuration data CFG_DATA, an end data END, and a configuration completion data CFG_DONE from the timing controller TCON in the configuration mode. The configuration data CFG_DATA may include a packet header CFG[7:0] defining the lengths of the data packets DATA1 to DATA N .

[0070] The configuration data CFG_DATA may have the following format: a packet header CFG[7:0], data packets DATA1 to DATA N and a checksum CHECK_SUM[7:0].

[0071] The packet header CFG[7:0] may define the number of bytes of the currently exchanged data packets DATA1 to DATA N . In addition, the packet header CFG[7:0] may define the total number of the configuration data CFG_DATA sequences CFG_DATA[1] to CFG_DATA[N]. In addition, the packet header CFG[7:0] may define whether the checksum CHECK_SUM[7:0] is activated.

[0072] As an example, the header CFG [7:0] can include 8 bits, and the [0] bit of the header CFG [7:0] can be used for synchronization, the [3:1] bits of the header CFG [7:0] can be used to define the number of bytes of the data packets DATA1 to DATAN currently being exchanged, and the [6:4] bits of the header CFG [7:0] can be used to define the total number of the configuration data CFG_DATA sequences CFG_DATA [1] to CFG_DATA [N]. Additionally, the [7] bit of the header CFG [7:0] can define whether the checksum CHECK_SUM [7:0] is activated.

[0073] First, in the configuration mode, the source driver can receive the preamble data PREAMBLE that continuously switches between the 0 level and the 1 level.

[0074] Next, when the source driver continuously receives the preamble data PREAMBLE within a predetermined time period, the source driver can send a lock signal RX_LOCK indicating that the source driver is ready to receive the configuration data CFG_DATA to the timing controller TCON. As an example, the source driver can provide the lock signal RX_LOCK by switching from a low level to a high level.

[0075] Next, the timing controller TCON can send the start data START, the configuration data CFG_DATA, the end data END, and the configuration completion data CFG_DONE to the source driver in response to the lock signal RX_LOCK. Here, the start data START can be set to the level "0011", and the end data END can be set to the level "1100".

[0076] Next, after receiving the end data END "1100", the source driver can receive the configuration completion data CFG_DONE that continuously switches between the 0 level and the 1 level.

[0077] Next, when the source driver receives the configuration completion data CFG_DONE within a predetermined time period, the source driver can perform pre - clock training, equalizer training, or display mode according to the configuration data CFG_DATA.

[0078] Figure 5 is a diagram for describing the scrambling protocol of a display device according to an embodiment.

[0079] The timing controller TCON can scramble the transmission data into a pseudo - random binary sequence (PRBS) using a linear feedback shift register (LFSR), and the timing controller TCON can include the PRBS in the communication signal and send the communication signal to the source driver SDIC. The transmission data can include at least one of a control data packet, image data, and a data checksum.

[0080] As an example, the timing controller TCON may include a scrambler (not shown) for scrambling the transmitted data. Scrambling is a process of mixing each bit of the transmitted data to be sent, and can prevent the same bit (e.g., 1 or 0) from being continuously placed more than K times in the data transmission stream (where K is a natural number greater than or equal to 2). The scrambling can be performed according to a previously agreed protocol.

[0081] The LFSR is a type of shift register and may have a structure in which the value input to the register is calculated as a linear function of the previous state value. As an example, the LFSR may use an exclusive OR (XOR) operation as the linear function. Here, the initial bit value of the LFSR may be referred to as a seed, and since the operation of the LFSR is deterministic, the sequence of values generated by the LFSR can be determined by the previous values. Additionally, since the number of values that the register can have is limited, the sequence can repeat at a specific period.

[0082] The timing controller TCON can periodically change the seed value of the LFSR. As an example, the timing controller TCON can change the seed value at a frame interval or a line interval. Additionally, the timing controller TCON can use a control data packet to change the seed value. As another example, the timing controller TCON can use at least one of image data and a data checksum to change the seed value.

[0083] The timing controller TCON can calculate the value of the transmitted data input to the LFSR and the state value of the previous transmitted data through a linear function to scramble the transmitted data.

[0084] Additionally, the timing controller TCON can cause the PRBS obtained by scrambling the transmitted data to be included in the communication signal, and can send the communication signal to the source driver through the communication link.

[0085] The source driver SDIC can receive the communication signal from the timing controller TCON through the communication link, and can descramble the PRBS included in the communication signal into the transmitted data. Additionally, the source driver SDIC can use the transmitted data to drive the display panel.

[0086] As an example, the source driver SDIC may include a descrambler (not shown) configured to descramble the PRBS into the transmitted data. The descrambler can perform the function of restoring the data stream in which each bit is mixed with each other to the original data.

[0087] The source driver SDIC can receive a scramble reset signal during the blank link training period.

[0088] As an example, when the scrambling reset signal ISCR is activated, the source driver SDIC can use at least one of the control data packet, the image data, and the data checksum to descramble the PRBS, where the control data packet, the image data, and the data checksum are transmitted as the transmission data of the previous horizontal line.

[0089] As described above, the timing controller TCON can perform a scrambling reset at regular intervals, and can use at least one of the control data packet, the image data, and the data checksum transmitted as the transmission data to change the seed value each time a scrambling reset is performed.

[0090] Then, the source driver SDIC can use at least one of the control data packet, the image data, and the data checksum transmitted as the previous transmission data to descramble the PRBS.

[0091] The timing controller TCON and the source driver SDIC can perform both high-speed data communication and low-speed data communication, and can send and receive the control data packet, the image data, and the data checksum described above through high-speed data communication.

[0092] Train the clock and link for high-speed data communication during the display period, and can send and receive the control data packet, the image data, and the data checksum according to the trained clock and link.

[0093] In the display mode of the display period, after clock training and link training have been performed, the transmission data including the control data packet, the image data, and the data checksum in the frame unit and the line unit can be repeatedly sent and received.

[0094] Since the transmission data is sent and received through high-speed data communication in the display mode, the data reception rate can be changed according to the setting value for communication. To increase the reception rate and allow high-speed data communication to proceed smoothly, the timing controller TCON and the source driver SDIC can send and receive information for supporting high-speed data communication through low-speed data communication. The description related to this is replaced by the description of Figure 2 instead.

[0095] According to the above embodiment, by converting the transmission data into a completely random code sequence, the effect of reducing electromagnetic interference (EMI) can be improved.

[0096] In addition, according to an embodiment, in the method of generating the PRBS using the LFSR, a low-order polynomial can be used by controlling the seed value, thereby reducing the size of the source driver chip.

[0097] Figure 6 is a diagram according to an embodiment for describing a protocol for defining the position of a configuration packet of a display device.

[0098] The timing controller TCON can send a communication signal including a blank pattern H-BLANK and line data LINE DATA to at least one source driver SDIC at a horizontal line interval of 1-H.

[0099] The timing controller TCON can cause a configuration packet CFG to be included in the blank pattern H-BLANK and can place the configuration packet CFG in the end cycle of the blank pattern H-BLANK.

[0100] As an example, the timing controller TCON can place the configuration packet CFG in the end cycle of the blank pattern H-BLANK that is farthest from the line data LINE DATA of the previous horizontal line. The timing controller TCON can cause at least one of clock training, link training, and the configuration packet CFG to be included in the blank pattern H-BLANK. Additionally, the timing controller TCON can cause at least one of a control data packet, image data, and a data checksum to be included in the line data LINE DATA.

[0101] As another example, when the link lock signal LINK_LOCK fails, the timing controller TCON can include the configuration packet CFG in the end cycle of the blank pattern H-BLANK after restoring the link lock signal LINK_LOCK by enabling the source output enable signal SOE.

[0102] The source driver SDIC can recover the blank pattern H-BLANK and line data in the communication signal and can use the blank pattern H-BLANK and line data LINE DATA to drive the display panel.

[0103] The source driver SDIC can receive the source output enable signal SOE enabled at the horizontal line interval of 1-H and can provide the link lock signal LINK_LOCK indicating a lock failure to the timing controller TCON when a lock failure occurs after the source output enable signal is enabled.

[0104] The source driver SDIC can use at least one of clock training and link training included in the blank pattern H-BLANK to recover the link with the timing controller TCON. As an example, the source driver SDIC can recover the PLL clock by performing clock training and can lock the symbol boundary detection and symbol clock by performing link training.

[0105] The source driver SDIC can provide the link lock signal LINK_LOCK indicating link recovery to the timing controller TCON and, after link recovery, can receive the configuration packet CFG located at the end cycle of the blank pattern H-BLANK from the timing controller TCON.

[0106] For example, when the source driver SDIC receives a source output enable signal SOE, the source driver SDIC may perform the following operations: output a data voltage corresponding to image data to the display panel (①).

[0107] Here, the source driver SDIC can drive multiple output circuits simultaneously, and each output circuit corresponds to each channel of multiple data lines configured to output a data voltage to the display panel. The output circuit operates in a high-voltage region, and due to the operation of the output circuit operating in the high-voltage region, high-voltage noise can be instantaneously generated (②). The high-voltage noise can cause a link failure between the timing controller TCON and the source driver SDIC (③).

[0108] The source driver SDIC can restore the PLL clock by performing clock training and perform link training to lock symbol boundary detection and symbol clock to restore the link between the timing controller TCON and the source driver SDIC (④).

[0109] After link restoration, the timing controller TCON can include a configuration packet CFG in the end period of the blank pattern H-BLANK. A scrambled reset signal can be included in the configuration packet CFG.

[0110] The source driver SDIC can restore at least one of a control data packet, image data, and a data checksum of line data LINE DATA in response to the scrambled reset signal in the configuration packet CFG.

[0111] When a critical data packet such as a scrambled reset signal is affected by high-voltage noise, the source driver SDIC may not be able to correctly restore the control data packet, thereby possibly failing to achieve normal driving. However, according to an embodiment, by changing the protocol to appropriately restore line data including a control data packet, image data, and a data checksum, such that the configuration packet CFG including the scrambled reset signal can be received after the high-voltage noise stabilizes, thereby avoiding the high-voltage impact when driving the display panel.

[0112] The operation of the display device as described above will be described in detail below.

[0113] When the display device is powered on, the timing controller TCON can send a clock mode for clock training to the source driver SDIC. The clock mode can be sent by being included in a communication signal. The source driver SDIC receives the clock mode and can train its clock according to the clock mode. In addition, the source driver SDIC can switch the level of a lock signal from a low level to a high level after completing clock training, and send the lock signal to the timing controller TCON through a feedback link FL.

[0114] The timing controller TCON and the source driver SDIC can perform communication using the PLL mode, and in this way, the source driver SDIC can generate an internal clock based on the frequency and phase of the clock mode, and can use the internal clock to recover control packets, image data, and data checksums.

[0115] In addition, when there is a link failure between the timing controller TCON and the source driver SDIC, the display device can perform clock training again. After the clock training is completed, the timing controller TCON can send link data through the communication signal.

[0116] The source driver SDIC can receive link data according to its clock, and can train the link according to the link data. The link training can be performed at the initial stage of data transmission. In addition, when there is a link failure between the timing controller TCON and the source driver SDIC, the link training can be performed again. After the link training is completed, the timing controller TCON can send image data through the communication signal.

[0117] The image data can be sent for each frame. In addition, there may be a vertical blanking period between the image data sent for each frame.

[0118] One frame period can include a plurality of horizontal line periods 1-H respectively corresponding to a plurality of horizontal lines of the display panel.

[0119] In addition, the timing controller TCON can send image data corresponding to each horizontal line for each horizontal line period 1-H. As an example, for the timing controller TCON, each horizontal line period 1-H can include a blank pattern transmission period and a line data transmission period. The timing controller TCON can include and send a configuration packet containing a scrambled reset signal in the blank pattern during the blank pattern transmission period, and can place the configuration packet at the end period of the blank pattern (i.e., the end period of the blank pattern transmission period) and send the configuration packet to the source driver SDIC.

[0120] In addition, the timing controller TCON can send line data including control packets, image data, and data checksums to the source driver SDIC during the line data transmission period of the horizontal line period 1-H.

[0121] In addition, for the source driver SDIC, the horizontal line period 1-H can include a blank pattern reception period and a line data reception period.

[0122] The source driver SDIC can receive a configuration packet including a scrambled reset signal during a blank pattern reception period, and recover line data including a control data packet, image data, and a data checksum by using the scrambled reset signal during a line data reception period. Here, the source driver SDIC can align the image data according to the data link.

[0123] In addition, the source driver SDIC can convert the image data into corresponding data voltages in response to the control data packet, and supply the data voltages to corresponding pixels to drive the display panel.

[0124] As described above, according to the embodiment, by using the protocol between the timing controller and the source driver to avoid the influence of high-voltage noise in the display panel driving, the display panel can be stably driven.

[0125] In addition, according to the embodiment, by stably recovering the control data packet lost due to high-voltage noise, the display panel can be stably driven.

Claims

1. A display device, comprising: A timing controller configured to transmit a communication signal including a blank pattern and line data at a horizontal line interval; And A source driver configured to recover the blank pattern and the line data in the communication signal and drive a display panel using the blank pattern and the line data, Wherein the timing controller includes a configuration packet in the blank pattern and places the configuration packet at an end period of the blank pattern, Wherein the source driver recovers at least one of a control data packet, image data, and a data checksum of the line data in response to a scrambled reset signal of the configuration packet.

2. The display device according to claim 1, wherein, The timing controller places the configuration packet at the end period of the blank pattern that is farthest from the line data of the previous horizontal line.

3. The display device according to claim 1, wherein, When a fault occurs in the link lock signal, after the link lock signal is restored, the timing controller includes the configuration packet in the blank pattern.

4. The display device according to claim 1, wherein The source driver receives a source output enable signal enabled at the horizontal line interval, and provides a link lock signal indicating the lock fault to the timing controller when a lock fault occurs after the source output enable signal is enabled.

5. The display device according to claim 4, wherein, The source driver recovers a communication link through at least one of clock training and link training for lock symbol boundary detection and symbol clock.

6. The display device according to claim 5, wherein, The timing controller includes the configuration packet in the blank pattern after link recovery.

7. A display driving device, comprising at least one source driver configured to recover a blank pattern and line data in a communication signal transmitted at a horizontal line interval and drive a display panel using the blank pattern and the line data, Among them, A configuration packet is included in the blank pattern, and the configuration packet is set to be located at an end period of the blank pattern, Wherein the source driver recovers at least one of a control data packet, image data, and a data checksum of the line data in response to a scrambled reset signal of the configuration packet.

8. The display driving device according to claim 7, wherein, The configuration packet is set to be located at the end period of the blank pattern that is farthest from the line data of the previous horizontal line.

9. The display driving device according to claim 7, wherein, When a fault occurs in the link lock signal, the configuration packet is set to be included in the blank pattern after the link lock signal is restored.

10. The display driving device according to claim 7, wherein, The source driver receives a source output enable signal enabled at the horizontal line interval, and provides a link latch signal indicating the latch fault to a timing controller when a latch fault occurs after the source output enable signal is enabled.

11. The display driving device according to claim 10, wherein, The source driver recovers a communication link through at least one of clock training and link training for lock symbol boundary detection and symbol clock.

12. The display driving device according to claim 11, wherein, The source driver provides the link lock signal indicating link recovery to the timing controller and receives the configuration packet in the end period of the blank pattern.

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