Optical semiconductor integrated device

Abstract

An optical semiconductor integrated device (1) is provided with an optical modulation unit (4), and a semiconductor waveguide element unit (3) connected to the optical modulation unit (4). The light modulation unit (4) includes an active layer (42), an upper cladding layer (43), and a first semiconductor region (44) having the same conductivity type as the upper cladding layer (43). The first semiconductor region (44) is disposed in a portion between the active layer (42) and the upper cladding layer (43). A first collision ionization coefficient of the first semiconductor region (44) is smaller than a collision ionization coefficient of the upper cladding layer (43).

Description

Technical Field

[0001] The present disclosure relates to an opto-semiconductor integrated device. Background Art

[0002] Japanese Patent Application Laid-Open No. 2008-305981 (Patent Document 1) discloses a semiconductor laser element including a DFB laser and an optical modulator. In order to prevent end face damage caused by electrostatic discharge (ESD), in the semiconductor laser element of Patent Document 1, the optical modulator has a first part and a second part including an emission-side end face, and the thickness of the insulating region of the active layer of the first part is thicker than the thickness of the insulating region of the active layer of the second part.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2008-305981 Summary of the Invention

[0006] However, when increasing the thickness of the insulating region of the active layer of the first part, the electric field strength applied to the optical modulator decreases, and thus the extinction ratio of the optical modulator decreases. The present disclosure has been made in view of the above problems, and an object thereof is to provide an opto-semiconductor integrated device having improved tolerance against ESD without reducing the extinction ratio of the optical modulation unit.

[0007] The opto-semiconductor integrated device of the present disclosure includes an optical modulation unit and a semiconductor waveguide element unit connected to the optical modulation unit. The optical modulation unit includes an active layer, an upper cladding layer, and a first semiconductor region having the same conductivity type as the upper cladding layer. The first semiconductor region is disposed in a part between the active layer and the upper cladding layer. The first impact ionization coefficient of the first semiconductor region is smaller than the impact ionization coefficient of the upper cladding layer.

[0008] Therefore, in the first semiconductor region, the occurrence of impact ionization in a chain during optical modulation is suppressed. Even if a momentary high voltage is applied to the optical modulation unit due to static electricity, a large current caused by avalanche breakdown can be prevented from flowing into the optical modulation unit without increasing the thickness of the active layer. According to the opto-semiconductor integrated device of the present disclosure, the tolerance against electrostatic breakdown (ESD) can be improved without reducing the extinction ratio of the optical modulation unit. Brief Description of the Drawings

[0009] Figure 1 is a schematic plan view of the opto-semiconductor integrated device of the embodiment.

[0010] Figure 2 is of the opto-semiconductor integrated device of the embodiment, Figure 1 a schematic cross-sectional view taken along the line II-II shown.

[0011] Figure 3 is a schematic cross-sectional view of the optoelectronic integrated device of the embodiment at the indicated cross-section line III-III. Figure 1 The schematic cross-sectional view at the indicated cross-section line III-III of the optoelectronic integrated device of the embodiment.

[0012] Figure 4 is a schematic cross-sectional view of the optoelectronic integrated device of the embodiment at the indicated cross-section line IV-IV. Figure 1 The schematic cross-sectional view at the indicated cross-section line IV-IV of the optoelectronic integrated device of the embodiment.

[0013] Figure 5 is a schematic cross-sectional view of the optoelectronic integrated device of the embodiment at the indicated cross-section line V-V. Figure 1 The schematic cross-sectional view at the indicated cross-section line V-V of the optoelectronic integrated device of the embodiment.

[0014] Figure 6 is a schematic cross-sectional view of the optoelectronic integrated device of the embodiment at the indicated cross-section line VI-VI. Figure 1 The schematic cross-sectional view at the indicated cross-section line VI-VI of the optoelectronic integrated device of the embodiment.

[0015] Figure 7 is a schematic cross-sectional view of the optoelectronic integrated device of the embodiment at the indicated cross-section line VII-VII. Figure 1 The schematic cross-sectional view at the indicated cross-section line VII-VII of the optoelectronic integrated device of the embodiment.

[0016] Figure 8 is a schematic cross-sectional view of the optoelectronic integrated device of the first modification of the embodiment.

[0017] Figure 9 is a schematic cross-sectional view of the optoelectronic integrated device of the second modification of the embodiment. Detailed implementation manners

[0018] Hereinafter, embodiments of the present disclosure will be described. In addition, the same reference numerals are added to the same structures, and their descriptions will not be repeated.

[0019] Referring to Figures 1 to 7 , the optoelectronic integrated device 1 of the embodiment will be described. The optoelectronic integrated device 1 includes a laser section 2, a passive waveguide section 3, an optical modulation section 4, a spot size conversion section 5, a high reflection film 61, and an antireflection film 62. The laser section 2, the passive waveguide section 3, the optical modulation section 4, and the spot size conversion section 5 are arranged along the optical axis direction of the optoelectronic integrated device 1.

[0020] Specifically, the optoelectronic integrated device 1 includes a semiconductor substrate 10. The semiconductor substrate 10 is, for example, an n-InP substrate. The laser section 2, the passive waveguide section 3, the optical modulation section 4, and the spot size conversion section 5 share the semiconductor substrate 10. The optoelectronic integrated device 1 includes end faces 8 and 9. The end face 9 is the emission end face of the optoelectronic integrated device 1.

[0021] Referring to Figures 1 to 3, the laser unit 2 includes a semiconductor substrate 10, a lower cladding layer 11, a diffraction grating 12, a first active layer 13, an upper cladding layer 14, a current blocking layer 15, an upper cladding layer 16, a contact layer 17, an insulating protective film 22, a first electrode 25, and a second electrode 26. The laser unit 2 includes an end face 8.

[0022] The lower cladding layer 11 is disposed on the upper surface of the semiconductor substrate 10. The lower cladding layer 11 is, for example, an n-type semiconductor layer such as an n-InP layer. The diffraction grating 12 is embedded in the lower cladding layer 11. The diffraction grating 12 functions as, for example, a distributed Bragg reflector (DBR).

[0023] The first active layer 13 is disposed on the lower cladding layer 11. The first active layer 13 is, for example, a multiple quantum well (MQW) layer. The first active layer 13 is, for example, an intrinsic semiconductor layer (i-layer) that is not intentionally doped with an n-type dopant and a p-type dopant. The first active layer 13 is disposed between the lower cladding layer 11 and the upper cladding layer 14, and has a refractive index larger than that of the lower cladding layer 11 and the upper cladding layer 14.

[0024] The upper cladding layer 14 is disposed on the first active layer 13. The upper cladding layer 14 is, for example, a p-type semiconductor layer such as a p-InP layer.

[0025] The current blocking layer 15 is disposed on the upper surface of the semiconductor substrate 10. With respect to the current blocking layer 15, both side surfaces of the laminate of the lower cladding layer 11, the first active layer 13, and the upper cladding layer 14 are embedded in the current blocking layer 15. The laser unit 2 has an embedded structure. The current blocking layer 15 includes, for example, a semi-insulating semiconductor layer 15a and an n-type semiconductor layer 15b. The semi-insulating semiconductor layer 15a is disposed on the upper surface of the semiconductor substrate 10. The semi-insulating semiconductor layer 15a is, for example, an InP layer doped with Fe. The n-type semiconductor layer 15b is disposed on the semi-insulating semiconductor layer 15a. The n-type semiconductor layer 15b is, for example, an n-InP layer.

[0026] The upper cladding layer 16 is disposed on the upper cladding layer 14 and the current blocking layer (n-type semiconductor layer 15b). The upper cladding layer 16 and the n-type semiconductor layer 15b form a pn junction. The upper cladding layer 16 may be formed of the same semiconductor material as the upper cladding layer 14. The upper cladding layer 16 is, for example, a p-type semiconductor layer such as a p-InP layer.

[0027] Grooves 20 and 21 are provided in the current blocking layer 15 and the upper cladding layer 16. The grooves 20 and 21 reach the upper surface of the semiconductor substrate 10. The grooves 20 and 21 are separated into a central portion of the optoelectronic integrated device 1 located between the grooves 20 and 21 and a peripheral portion of the optoelectronic integrated device 1 located outside the grooves 20 and 21.

[0028] The insulating protective film 22 is disposed on the surfaces of the grooves 20 and 21 and on the upper cladding 16. The insulating protective film 22 is, for example, a SiO2 film. An opening is provided in the insulating protective film 22.

[0029] The contact layer 17 is disposed on the upper cladding 16 exposed from the opening of the insulating protective film 22. The contact layer 17 has the same conductivity type as the upper claddings 14 and 16, and is doped with more dopants than the upper claddings 14 and 16. The contact layer 17 is, for example, a p + -InGaAs layer.

[0030] The first electrode 25 is formed on the lower surface of the semiconductor substrate 10. The second electrode 26 is disposed on the contact layer 17. The first electrode 25 and the second electrode 26 are, for example, gold (Au) electrodes.

[0031] The upper surface of the first active layer 13 is in contact with the upper cladding 14, and the lower surface of the first active layer 13 is in contact with the lower cladding 11. The upper cladding 14, the first active layer 13, and the lower cladding 11 form a pin structure. A voltage higher than that of the first electrode 25 is applied to the second electrode 26, thereby applying a forward bias voltage to the pin structure of the laser section 2. A current is injected into the first active layer 13, so that the laser section 2 emits laser light.

[0032] The semi-insulating semiconductor layer 15a is less likely to allow current to flow than the upper cladding 14, the first active layer 13, and the lower cladding 11. Further, when a forward bias voltage is applied to the pin structure using the first electrode 25 and the second electrode 26, the pn junction formed by the upper cladding 14 and the n-type semiconductor layer 15b is applied with a reverse bias voltage, so that current is less likely to flow through the pn junction. Therefore, the current blocking layer 15 blocks the current flowing between the first electrode 25 and the second electrode 26, causing the current to concentrate on the first active layer 13.

[0033] Refer to Figure 1 、 Figure 2 and Figure 4 , the passive waveguide section 3 includes the semiconductor substrate 10, the lower cladding 11, the passive waveguide 30, the current blocking layer 15, the upper cladding 16, and the insulating protective film 22. The passive waveguide section 3 may also include the first electrode 25.

[0034] The passive waveguide 30 is disposed on the lower cladding 11. The upper cladding 16 is disposed on the passive waveguide 30. The passive waveguide 30 is disposed between the lower cladding 11 and the upper cladding 16 and has a refractive index greater than that of the lower cladding 11 and the upper cladding 16. The passive waveguide 30 is formed of a semiconductor material (such as InGaAsP) having a bandgap greater than the energy of the laser emitted from the laser section 2. The passive waveguide 30 is, for example, an intrinsic semiconductor layer. Both side surfaces of the laminate of the lower cladding 11 and the passive waveguide 30 are buried by the current blocking layer 15. The passive waveguide 30 is connected to the first active layer 13 of the laser section 2 and the second active layer 42 of the optical modulation section 4 to optically couple the first active layer 13 and the second active layer 42. The passive waveguide 30 guides the laser emitted from the laser section 2 to the second active layer 42 of the optical modulation section 4.

[0035] In the passive waveguide 30, as going from the laser section 2 toward the optical modulation section 4, the width of each of the grooves 20 and 21 gradually increases, and the width of the current blocking layer disposed between the grooves 20 and 21 gradually decreases. The width of the current blocking layer disposed between the grooves 20 and 21 becomes zero at the connection portion of the passive waveguide section 3 and the optical modulation section 4.

[0036] Refer to Figure 1 、 Figure 2 、 Figure 5 And Figure 6 , the optical modulation section 4 includes an end face 4a and an end face 4b on the side opposite to the end face 4a. The end face 4a and the end face 4b are the two end faces of the optical modulation section 4 in the optical axis direction of the optical semiconductor integrated device 1. In the present embodiment, the optical modulation section 4 is disposed between the passive waveguide section 3 and the spot size conversion section 5 and is connected to the passive waveguide section 3 and the spot size conversion section 5. The end face 4a faces the passive waveguide section 3 and is the interface between the passive waveguide section 3 and the optical modulation section 4. The end face 4b faces the spot size conversion section 5 and is the interface between the optical modulation section 4 and the spot size conversion section 5. The modulation section length L (refer to Figure 2 ) is the distance between the end face 4a and the end face 4b in the second active layer 42.

[0037] The optical modulation section 4 includes a semiconductor substrate 10, a lower cladding 11, a lower cladding 41, a second active layer 42, an upper cladding 43, a semiconductor region 44, a semiconductor region 45, a current blocking layer 15, an upper cladding 16, a contact layer 47, an insulating protective film 22, a first electrode 25, a third electrode 27, a pad 28, and a bridge wiring 29.

[0038] The lower cladding 41 is disposed on the lower cladding 11. The lower cladding 41 may be formed of the same semiconductor material as the lower cladding 11. The lower cladding 41 is, for example, an n-type semiconductor layer such as an n-InP layer.

[0039] The second active layer 42 is disposed on the lower cladding layer 41. The second active layer 42 is, for example, a multi-quantum well (MQW) layer. The second active layer 42 is, for example, an intrinsic semiconductor layer (i-layer) that is not intentionally doped with an n-type dopant and a p-type dopant. The second active layer 42 is disposed between the lower cladding layer 41 and the upper cladding layer 43, and has a refractive index larger than that of the lower cladding layer 41 and the upper cladding layer 43.

[0040] The upper cladding layer 43 is disposed on the second active layer 42. The upper cladding layer 43 may be formed of the same semiconductor material as the upper cladding layer 16. The upper cladding layer 43 is a p-type semiconductor layer such as p-InP.

[0041] The upper cladding layer 43 includes a first portion 43a, a second portion 43b, and a third portion 43c. The second portion 43b is closer to the end face 8 than the first portion 43a. The third portion 43c is closer to the end face 9 than the first portion 43a. The lower surface of the first portion 43a is in contact with the second active layer 42. The lower surface of the second portion 43b recedes from the first portion 43a, and the second portion 43b is away from the second active layer 42. The lower surface of the third portion 43c recedes from the first portion 43a, and the third portion 43c is away from the second active layer 42. The second portion 43b is in contact with the semiconductor region 44. The third portion 43c is in contact with the semiconductor region 45. The thickness of the second portion 43b is smaller than the thickness of the first portion 43a. The sum of the thickness of the second portion 43b and the thickness of the semiconductor region 44 is equal to the thickness of the first portion 43a. The thickness of the third portion 43c is smaller than the thickness of the first portion 43a. The sum of the thickness of the third portion 43c and the thickness of the semiconductor region 45 is equal to the thickness of the first portion 43a.

[0042] Both side surfaces of the stack of the upper cladding layer 16, the upper cladding layer 43, the second active layer 42, the lower cladding layer 41, and the lower cladding layer 11 define the surfaces of the grooves 20 and 21, and are covered with the insulating protective film 22. The optical modulation section 4 has a high mesa structure.

[0043] The contact layer 47 is disposed on the upper cladding layer 16 exposed from the opening of the insulating protective film 22. The contact layer 47 has the same conductivity type as the upper cladding layers 16 and 43, and is doped with more dopants than the upper cladding layers 16 and 43. The contact layer 47 is, for example, a p + -InGaAs layer.

[0044] The third electrode 27 is disposed on the contact layer 47. The third electrode 27 is, for example, a gold (Au) electrode. A conductive wire (not shown) is bonded to the pad 28. The bridge wiring 29 spans across the groove 21 and connects the third electrode 27 and the pad 28. A voltage from an external power supply (not shown) is applied to the third electrode 27 via the conductive wire, the pad 28, and the bridge wiring 29.

[0045] The semiconductor region 44 has the same conductivity type as the upper cladding layers 16 and 43. The semiconductor region 44 is disposed in a part between the second active layer 42 and the upper cladding layer 43. The semiconductor region 44 is in contact with the second active layer 42, the upper cladding layer 43, and the passive waveguide portion 3 (specifically, the passive waveguide 30). The semiconductor region 44 and the upper cladding layer 43 are in contact with the upper surface of the second active layer 42. The lower surface of the semiconductor region 44 and the lower surface of the first portion 43a of the upper cladding layer 43 are flush with each other. The semiconductor region 44 is disposed at the end face 4a and forms a part of the end face 4a. The semiconductor region 44 is disposed between the end face 4a and the first imaginary plane 48 that is separated from the end face 4a by one-tenth of the length L of the modulation section.

[0046] The first impact ionization coefficient of the semiconductor region 44 is smaller than the impact ionization coefficient of the upper cladding layer 43. For example, when the upper cladding layer 43 is formed of p-InP, the semiconductor region 44 is formed of InGaAsP. The semiconductor region 44 may also be lattice-matched with the upper cladding layers 16 and 43. In this specification, the semiconductor region being lattice-matched with the cladding layer means that the difference between the lattice constant of the semiconductor material constituting the semiconductor region and the lattice constant of the semiconductor material constituting the cladding layer is within ±0.1% of the lattice constant of the semiconductor material constituting the cladding layer. The semiconductor region 44 is formed of In 0.82 Ga 0.18 As 0.4 P 0.6 formed.

[0047] The semiconductor region 45 has the same conductivity type as the upper cladding layers 16 and 43. The semiconductor region 45 is disposed in a part between the second active layer 42 and the upper cladding layer 43 and is away from the semiconductor region 44. The semiconductor region 45 is in contact with the second active layer 42, the upper cladding layer 43, and the spot size conversion section 5 (specifically, the spot size conversion waveguide 51). The semiconductor region 45 and the upper cladding layer 43 are in contact with the upper surface of the second active layer 42. The lower surface of the semiconductor region 45 and the lower surface of the first portion 43a of the upper cladding layer 43 are flush with each other. The semiconductor region 45 is disposed at the end face 4b and forms a part of the end face 4b. The semiconductor region 45 is disposed between the end face 4b and the second imaginary plane 49 that is separated from the end face 4b by one-tenth of the length L of the modulation section.

[0048] The second impact ionization coefficient of the semiconductor region 45 is smaller than the impact ionization coefficient of the upper cladding layer 43. The semiconductor region 45 may also be formed of the same material as the semiconductor region 44. For example, when the upper cladding layer 43 is formed of p-InP, the semiconductor region 45 is formed of InGaAsP. The semiconductor region 45 may also be lattice-matched with the upper cladding layers 16 and 43. The semiconductor region 45 is formed of In 0.82 Ga 0.18 As0.4 P 0.6 formed

[0049] The upper surface of the second active layer 42 is in contact with the upper cladding 43, the semiconductor region 44, and the semiconductor region 45, and the lower surface of the second active layer 42 is in contact with the lower cladding 41. The upper cladding 43, the semiconductor region 44, the semiconductor region 45, the second active layer 42, and the lower cladding 41 form a pin structure. When a reverse bias voltage is not applied to the pin structure of the optical modulation unit 4, the second active layer 42 transmits the laser light emitted from the laser unit 2. When a voltage lower than the first electrode 25 is applied to the third electrode 27 so that a reverse bias voltage is applied to the pin structure of the optical modulation unit 4, the absorption edge wavelength of the second active layer 42 shifts to the longer wavelength side, and the second active layer 42 absorbs the laser light emitted from the laser unit 2. In this way, the optical modulation unit 4 modulates the intensity of the laser light.

[0050] Refer to Figure 1 , Figure 2 and Figure 7 , in order to increase the coupling efficiency of the laser light to an optical element (not shown) such as an optical fiber, the spot size conversion unit 5 increases the diameter of the laser light emitted from the laser unit 2. The spot size conversion unit 5 includes a semiconductor substrate 10, a lower cladding 11, a spot size conversion waveguide 51, a current blocking layer 15, an upper cladding 16, an insulating protective film 22, and a window region 52. The spot size conversion unit 5 includes an end face 9. The spot size conversion unit 5 may also include the first electrode 25.

[0051] The spot size conversion waveguide 51 is disposed on the lower cladding 11. The upper cladding 16 is disposed on the spot size conversion waveguide 51. The spot size conversion waveguide 51 is disposed between the lower cladding 11 and the upper cladding 16 and has a refractive index larger than that of the lower cladding 11 and the upper cladding 16. The spot size conversion waveguide 51 is formed of a semiconductor material (e.g., InGaAsP) having a bandgap larger than the energy of the laser light emitted from the laser unit 2. The spot size conversion waveguide 51 may also be formed of the same material as the passive waveguide 30. The spot size conversion waveguide 51 is, for example, an intrinsic semiconductor layer. Both side surfaces of the laminate of the lower cladding 11 and the spot size conversion waveguide 51 are buried by the current blocking layer 15.

[0052] The width of the spot size conversion waveguide 51 gradually narrows as it goes from the optical modulation unit 4 toward the end face 9. Therefore, as it goes from the optical modulation unit 4 toward the end face 9, the light confinement effect of the spot size conversion waveguide 51 on the laser light becomes weaker, and the diameter of the laser light gradually expands. The spot size conversion waveguide 51 is away from the end face 9.

[0053] The window region 52 is disposed on the lower cladding 11. The upper cladding 16 is disposed on the window region 52. The window region 52 is disposed between the lower cladding 11 and the upper cladding 16. The window region 52 is disposed between the spot size conversion waveguide 51 and the end face 9. The window region 52 includes the end face 9. The window region 52 may also have the same structure as the current blocking layer 15. For example, the window region 52 includes a semi-insulating semiconductor layer 15a and an n-type semiconductor layer 15b. In the window region 52, the diameter of the laser is further enlarged.

[0054] Refer to Figure 1 and Figure 2 , a high reflection film 61 is formed on the end face 8. The high reflection film 61 reflects the laser generated in the laser section 2 with a high reflectance (for example, a reflectance of 95% or more). The high reflection film 61 is, for example, a multilayer film formed of a SiO2 film, a Si film, an Al2O3 film, or the like.

[0055] Refer to Figure 1 and Figure 2 , an antireflection film 62 is formed on the end face 9. The antireflection film 62 prevents the laser generated in the laser section 2 from reflecting on the end face 9 and allows the laser to be emitted from the end face 9 with a high extraction efficiency. The antireflection film 62 is, for example, a multilayer film formed of a SiO2 film, a Si film, an Al2O3 film, or the like.

[0056] An example of a method for manufacturing the optoelectronic integrated device 1 of the present embodiment will be described.

[0057] The lower cladding 11 is formed on the upper surface of the semiconductor substrate 10. For example, the lower cladding 11 is deposited on the upper surface of the semiconductor substrate 10 using a method such as metalorganic chemical vapor deposition (MOCVD). The diffraction grating 12 is formed only in the region where the laser section 2 should be formed in the lower cladding 11.

[0058] The first active layer 13 and the upper cladding 14 are formed on the lower cladding 11. For example, the first active layer 13 and the upper cladding 14 are formed on the entire upper surface of the lower cladding 11 using a method such as metalorganic chemical vapor deposition (MOCVD). The first active layer 13 and the upper cladding 14 are patterned by photolithography and etching. The first active layer 13 and the upper cladding 14 are formed in the region where the laser section 2 should be formed.

[0059] The region where the laser section 2 should be formed is covered with a mask. Thereafter, using a method such as metalorganic chemical vapor deposition (MOCVD), the lower cladding 41, the second active layer 42, and the upper cladding 43 are formed on the entire upper surface of the lower cladding 11 exposed from the mask. The lower cladding 41, the second active layer 42, and the upper cladding 43 are patterned by photolithography and etching. The lower cladding 41, the second active layer 42, and the upper cladding 43 are formed in the region where the optical modulation section 4 should be formed.

[0060] Except for the region where the laser section 2 should be formed, the region where the optical modulation section 4 should be formed is covered with a mask. Then, using a method such as metalorganic chemical vapor deposition (MOCVD), a passive waveguide 30 and a spot size conversion waveguide 51 are formed on the entire upper surface of the lower cladding 11 exposed from the mask. The passive waveguide 30 and the spot size conversion waveguide 51 are patterned by photolithography and etching. The passive waveguide 30 is formed in the region where the passive waveguide section 3 should be formed, and the spot size conversion waveguide 51 is formed in the region where the spot size conversion section 5 should be formed.

[0061] Using a method such as metalorganic chemical vapor deposition (MOCVD), a current blocking layer 15 and a window region 52 are formed on the upper surface of the semiconductor substrate 10. The side surfaces of the lower cladding 11, the first active layer 13, the upper cladding 14, the passive waveguide 30, the lower cladding 41, the second active layer 42, the upper cladding 43, and the spot size conversion waveguide 51 are buried by the current blocking layer 15.

[0062] Using a method such as metalorganic chemical vapor deposition (MOCVD), an upper cladding 16 is formed on the upper cladding 14, the passive waveguide 30, the upper cladding 43, the spot size conversion waveguide 51, and the current blocking layer 15. Using a method such as metalorganic chemical vapor deposition (MOCVD), a contact layer 17, 47 is formed on the upper cladding 16.

[0063] The current blocking layer 15 is etched to form grooves 20, 21. The side surfaces of the lower cladding 41, the second active layer 42, and the upper cladding 43 are exposed from the current blocking layer 15, so that the optical modulation section 4 has a high mesa structure. The side surfaces of the lower cladding 11, the first active layer 13, and the upper cladding 14 remain covered by the current blocking layer 15, and the laser section 2 has a buried structure. The side surfaces of the passive waveguide 30 and the spot size conversion waveguide 51 remain covered by the current blocking layer 15.

[0064] Using a method such as chemical vapor deposition (CVD), an insulating protective film 22 is formed on the surfaces of the grooves 20, 21 and the upper cladding 16. An opening is provided in the insulating protective film 22 by etching. Using evaporation, photolithography, etching, etc., a first electrode 25, a second electrode 26, a third electrode 27, a pad 28, and a bridge wiring 29 are formed. The first electrode 25 is formed on the lower surface of the semiconductor substrate 10. The second electrode 26 is formed on the contact layer 17. The third electrode 27 is formed on the contact layer 47. The pad 28 is formed on the insulating protective film 22. The bridge wiring 29 spans the groove 21 and connects the third electrode 27 and the pad 28.

[0065] The end faces 8 and 9 are formed by splitting. Using a method such as chemical vapor deposition (CVD), a high-reflection film 61 is formed on the end face 8. Using a method such as chemical vapor deposition (CVD), an antireflection film 62 is formed on the end face 9. Thus, the optoelectronic integrated device 1 is obtained.

[0066] Describe the operation of the optoelectronic integrated device 1 of this embodiment.

[0067] A voltage higher than that of the first electrode 25 is applied to the second electrode 26, and a forward bias voltage is applied to the pin structure of the laser section 2. A current is injected into the first active layer 13, and the laser section 2 emits laser light. The end face 8 and the end face of the laser section 2 facing the passive waveguide section 3 function as an optical resonator for the laser. Since the high-reflection film 61 is formed on the end face 8, the intensity of the laser can be increased. For example, the diffraction grating 12 functions as a distributed Bragg reflector (DBR) for the laser. The laser section 2 is a distributed feedback laser (DFB laser).

[0068] The passive waveguide 30 guides the laser light from the laser section 2 to the second active layer 42 of the optical modulation section 4.

[0069] When a reverse bias voltage is not applied to the pin structure of the optical modulation section 4, the second active layer 42 transmits the laser light emitted from the laser section 2. When a voltage lower than that of the first electrode 25 is applied to the third electrode 27 and a reverse bias voltage is applied to the pin structure of the optical modulation section 4, the absorption edge wavelength of the second active layer 42 shifts to the long wavelength side, and the second active layer 42 absorbs the laser light emitted from the laser section 2. Thus, the optical modulation section 4 modulates the intensity of the laser light.

[0070] The laser light modulated in the optical modulation section 4 is incident on the spot size conversion waveguide 51 of the spot size conversion section 5. Regarding the laser light, as it travels in the spot size conversion waveguide 51 and the window region 52, the diameter of the laser light gradually increases. Furthermore, an antireflection film 62 is provided on the end face 9. Therefore, the laser light can be coupled to an optical element (not shown) such as an optical fiber disposed opposite to the end face 9 with a high coupling efficiency.

[0071] When a reverse bias voltage is applied to the pin structure of the optical modulator 4, a depletion layer is formed in the pin structure of the optical modulator 4, so normally, no current flows in the pin structure of the optical modulator 4. However, when a high voltage is applied to the pin structure of the optical modulator 4 due to static electricity, a high electric field is formed in the pin structure of the optical modulator 4. During optical modulation, laser light is absorbed by the second active layer 42, thereby generating carriers (electrons and holes) in the optical modulator 4. The carriers are accelerated by the high electric field and collide with atoms constituting the semiconductor layer forming the pin structure of the optical modulator 4. Due to the collision, new carriers are generated. Such impact ionization is generated in a chain reaction, and a large current caused by avalanche breakdown flows to the pin structure of the optical modulator 4. Electrostatic discharge (ESD) occurs in the optical modulator 4. The upper cladding layer 43 is a p-type semiconductor layer, and the impact ion coefficient of holes in the upper cladding layer 43 is large. Therefore, a large current is likely to occur in the upper cladding layer 43.

[0072] In the present embodiment, a semiconductor region 44 and a semiconductor region 45 are arranged in a portion between the second active layer 42 and the upper cladding layer 43. The first collision ionization coefficient of the semiconductor region 44 and the second collision ionization coefficient of the semiconductor region 45 are respectively smaller than the collision ionization coefficient of the upper cladding layer 43. Therefore, in the semiconductor region 44 and the semiconductor region 45, the occurrence of collision ionization in a chain during light modulation is suppressed. Even if a high voltage is applied to the pin structure of the light modulation unit 4 due to static electricity, a large current can be prevented from flowing in the pin structure of the light modulation unit 4. The optical semiconductor integrated device 1 has improved tolerance to electrostatic damage (ESD).

[0073] In addition, the resistance to electrostatic discharge (ESD) can be improved without increasing the thickness of the i-layer (second active layer 42) of the pin structure of the light modulator 4. Therefore, the extinction ratio of the light modulator 4 does not decrease.

[0074] Reference Figure 8 as well as Figure 9 , an optical semiconductor integrated device 1 according to a modified example of the present embodiment will be described.

[0075] You can also Figure 8 The optical semiconductor integrated device 1 of the first modified example of the present embodiment shown in FIG. 1 is different from the optical semiconductor integrated device 1 of the present embodiment (see FIG. 1 ). Figure 1 as well as Figure 2 ) The passive waveguide section 3 is omitted. In the optical semiconductor integrated device 1, the light modulator 4 is arranged between the laser section 2 and the spot size conversion section 5, and is connected to the laser section 2 and the spot size conversion section 5. The end face 4a faces the laser section 2 and is the interface between the laser section 2 and the light modulator 4. The semiconductor region 44 is in contact with the second active layer 42, the upper cladding layer 43, and the laser section 2 (specifically, the first active layer 13).

[0076] It is also possible to, as Figure 9 shown in the second modification of the optical semiconductor integrated device 1 of the present embodiment, omit the passive waveguide section 3 and the spot size conversion section 5 from the optical semiconductor integrated device 1 of the present embodiment (refer to Figure 1 and Figure 2 ). In the optical semiconductor integrated device 1, the optical modulation section 4 is connected to the laser section 2. The end face 4a faces the laser section 2 and is the interface between the laser section 2 and the optical modulation section 4. The end face 4b is the end face 9 of the optical semiconductor integrated device 1. The semiconductor region 44 is in contact with the second active layer 42, the upper cladding layer 43, and the laser section 2 (specifically, the first active layer 13). The semiconductor region 45 is in contact with the second active layer 42 and the upper cladding layer 43. The semiconductor region 45 is disposed on the end face 9 and forms a part of the end face 4b.

[0077] In the third modification of the present embodiment, it is also possible to omit either the semiconductor region 44 or the semiconductor region 45.

[0078] Describe the effects of the optical semiconductor integrated device 1 of the present embodiment.

[0079] The optical semiconductor integrated device 1 of the present embodiment includes an optical modulation section 4 and a semiconductor waveguide element section (such as the passive waveguide section 3) connected to the optical modulation section 4. The optical modulation section 4 includes an active layer (the second active layer 42), an upper cladding layer 43, and a first semiconductor region (such as the semiconductor region 44) having the same conductivity type as the upper cladding layer 43. The first semiconductor region is disposed in a part between the active layer and the upper cladding layer 43. The first impact ionization coefficient of the first semiconductor region is smaller than the impact ionization coefficient of the upper cladding layer 43.

[0080] Therefore, in the first semiconductor region (such as the semiconductor region 44), the occurrence of impact ionization in a chain during optical modulation is suppressed. Even if a momentary high voltage is applied to the optical modulation section 4 due to static electricity, without increasing the thickness of the active layer (the second active layer 42), it is possible to prevent a large current due to avalanche breakdown from flowing into the optical modulation section 4. According to the optical semiconductor integrated device 1, the tolerance to electrostatic discharge (ESD) can be improved without reducing the extinction ratio of the optical modulation section 4.

[0081] In the optical semiconductor integrated device 1 of the present embodiment, the optical modulation section 4 includes a first end face (such as the end face 4a) facing the semiconductor waveguide element section (such as the passive waveguide section 3) and a second end face (such as the end face 4b) on the side opposite to the first end face. The first semiconductor region (such as the semiconductor region 44) is disposed on the first end face.

[0082] A large current that causes electrostatic discharge (ESD) easily flows to the end face of the optical modulation unit 4. The first semiconductor region (e.g., semiconductor region 44) is disposed on the first end face (e.g., end face 4a). Therefore, a large current that causes ESD can be effectively suppressed. According to the optical semiconductor integrated device 1, the tolerance against ESD can be improved without reducing the extinction ratio of the optical modulation unit 4.

[0083] In the optical semiconductor integrated device 1 of the present embodiment, the first semiconductor region (e.g., semiconductor region 44) is disposed between the first end face (e.g., end face 4a) and a first imaginary plane 48 that is one-tenth of the modulation unit length L away from the first end face. The modulation unit length L is the distance between the first end face and the second end face (e.g., end face 4b) in the active layer.

[0084] Therefore, a decrease in the reverse bias voltage applied to the second active layer 42 caused by the first semiconductor region (e.g., semiconductor region 44) can be suppressed. According to the optical semiconductor integrated device 1, the tolerance against ESD can be improved without reducing the extinction ratio of the optical modulation unit 4.

[0085] In the optical semiconductor integrated device 1 of the present embodiment, the upper cladding layer 43 is formed of p-type InP. The first semiconductor region (e.g., semiconductor region 44) is formed of InGaAsP whose lattice matches that of the upper cladding layer 43.

[0086] A change in the absorption end wavelength of the second active layer 42 due to a lattice mismatch between the first semiconductor region (e.g., semiconductor region 44) and the upper cladding layer 43 can be prevented. According to the optical semiconductor integrated device 1, the tolerance against ESD can be improved without reducing the extinction ratio of the optical modulation unit 4.

[0087] In the optical semiconductor integrated device 1 of the present embodiment, the optical modulation unit 4 includes a second semiconductor region (e.g., semiconductor region 45) having the same conductivity type as the upper cladding layer 43. The second semiconductor region is disposed in a part between the active layer (second active layer 42) and the upper cladding layer 43 and is away from the first semiconductor region (e.g., semiconductor region 44). The second impact ionization coefficient of the second semiconductor region is smaller than the impact ionization coefficient of the upper cladding layer 43.

[0088] Therefore, in the second semiconductor region (e.g., semiconductor region 45), the occurrence of impact ionization in a chain during optical modulation is suppressed. Even if a momentary high voltage is applied to the optical modulation unit 4 due to static electricity, a large current caused by avalanche breakdown can be prevented from flowing to the optical modulation unit 4 without increasing the thickness of the active layer (second active layer 42). According to the optical semiconductor integrated device 1, the tolerance against electrostatic discharge (ESD) can be improved without reducing the extinction ratio of the optical modulation unit 4.

[0089] In the optoelectronic integrated device 1 of the present embodiment, the second semiconductor region (e.g., semiconductor region 45) is disposed on the second end face (e.g., end face 4b).

[0090] A large current causing electrostatic breakdown (ESD) easily flows to the end face of the optical modulation unit 4. The second semiconductor region (e.g., semiconductor region 45) is disposed on the second end face (e.g., end face 4b). Therefore, the large current causing ESD can be effectively suppressed. According to the optoelectronic integrated device 1, the tolerance to ESD can be improved without reducing the extinction ratio of the optical modulation unit 4.

[0091] In the optoelectronic integrated device 1 of the present embodiment, the first semiconductor region (e.g., semiconductor region 44) is disposed between the first end face (e.g., end face 4a) and the first imaginary plane 48 which is one-tenth of the modulation unit length L away from the first end face. The second semiconductor region (e.g., semiconductor region 45) is disposed between the second end face (e.g., end face 4b) and the second imaginary plane 49 which is one-tenth of the modulation unit length L away from the second end face. The modulation unit length L is the distance between the first end face and the second end face in the active layer.

[0092] Therefore, a decrease in the reverse bias voltage applied to the second active layer 42 caused by the first semiconductor region (e.g., semiconductor region 44) and the second semiconductor region (e.g., semiconductor region 45) can be suppressed. According to the optoelectronic integrated device 1, the tolerance to ESD can be improved without reducing the extinction ratio of the optical modulation unit 4.

[0093] In the optoelectronic integrated device 1 of the present embodiment, the upper cladding layer 43 is formed of p-type InP. The first semiconductor region (e.g., semiconductor region 44) and the second semiconductor region (e.g., semiconductor region 45) are each formed of InGaAsP having a lattice matching that of the upper cladding layer 43.

[0094] A change in the absorption edge wavelength of the second active layer 42 due to lattice mismatch between the first semiconductor region (e.g., semiconductor region 44) and the upper cladding layer 43 and lattice mismatch between the second semiconductor region (e.g., semiconductor region 45) and the upper cladding layer 43 can be prevented. According to the optoelectronic integrated device 1, the tolerance to ESD can be improved without reducing the extinction ratio of the optical modulation unit 4.

[0095] The optoelectronic integrated device 1 of the present embodiment further includes a laser unit 2. The semiconductor waveguide element unit is a passive waveguide unit 3 connected to the laser unit 2 and the optical modulation unit 4.

[0096] According to the optoelectronic integrated device 1, the tolerance to ESD can be improved without reducing the extinction ratio of the optical modulation unit 4.

[0097] In the optoelectronic integrated device 1 of the present embodiment, the semiconductor waveguide element section is the laser section 2.

[0098] According to the optoelectronic integrated device 1, the tolerance against ESD can be improved without reducing the extinction ratio of the optical modulation section 4.

[0099] The optoelectronic integrated device 1 of the present embodiment further includes a spot size conversion section 5. The second end face (for example, end face 4b) faces the spot size conversion section 5.

[0100] According to the optoelectronic integrated device 1, the tolerance against ESD can be improved without reducing the extinction ratio of the optical modulation section 4.

[0101] In the optoelectronic integrated device 1 of the present embodiment, the second end face (for example, end face 4b) is the emission end face (end face 9) of the optoelectronic integrated device 1.

[0102] According to the optoelectronic integrated device 1, the tolerance against ESD can be improved without reducing the extinction ratio of the optical modulation section 4.

[0103] It should be considered that the embodiments disclosed herein are illustrative only and not restrictive in all respects. The scope of the present disclosure is represented by the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0104] (Reference Signs)

[0105] 1: Optoelectronic integrated device; 2: Laser section; 3: Passive waveguide section; 4: Optical modulation section; 4a, 4b: End faces; 5: Spot size conversion section; 8, 9: End faces; 10: Semiconductor substrate; 11: Lower cladding; 12: Diffraction grating; 13: First active layer; 14: Upper cladding; 15: Current blocking layer; 15a: Semi-insulating semiconductor layer; 15b: n-type semiconductor layer; 16: Upper cladding; 17: Contact layer; 20, 21: Grooves; 22: Insulating protective film; 25: First electrode; 26: Second electrode; 27: Third electrode; 28: Pad; 29: Bridge wiring; 30: Passive waveguide; 41: Lower cladding; 42: Second active layer; 43: Upper cladding; 43a: First part; 43b: Second part; 43c: Third part; 44: First semiconductor region; 45: Second semiconductor region; 47: Contact layer; 48: First imaginary plane; 49: Second imaginary plane; 51: Spot size conversion waveguide; 52: Window region; 61: High reflection film; 62: Anti-reflection film.

Claims

1. A photonic semiconductor integrated device, comprising: an optical modulation section; and a semiconductor waveguide element section connected to the optical modulation section, wherein the optical modulation section includes an active layer, an upper cladding layer, and a first semiconductor region having the same conductivity type as the upper cladding layer, the first semiconductor region is disposed in a part between the active layer and the upper cladding layer, and a first impact ionization coefficient of the first semiconductor region is smaller than an impact ionization coefficient of the upper cladding layer.

2. The photonic semiconductor integrated device according to claim 1, wherein the optical modulation section includes a first end face facing the semiconductor waveguide element section and a second end face on a side opposite to the first end face, and the first semiconductor region is disposed at the first end face.

3. The photonic semiconductor integrated device according to claim 2, wherein the first semiconductor region is disposed between the first end face and a first imaginary plane that is one-tenth of a modulation section length away from the first end face, and the modulation section length is a distance between the first end face and the second end face in the active layer.

4. The photonic semiconductor integrated device according to any one of claims 1 to 3, wherein the upper cladding layer is formed of p-type InP, and the first semiconductor region is formed of InGaAsP having a lattice matched with the upper cladding layer.

5. The photonic semiconductor integrated device according to claim 2, wherein the optical modulation section includes a second semiconductor region having the same conductivity type as the upper cladding layer, the second semiconductor region is disposed in a part between the active layer and the upper cladding layer and is away from the first semiconductor region, and a second impact ionization coefficient of the second semiconductor region is smaller than the impact ionization coefficient of the upper cladding layer.

6. The photonic semiconductor integrated device according to claim 5, wherein the second semiconductor region is disposed at the second end face.

7. The photonic semiconductor integrated device according to claim 6, wherein the first semiconductor region is disposed between the first end face and a first imaginary plane that is one-tenth of a modulation section length away from the first end face, the second semiconductor region is disposed between the second end face and a second imaginary plane that is one-tenth of the modulation section length away from the second end face, and the modulation section length is a distance between the first end face and the second end face in the active layer.

8. The photonic semiconductor integrated device according to any one of claims 5 to 7, wherein the upper cladding layer is formed of p-type InP, and the first semiconductor region and the second semiconductor region are each formed of InGaAsP having a lattice matched with the upper cladding layer.

9. The photonic semiconductor integrated device according to any one of claims 1 to 8, wherein a laser section is further provided, and the semiconductor waveguide element section is a passive waveguide section connected to the laser section and the optical modulation section.

10. The photonic semiconductor integrated device according to any one of claims 1 to 8, wherein the semiconductor waveguide element section is a laser section.

11. The opto-semiconductor integrated device according to any one of claims 5 to 8, wherein it further includes a spot size conversion section, and the second end face faces the spot size conversion section.

12. The opto-semiconductor integrated device according to any one of claims 5 to 8, wherein the second end face is the emission end face of the opto-semiconductor integrated device.

Images