Ultrasonic three-dimensional imaging method and system based on FPGA

Abstract

The invention provides an ultrasonic three-dimensional imaging method and system based on an FPGA, and relates to the technical field of ultrasonic imaging, and the method comprises the steps: transmitting a chirp signal, receiving an echo signal reflected by a target object, and carrying out the preprocessing; carrying out adaptive filtering, constant false alarm rate detection, adaptive beam forming and three-dimensional positioning algorithm processing on the preprocessed signal to generate target position data; and performing three-dimensional point cloud image reconstruction on the target position data by using a density-based spatial clustering algorithm and a deep learning model, and outputting a target three-dimensional image. Through the innovation of a signal processing algorithm and the collaborative design of the system, the technical bottlenecks of a traditional ultrasonic sensor in detection distance, anti-interference, real-time performance and positioning precision are solved, and the three-dimensional sensing capability with high reliability and strong environmental adaptability is provided for intelligent driving.

Description

Technical Field

[0001] This application relates to the field of ultrasonic imaging technology, and particularly to an ultrasonic three-dimensional imaging method and system based on FPGA. Background Art

[0002] With the rapid development of intelligent driving technology, the performance of the environmental perception system has become the key bottleneck restricting the safety and reliability of driverless vehicles. Existing environmental perception technologies mainly rely on devices such as vision sensors, lidar, and millimeter-wave radars, but face multiple challenges in practical applications: optical sensors are significantly restricted by lighting conditions, lidar has problems of insufficient vertical resolution and high cost, and millimeter-wave radars are vulnerable to electromagnetic interference and have limited resolution. In contrast, ultrasonic sensors have important application values in the field of intelligent driving due to their all-weather working ability, low cost, and short-range high-precision ranging advantages.

[0003] However, despite the above advantages of ultrasonic sensors, their technical limitations in complex scenarios still significantly restrict the application efficiency: their inherent signal processing mechanism leads to limited detection range, and the rapid attenuation of energy with distance makes it difficult to achieve three-dimensional imaging in the medium and long distances; the multiple target reflections and noise superposition in complex acoustic environments further exacerbate signal interference, and traditional fixed beamforming technology is difficult to effectively distinguish real targets from reverberation components, resulting in beam distortion and cumulative positioning errors; the limitations of the hardware architecture lead to low processing efficiency of high-density point cloud data, and the real-time performance is difficult to meet the millisecond-level response requirements of autonomous driving; the two-dimensional imaging mode further causes serious false alarm problems, and the signal superposition effect in occluded scenarios leads to a significant increase in the target misjudgment rate. These technical defects are interrelated and jointly restrict the environmental perception efficiency of ultrasonic sensors in complex scenarios, and it is difficult to meet the urgent needs of intelligent driving for high-precision and strong-robustness three-dimensional perception systems. Summary of the Invention

[0004] The purpose of this application is to provide an ultrasonic three-dimensional imaging method and system based on FPGA to solve the problem that the technical limitations of existing environmental perception technologies in complex scenarios still significantly restrict the application efficiency and are difficult to meet the urgent needs of intelligent driving for high-precision and strong-robustness three-dimensional perception systems mentioned in the above background art.

[0005] To achieve the above purpose, this application provides the following technical solution: An ultrasonic three-dimensional imaging method based on FPGA, the steps include: externally transmitting a chirp signal, receiving the echo signal reflected by the target object, and performing preprocessing; performing adaptive filtering, constant false alarm rate detection, adaptive beamforming, and three-dimensional positioning algorithm processing on the preprocessed signal to generate target position data; using a density-based spatial clustering algorithm and a deep learning model to perform three-dimensional point cloud image reconstruction on the target position data, and outputting a target three-dimensional image.

[0006] Optionally, the step of generating the chirp signal includes: based on preset start frequency, stop frequency, frequency modulation rate, and signal duration parameters, generating waveform data with linearly varying frequency over time through direct digital frequency synthesis method, outputting a linear frequency modulated continuous wave signal through digital-to-analog conversion, and amplifying the signal power through a power amplifier to output a chirp signal that meets the detection distance.

[0007] Optionally, the preprocessing step specifically includes: preliminarily amplifying the echo signal using a low-noise amplifier; dynamically adjusting the signal gain through a time gain compensation mechanism; filtering out high-frequency aliasing components and suppressing DC bias and flicker noise by cascading an anti-aliasing filter and a baseline correction filter; stabilizing the signal amplitude using a voltage-controlled amplifier combined with automatic gain control; using a field programmable gate array for data deserialization and buffering, and compensating for timing deviation through phase-locked loop synchronous sampling and an elastic buffer.

[0008] Optionally, the step of adaptive filtering specifically includes: pre-storing the number of taps of a finite impulse response filter, initial filter coefficients, and initial step size parameters in the on-chip random access memory of a field programmable gate array; configuring the sampling rate and channel parameters of an analog-to-digital converter to ensure synchronous acquisition of multi-channel signals; performing shift register delay processing on the multi-channel microphone input signals to generate an input signal vector containing the current and the previous N-1 time signals; calculating the array element delay time in the direction of the desired signal based on the delay and sum principle to generate initial weighting coefficients; obtaining an intermediate output of beamforming through weighted sum operation; calculating the error between the desired signal and the output, and dynamically adjusting the step size parameter according to the power value of the input signal vector; performing weighted sum based on the error signal and the current weighting coefficients to dynamically adjust the weighting coefficients; storing the updated weighting coefficients back into the on-chip random access memory and repeating the iteration until the mean square error value is less than a preset threshold or the maximum number of iterations is reached; storing intermediate data through a block random access memory or an external synchronous dynamic random access memory, and implementing parallel computing using a pipeline architecture.

[0009] Optionally, the weighting coefficient update process is implemented using a hardware multiplier and an accumulator, and the coordinated operation of the signal delay, weighted sum, error calculation, and coefficient update modules is coordinated by a state machine; wherein, the state machine includes five state nodes: signal acquisition state, delay processing state, weighted operation state, error feedback state, and coefficient update state.

[0010] Optionally, the constant false alarm rate detection step specifically includes: initializing the constant false alarm rate algorithm parameters, including setting the number of reference cells, the number of guard cells, the false alarm rate control factor, and the input data dimension and format; receiving and storing the amplitude or power value of the ultrasonic echo signal; for each cell to be detected, selecting the surrounding reference cells to form a reference window, and calculating the statistical characteristics of the background noise by dividing the window into multiple sub - windows; generating a variability index and a mean ratio based on the statistical characteristics of the sub - windows to judge the uniformity of the signal environment and the presence of clutter edges; dynamically selecting a constant false alarm rate algorithm according to the environment judgment result: selecting the cell - average constant false alarm rate algorithm and adjusting the weight in a uniform environment, selecting an improved ordered - statistic constant false alarm rate algorithm to correct the maximum value in a clutter - edge environment, and selecting an ordered - statistic constant false alarm rate algorithm in a multi - target environment; generating an adaptive detection threshold based on the selected algorithm, and performing a cyclic scan on all cells to be detected to complete target detection; outputting the detection result including the target position information.

[0011] Optionally, the step of, for each cell to be detected, selecting the surrounding reference cells to form a reference window and calculating the statistical characteristics of the background noise by dividing the window into multiple sub - windows specifically includes: equally dividing the reference window into several sub - windows, respectively calculating the mean and variance of each sub - window, characterizing the signal distribution uniformity by the ratio of the sum of the squared sub - window means to the square of the sum of the means, and locating the clutter - edge position in combination with the mean ratio relationship of the sub - windows.

[0012] Optionally, the steps of adaptive beamforming specifically include: deploying multiple ultrasonic receiving base stations, which are optimally arranged according to the Fibonacci spherical distribution; through the direct memory access transmission method, transmitting the pre - stored receiver coordinates, sound speed, iteration parameters, and the initial value of the weighting matrix from the ARM processor to the field - programmable gate array; real - time collecting the time - difference - of - arrival data of each base station, and selecting the time - difference - of - arrival data of the five base stations closest to the object to be measured for weighted average processing; constructing a non - linear equation set based on the time - difference - of - arrival data and linearizing it, and using the least - squares method to obtain a preliminary estimate of the coordinates of the object to be measured; introducing the weighted least - squares method in the local optimization stage, and dynamically adjusting the weighting matrix to avoid falling into a local optimal solution; using the internal digital signal processor resources of the field - programmable gate array to implement matrix operations, and completing the iteration convergence judgment through pipeline design and state - machine control; when the sum of the squared residuals is less than a preset threshold or the maximum number of iterations is reached, outputting the three - dimensional coordinate positioning result of the object to be measured; constructing a non - linear error equation set in the global optimization stage to describe the relationship between the three - dimensional coordinates of the object to be measured and the time - difference - of - arrival; solving the Jacobian matrix of the non - linear equation set through matrix transformation; optimizing the initial iteration value in combination with the Fibonacci spherical distribution characteristics; using fixed - point arithmetic to reduce resource consumption and adjust the numerical bit width; dynamically balancing the global search and local convergence speed through an adaptive mechanism.

[0013] Optionally, the specific steps of the 3D positioning algorithm include: using a density-based spatial clustering algorithm with noise (DBSCAN) to optimize and preprocess the received point cloud data; extracting features from the point cloud data through the PointNet++ model, generating a 3D point cloud model, and outputting a 3D point cloud image.

[0014] On the other hand, the present application also provides an ultrasonic 3D imaging system based on FPGA, including: a signal transceiver module for transmitting a chirp signal externally, receiving an echo signal reflected by a target object, and performing preprocessing; a signal processing module for performing adaptive filtering, constant false alarm rate (CFAR) detection, adaptive beamforming, and 3D positioning algorithm processing on the preprocessed signal to generate target position data; an image generation module for reconstructing a 3D point cloud image from the target position data using a density-based spatial clustering algorithm and a deep learning model, and outputting a target 3D image.

[0015] Compared with the prior art, the beneficial effects of the present application are as follows:

[0016] By transmitting a linear frequency modulated continuous wave signal, i.e., a chirp signal, and performing matched filtering, the present application improves the signal energy utilization rate, effectively suppresses the energy attenuation during the propagation of ultrasonic waves, significantly extends the detection range, and meets the requirements of medium- and long-distance environmental perception. The use of adaptive filtering technology dynamically suppresses noise, combined with the constant false alarm rate (CFAR) detection algorithm, adaptively distinguishes real targets from clutter interference, maintains a high signal-to-noise ratio in a complex acoustic environment, and reduces the false detection rate. Through the adaptive beamforming technology, the signal reception directivity is optimized, combined with the time difference of arrival (TDOA) positioning algorithm and the global-local collaborative optimization strategy, to suppress the multipath effect and noise interference, and improve the accuracy of target position calculation. Based on a parallel signal processing architecture, the data flow processing efficiency is optimized, the point cloud generation delay is shortened, the stringent requirements of autonomous driving for real-time performance are met, and the millisecond-level environmental perception response is supported. Using the density-based clustering algorithm (DBSCAN) to filter noise, combined with a deep learning model to extract geometric features, a 3D point cloud image with high density and low noise is generated, accurately characterizing the shape and spatial distribution of the target. Through the innovation of signal processing algorithms and the system collaborative design, the present application solves the technical bottlenecks of traditional ultrasonic sensors in terms of detection range, anti-interference, real-time performance, and positioning accuracy, providing a three-dimensional perception ability with high reliability and strong environmental adaptability for intelligent driving. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of the method steps flow of the present application.

[0018] Figure 2 It is a schematic diagram of the overall framework of the ultrasonic imaging system of the present application.

[0019] Figure 3 It is a schematic diagram of the signal reception module process of the present application.

[0020] Figure 4 This is a schematic diagram of the signal processing module framework of the present application.

[0021] Figure 5 This is a schematic diagram of the NLMS process of the adaptive filtering algorithm of the present application.

[0022] Figure 6 This is a schematic diagram of the adaptive constant false alarm rate (CFAR) detection algorithm of the present application.

[0023] Figure 7 This is a schematic diagram of the flowchart of the TDOA positioning algorithm for global-local collaborative optimization of the present application.

[0024] Figure 8 This is a schematic diagram of the system structure of the present application.

[0025] In the figure: 1 - ultrasonic sensor, 2 - signal transmitter, 3 - signal receiver, 4 - signal processor, 5 - signal imaging module, 10 - signal transceiver module, 20 - signal processing module, 30 - image generation module. Specific implementation manners

[0026] Next, the solution of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to describe the embodiments of the present application here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0028] Those skilled in the art of the present technology can understand that, unless specifically stated otherwise, the singular forms "a", "an", "the", and "said" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present application means the presence of features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or their groups. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to other elements, or there may also be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any unit and all combinations of one or more related listed items.

[0029] Those skilled in the art of the present technology can understand that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as the general understanding of those of ordinary skill in the art to which the present application pertains. It should also be understood that terms such as those defined in a general dictionary should be understood to have a meaning consistent with the meaning in the context of the prior art, and will not be interpreted with an idealized or overly formal meaning unless specifically defined as here.

[0030] It should be understood that the sequence numbers and magnitudes of the steps in this embodiment do not imply the sequence of execution order. The execution order of each process is determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0031] It should be noted that, without conflict, the embodiments and features in the embodiments of the present application may be combined with each other. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0032] Please refer to Figures 1-7 , a method for ultrasonic three-dimensional imaging based on FPGA according to the present application, the steps include: externally transmitting a chirp signal, receiving the echo signal reflected by the target object, and performing preprocessing; performing adaptive filtering, constant false alarm rate detection, adaptive beamforming, and three-dimensional positioning algorithm processing on the preprocessed signal to generate target position data; using a density-based spatial clustering algorithm and a deep learning model to perform three-dimensional point cloud image reconstruction on the target position data, and outputting a target three-dimensional image.

[0033] Specifically, this application transmits a linear frequency modulated continuous wave signal, i.e., a chirp signal, and performs matched filtering to improve the signal energy utilization rate, effectively suppress the energy attenuation during ultrasonic wave propagation, significantly extend the detection range, and meet the requirements of medium and long-distance environmental perception. The adaptive filtering technology is used to dynamically suppress noise, combined with the constant false alarm rate (CFAR) detection algorithm to adaptively distinguish real targets from clutter interference, maintain a high signal-to-noise ratio in complex acoustic environments, and reduce the false detection rate. The adaptive beamforming technology is used to optimize the signal reception directivity, combined with the time difference of arrival (TDOA) positioning algorithm and the global-local collaborative optimization strategy to suppress multipath effects and noise interference, and improve the target position calculation accuracy. Based on a parallel signal processing architecture, the data stream processing efficiency is optimized, the point cloud generation delay is shortened, and the strict real-time requirements of autonomous driving are met, supporting millisecond-level environmental perception responses. The density-based spatial clustering of applications with noise (DBSCAN) algorithm is used to filter noise, combined with a deep learning model to extract geometric features, generating a three-dimensional point cloud image with high density and low noise, accurately representing the target shape and spatial distribution. Through the innovation of signal processing algorithms and system collaborative design, this application solves the technical bottlenecks of traditional ultrasonic sensors in detection range, anti-interference, real-time performance, and positioning accuracy, providing high-reliability and strong environmental adaptability three-dimensional perception capabilities for intelligent driving.

[0034] In some embodiments, the generation steps of the chirp signal include: based on preset start frequency, end frequency, frequency modulation rate, and signal duration parameters, generating waveform data with linearly varying frequency over time through direct digital frequency synthesis method, outputting a linear frequency modulated continuous wave signal through digital-to-analog conversion, and amplifying the signal power through a power amplifier to output a chirp signal that meets the detection range.

[0035] Specifically, this application uses a chirp signal whose frequency varies linearly with time. The chirp signal has pulse compression characteristics. When received, the matched filtering technology is used to achieve pulse compression, which can further improve the range resolution and signal-to-noise ratio. Its input is the chirp signal parameters preset by the system, including start frequency, end frequency, frequency modulation rate, and signal duration, etc. Through the direct digital synthesis (DDS) technology, waveform data is generated according to the calculated frequency, and after digital-to-analog conversion (DAC), a chirp signal with linearly varying frequency over time is output. The waveform data calculation formula of the chirp signal is: In the formula, E(t) is the signal electric field strength or voltage value at time t, t is the time variable, f0 is the start frequency, B is the bandwidth or frequency modulation range, and T is the total signal duration.

[0036] The generated chirp frequency modulation signal is amplified by a power amplifier (PA) to enhance the signal strength to meet the requirements of propagating in complex environments and detecting target objects. The amplified signal is transmitted to the outside for interaction with target objects in the surrounding environment.

[0037] The field-programmable gate array (FPGA) designs an ultrasonic excitation pulse to control the ultrasonic transmitting circuit to emit the driving signal required by the ultrasonic transducer. The signal transmitter 2 generates a control signal to trigger the ultrasonic sensor to emit a linear frequency modulated continuous wave (Chirp) signal and control the analog switches of each receiving channel.

[0038] Specifically, this application generates a linear frequency modulated continuous wave signal based on the direct digital frequency synthesis (DDS) technology, and realizes wideband signal coverage by precisely controlling the change rate of frequency over time (frequency modulation slope). The power amplifier performs non-linear compensation processing on the signal to effectively improve the signal propagation distance and penetration ability. This method significantly improves the range resolution through the phase continuous frequency modulation characteristic, and overcomes the defect that the detection distance is limited due to the rapid attenuation of the energy of the traditional ultrasonic signal.

[0039] In some embodiments, the preprocessing step specifically includes: preliminarily amplifying the echo signal using a low-noise amplifier; dynamically adjusting the signal gain through a time gain compensation mechanism; filtering out high-frequency aliasing components and suppressing DC offset and flicker noise by cascading an anti-aliasing filter and a baseline correction filter; stabilizing the signal amplitude using a voltage-controlled amplifier combined with automatic gain control; and deserializing and buffering the data using a field-programmable gate array, and compensating for the timing deviation through phase-locked loop synchronous sampling and an elastic buffer.

[0040] Specifically, this application introduces a group of low-noise amplifiers (LNAs), including an input impedance matching network, a low-noise field effect transistor, and a temperature compensation module, which can achieve a several-decibel magnitude increase in the amplitude of the input signal within a wide frequency band range, while controlling the noise floor at a low level to effectively avoid introducing additional noise. The weak signal is preliminarily amplified at the front end of the signal link through a multi-stage transistor amplifier circuit with high gain and low noise figure, which is used to parallelly increase the amplitude of the input signal of each channel. For each channel, this application adopts a time gain compensation (TGC) mechanism as a means to adjust signal attenuation, aiming to compensate for the reduction in signal strength caused by energy attenuation during ultrasonic propagation. However, considering the differences in the initial intensities of the signals of each channel, the subsequent signal processor 4 has strict requirements on the signal amplitude, and noise interference always exists. Simply relying on TGC compensation is difficult to fully meet the requirements. Therefore, this application also introduces a voltage-controlled amplifier (VCA) for further signal amplification processing. Based on the variable transconductance principle, the transconductance value of the differential pair transistor is adjusted by controlling the voltage to achieve continuous adjustable gain. It consists of a voltage-current conversion module, a translinear amplification stage, and an output buffer stage inside, and has a wide dynamic range of gain adjustment ability. This design enables the system to dynamically optimize the amplification factor according to the signal characteristics, and at the same time suppresses signal fluctuations through an automatic gain control (AGC) loop to ensure the stability of the output signal amplitude.

[0041] In the signal receiver 3, the present application utilizes a field-programmable gate array (FPGA) to perform secondary magnification adjustment on a preset TGC gain curve. By pre-storing TGC gain values corresponding to different time points calculated and set according to actual application requirements and ultrasonic propagation characteristics. When a signal is input, the FPGA reads the corresponding gain value from the lookup table based on the signal timestamp or propagation time information, and multiplies the input signal by the gain value to achieve precise amplification of the signal amplitude. The serial peripheral interface (SPI) is used to modify the gain controller to achieve dynamic time gain (TGC) compensation. Thus, customized settings can be made according to actual application scenarios and requirements. Thereby, precise regulation of signal gain can be ensured, and various different application scenarios and requirements can be flexibly adapted to.

[0042] The present application adopts two filters to work together and further processes the signal through two-stage filtering to effectively improve the signal-to-noise ratio and obtain a signal with a flat passband and a steep stopband characteristic. Before digital sampling, due to the complex spectral characteristics of the analog signal, if direct sampling is performed, high-frequency signals may produce aliasing phenomena, resulting in distortion of the sampled signal and inability to accurately restore the original signal. Therefore, the present application adopts two filters. The first one is used to achieve anti-aliasing before digital sampling, filtering out high-frequency components higher than half of the sampling frequency. Through a multi-stage cascaded resistor-capacitor network and a feedback adjustment circuit, a gentle passband response and a steep stopband attenuation are formed to effectively eliminate the risk of spectral aliasing. During the signal transmission and processing process, the DC bias and flicker noise will interfere with the normal analysis and processing of the signal, affecting the stability and accuracy of the signal. Another filter is also needed to suppress the DC bias and flicker noise. This filter is designed with an adjustable cut-off frequency, dynamically tracks the baseline drift through a feedback control loop, and at the same time integrates noise suppression technology to transfer the low-frequency interference energy to the stopband. The two-stage filters form a complement through cascaded design, ensuring the integrity of the signal in the passband and achieving deep suppression of wide-band interference components, significantly improving the accuracy and purity of subsequent signal analysis.

[0043] Considering the different requirements for signal characteristics in different application scenarios, this application constructs a parameterized control module in a field-programmable gate array (FPGA), establishes two-way communication with a four-channel analog-to-digital converter (ADC) through the SPI bus, and sends control data packets to the ADC. Each data packet contains a channel address, a filter type identifier (anti-aliasing / baseline correction), a cut-off frequency coefficient, and a gain parameter. The ADC integrates a configurable filter core, dynamically loads the corresponding filter coefficient matrix by parsing the data packet. Among them, the anti-aliasing filter uses an adjustable-order finite impulse response (FIR) structure to reconstruct the roll-off characteristic, and the baseline correction filter eliminates the offset through an infinite impulse response (IIR) topology combined with a DC servo loop. The system sends a synchronization pulse to all ADCs through the clock management unit of the FPGA, loads new parameters immediately after the ADC completes the current frame sampling, and uses a dual-buffer register bank to achieve "hot switching" of filter parameters to ensure signal continuity. This application selects a four-channel ADC for synchronous acquisition, uses 32 acquisition modules for sampling, and converts the analog signal into a digital signal.

[0044] This application realizes data deserialization and buffering through the on-board FPGA, synchronously samples the data stream using the reference clock generated by the phase-locked loop (PLL), and reorganizes the serial bit stream into parallel data according to the bit width requirements. The timing deviation is compensated by an elastic buffer, and the reorganized parallel data is written into a first-in-first-out (FIFO) memory that supports asynchronous clocks to achieve cross-clock domain buffering. The write side of the FIFO is driven by the sampling clock, and the read side is connected to the system main clock. The stable data transmission is achieved through a dual-port RAM structure and a pointer synchronization mechanism. This method has higher flexibility and scalability compared to traditional application-specific integrated circuits (ASICs), and can quickly adapt to different data formats, sampling rates, and application requirements.

[0045] Through the above series of signal preprocessing operations, this application can significantly improve the reception quality of chirp frequency-modulated signals. The low-noise amplifier (LNA) is used to amplify each channel signal in parallel, and the time gain compensation (TGC) is combined to accurately compensate the energy attenuation during the ultrasonic propagation process, thereby realizing the high-fidelity transmission of the signal. At the same time, relying on the programmable characteristics of the FPGA, the system can flexibly and accurately adjust the TGC gain curve to fully meet the requirements of diverse application scenarios. In addition, the FPGA undertakes the deserialization of digital sampling and the data storage task, further improving the data processing efficiency and flexibility of the system, and providing more efficient and reliable technical support for applications in related fields.

[0046] Specifically, in this application, a signal link with wide bandwidth and low noise is constructed through an anti-aliasing filter, a baseline correction filter, and a voltage-controlled amplifier. The anti-aliasing filter eliminates high-frequency aliasing components through a multi-stage resistor-capacitor network. The baseline correction filter suppresses low-frequency noise in combination with a DC servo loop. The voltage-controlled amplifier achieves dynamic gain adjustment through variable transconductance technology. The field-programmable gate array (FPGA) parallel processing architecture realizes signal deserialization and buffer storage, compensates for timing deviations through phase-locked loop synchronous sampling and an elastic buffer, and ensures high-precision synchronous acquisition of multi-channel signals.

[0047] In some embodiments, the steps of the adaptive filtering specifically include: pre-storing the number of taps of the finite impulse response filter, the initial filter coefficients, and the initial step size parameters in the on-chip random access memory of the field-programmable gate array; configuring the sampling rate and channel parameters of the analog-to-digital converter to ensure synchronous acquisition of multi-channel signals; performing shift register delay processing on the multi-channel microphone input signals to generate an input signal vector containing the current and the previous N-1 time signals; calculating the array element delay time in the direction of the desired signal based on the delay summation principle to generate the initial weighting coefficients; obtaining the intermediate output of beamforming through weighted summation operation; calculating the error between the desired signal and the output, and dynamically adjusting the step size parameter according to the power value of the input signal vector; performing weighted summation based on the error signal and the current weighting coefficients to dynamically adjust the weighting coefficients; storing the updated weighting coefficients back into the on-chip random access memory and repeating the iteration until the mean square error is less than the preset threshold or the maximum number of iterations is reached; storing the intermediate data through a block random access memory or an external synchronous dynamic random access memory, and implementing parallel computing using a pipeline architecture.

[0048] Specifically, this application uses the normalized least mean square (NLMS) adaptive filtering algorithm and optimizes the delay and sum (DAS) beamforming algorithm by adaptively optimizing the shape and directivity of the beam to improve the signal-to-noise ratio and anti-interference ability of the received signal. The initialization parameters such as the number of taps N of the FIR filter, the initial filter coefficients, and the initial step size are stored in the on-chip RAM of the FPGA for quick reading during subsequent processing. At the same time as the parameters are set, the ADC is configured to set the sampling rate and sampling channels to ensure the synchronization and accuracy of signal acquisition. When the system receives signals from multiple microphones, the shift register is used to delay the signals. Multiple time-delay copies of the input signal are created to construct the input signal vector x(n), which contains the current and the past N - 1 input signals. In the FPGA, the current weighted coefficient vector and the input signal vector are read from the storage area, and the input signal vector is weighted and summed with the weighted coefficient vector using the internal hardware multiplier and accumulator to obtain the intermediate output of the beamformer. According to the principle of delay and sum DAS, the delay time of each array element is calculated for the desired signal direction θ, and then the initial weighted coefficient w(0) is obtained. The system performs iterative operations by continuously repeating the steps of beamforming, error calculation, and weighted coefficient update. The error e(n) between the desired signal d(n) and the output y(n) of the beamformer is calculated, and by introducing a normalization factor, the normalized least mean square NLMS algorithm is used to update the dynamic step size with the formula, where μ(n) is the step size parameter, x(n) is the input signal vector, and ||x(n)|| 2Denote its squared norm, η is the learning rate parameter, and the step size parameter is adjusted according to the specific application scenario and signal environment to control the convergence speed and stability of the algorithm. The update amount of the weighting coefficient is calculated using the formula w(n + 1) = w(n) + μ(n)e(n)x(n), and the weighting coefficient vector w(n) is updated accordingly. At each iteration, the weighting coefficient is adjusted in the direction that reduces the mean square value of the error signal. The updated weighting coefficient vector w(n + 1) is stored back in the on-chip RAM for the next iteration. By continuously repeating the steps of beamforming, error calculation, and weighting coefficient update, iterative operations are performed to adjust the weighting coefficients of each element, so that the array forms a main beam in the direction of the desired signal, enhances the desired signal, forms nulls in the direction of the interference signal, and suppresses the interference signal to control the convergence speed and stability of the algorithm. And the intermediate data is stored using the Block RAM inside the Field Programmable Gate Array (FPGA) or the external Synchronous Dynamic Random Access Memory (SDRAM) connected to the system. A pipelined design is adopted to improve the calculation speed. The above iterative steps are continuously repeated until the mean square value of the error signal is less than a preset threshold or the number of iterations reaches the maximum set value. When the convergence condition is met, the iteration ends and the final beamforming result is output. During the implementation process, taking advantage of the parallel architecture of the FPGA, operations such as weighted summation, error calculation, and coefficient update are performed simultaneously. The weighted summation operation is implemented using hardware multipliers and accumulators. Compared with software implementation, its calculation speed is faster, which can effectively improve the overall performance of the system. With the help of the shift register and on-chip RAM of the FPGA, signals can be conveniently delayed, filter coefficients, signal delay values, and intermediate results are stored, providing the necessary data storage and processing space for the execution of the algorithm. Through the pipelined design, a complex calculation task is decomposed into multiple stages and executed in parallel in different hardware modules. After each stage completes a part of the calculation, the result is passed to the next stage, thereby realizing continuous data stream processing, effectively improving the calculation throughput rate, and enabling the system to process more data per unit time. A state machine is used to coordinate the operations of each module. The state machine controls the data flow and processing order according to the preset state transition rules, ensuring the collaborative work between each module, ensuring the correct flow of data between modules such as data acquisition, delay, weighted summation, error calculation, and coefficient update, avoiding data conflicts and errors, and ensuring the stability and reliability of the entire system.

[0049] Specifically, the NLMS adaptive filtering algorithm implemented based on the field-programmable gate array (FPGA) hardware in this application optimizes the filtering performance in real time through a dynamic step-size adjustment mechanism. The hardware multiplier and accumulator cooperate to complete the weighted summation operation, and the pipeline architecture enables parallel execution of signal delay processing, error calculation, and coefficient update. The state machine coordinates and controls the data flow between modules, and stores intermediate data through block RAM, significantly improving the signal-to-noise ratio suppression ability of the signal. This method effectively suppresses multipath interference and background noise, and improves the directivity accuracy of beamforming.

[0050] In some embodiments, the weighted coefficient update process is implemented using a hardware multiplier and an accumulator, and the state machine coordinates the cooperative operation of the signal delay, weighted summation, error calculation, and coefficient update modules; among them, the state machine includes five state nodes: signal acquisition state, delay processing state, weighted operation state, error feedback state, and coefficient update state.

[0051] Specifically, this application uses the cooperative design of a hardware multiplier and a state machine to achieve real-time iterative update of the weighted coefficient. The five-state machine cooperation mechanism (signal acquisition state, delay processing state, weighted operation state, error feedback state, coefficient update state) optimizes the calculation process and reduces the algorithm delay time. The on-chip RAM of the field-programmable gate array (FPGA) stores the filter coefficient matrix, and fixed-point arithmetic is used to reduce resource consumption, support dynamic adjustment of the convergence speed and steady-state accuracy, and adapt to the real-time changes of complex acoustic environments.

[0052] In some embodiments, the constant false alarm rate (CFAR) detection step specifically includes: initializing the CFAR algorithm parameters, including setting the number of reference cells, the number of guard cells, the false alarm rate control factor, and the dimension and format of the input data; receiving and storing the amplitude or power value of the ultrasonic echo signal; for each cell to be detected, selecting the surrounding reference cells to form a reference window, and calculating the statistical characteristics of the background noise by dividing it into multiple sub-windows; generating a variability index and a mean ratio according to the statistical characteristics of the sub-windows to judge the uniformity of the signal environment and the existence of clutter edges; dynamically selecting the CFAR algorithm based on the environmental judgment result: selecting the cell-average CFAR algorithm and adjusting the weight in a uniform environment, selecting the improved ordered-statistic CFAR algorithm to correct the maximum value in a clutter-edge environment, and selecting the ordered-statistic CFAR algorithm in a multi-target environment; generating an adaptive detection threshold based on the selected algorithm, and performing a cyclic scan on all cells to be detected to complete target detection; outputting the detection result including the target position information.

[0053] Specifically, this application introduces an improved adaptive constant false alarm rate (CFAR) target detection algorithm, aiming to improve the target detection performance in complex environments by adaptively adjusting the detection threshold. During system initialization, the key parameters of the CFAR algorithm are set, including the number N of reference cells, the number G of guard cells, the CFAR threshold factor T for controlling the false alarm rate, as well as the dimension and format of the input data. Subsequently, the amplitude or power value of the received echo signal is input from the receiving end and stored in the internal memory of the FPGA, organized in the order of cells. For each cell to be detected, the CFAR algorithm selects the surrounding reference cells to construct a window containing N reference cells for estimating the statistical characteristics of background noise or clutter. To avoid the influence of the target signal on the noise estimation, G guard cells are set on both sides of the cell to be detected.

[0054] First, the reference window is carefully divided into M smaller sub - windows. This refined division method can achieve in - depth analysis and evaluation of the signal environment. For each sub - window, its mean and variance are accurately calculated, which serve as the key basis for estimating the background noise level. Based on the mean and variance of the sub - windows, the variability index VI is calculated through the following formula:

[0055] In the formula, VI is the variability index, X(i) is the value of the i - th cell, N is the total number of cells in the reference window, M is the number of sub - windows, and L is the index of the sub - window. This VI index, as the core indicator for measuring the signal distribution uniformity, is of great significance. Based on the calculated VI value, the uniformity state of the signal environment and the presence of clutter edges can be accurately judged. When it is determined that there are clutter edges, the specific position of the clutter edge is further accurately determined by calculating the mean ratio MR value. The calculation formula for the mean ratio MR value is:

[0056] In the formula, MR is the mean ratio, X(i) is the value of the i - th cell, N is the total number of cells in the reference window, and M is the number of sub - windows.

[0057] If there are significant differences in the means of the two windows, it is determined as a clutter - edge environment. At this time, the specific position of the clutter edge is estimated more accurately by calculating MRpartition. The calculation formula is:

[0058] In the formula, MRpartition is the multi - resolution partition, X(i) is the value of the i - th cell, N is the total number of cells in the reference window, and M is the number of sub - windows.

[0059] Based on the calculation results, comprehensively judge the signal environment, and then dynamically select the most suitable CFAR algorithm. If the MR partition result shows a difference in the mean value, the GO-CFAR algorithm applicable to the clutter edge environment is executed at this time; if the MR partition result shows the same mean value, then compare the VI values of the leading window and the lag window, and select the window with the smaller VI value to execute the CA-CFAR algorithm. In particular, when the signal environment is uneven, intelligently decide whether to use the leading window or the lag window to execute the CA-CFAR algorithm according to the VI result. If more than two windows are determined to be variables, that is, execute the OS-CFAR algorithm applicable to the multi-target environment.

[0060] The core advantage of this algorithm is that it can adaptively generate the detection threshold according to the uniformity of the window and the actual presence of the clutter edge. By comparing and analyzing MR and VI, the algorithm can accurately judge the signal environment, so as to select the most optimized detection strategy. Use the VI value to effectively classify the positions of non-homogeneous windows, and select the appropriate window to execute the CFAR algorithm according to the classification results, that is, adjust the reference window weight according to the sub-window characteristics in the uniform environment, and select the window with the smaller VI value to execute CA-CFAR. Use the improved GO-CFAR algorithm in the clutter edge environment and combine the skewness and kurtosis of the sub-windows to correct the maximum value and improve the detection performance at the clutter edge. Use the OS-CFAR algorithm in the multi-target environment. Through this adaptive method, while maintaining a low false alarm rate in the target detection process, it effectively guarantees the accuracy and robustness of target detection. The above process is cycled for each unit to be detected, and the entire unit array is scanned to complete target detection. Finally, output the results of target detection, including the position information of the target or other markers. Utilize the parallel processing ability of FPGA to perform background noise estimation, threshold calculation, and target detection in parallel. Use hardware adders, multipliers, and comparators to accelerate the calculation. The memory is used to store input data, intermediate calculation results, and detection results. Improve the calculation throughput rate through pipeline design. Use a state machine to control each module to ensure the correct data flow. Through the above design, the FPGA implementation of the CFAR target detection algorithm can be realized, so as to realize target detection in a complex environment, with high robustness.

[0061] Specifically, the present application introduces a double-index criterion of variability index and mean ratio, and constructs a three-level environment adaptive detection mechanism. Through the sub-window division strategy, the fine estimation of background noise is realized, and the interference of target signals is eliminated by combining the protection unit design. The cell-averaging constant false alarm rate algorithm CA-CFAR, the greatest-of constant false alarm rate algorithm GO-CFAR, and the ordered statistics constant false alarm rate algorithm OS-CFAR are dynamically selected to achieve the adaptive adjustment of the detection threshold. While maintaining a low false alarm rate, this method significantly improves the target detection accuracy in clutter edges and multi-target environments.

[0062] In some embodiments, the step of, for each unit to be detected, selecting the surrounding reference units to form a reference window and calculating the statistical characteristics of the background noise by dividing into multiple sub-windows specifically includes: equally dividing the reference window into a plurality of sub-windows, respectively calculating the mean and variance of each sub-window, characterizing the signal distribution uniformity by the ratio of the sum of the squares of the sub-window means to the square of the sum of the means, and combining the sub-window mean proportional relationship to locate the clutter edge position.

[0063] Specifically, the present application divides the reference window into multiple independent statistical units through a multi-sub-window division strategy, and characterizes the signal distribution uniformity by the sub-window mean variance ratio. Combining the sub-window mean proportional relationship to locate the clutter edge, a dynamic environment classification model is established. This method effectively distinguishes uniform environments, clutter edges, and multi-target scenarios, provides a reliable environmental perception basis for subsequent algorithm selection, and improves the detection robustness in complex scenarios.

[0064] In some embodiments, the steps of the adaptive beamforming specifically include: deploying a plurality of ultrasonic receiving base stations, and the base stations are optimally arranged according to the Fibonacci spherical distribution; through the direct memory access transmission method, transmitting the pre-stored receiver coordinates, sound speed, iteration parameters, and the initial value of the weighting matrix from the ARM processor side to the field programmable gate array; collecting the time difference of arrival data of each base station in real time, and selecting the time difference of arrival data of the five base stations closest to the object to be measured for weighted average processing; constructing a non-linear equation set based on the time difference of arrival data and linearizing it, and using the least squares method to obtain a preliminary estimate of the coordinates of the object to be measured; introducing the weighted least squares method in the local optimization stage, and dynamically adjusting the weighting matrix to avoid falling into a local optimal solution; using the internal digital signal processor resources of the field programmable gate array to implement matrix operations, and completing the iterative convergence judgment through pipeline design and state machine control; when the sum of the squared residuals is less than a preset threshold or the maximum number of iterations is reached, output the three-dimensional coordinate positioning result of the object to be measured; constructing a non-linear error equation set in the global optimization stage to describe the relationship between the three-dimensional coordinates of the object to be measured and the time difference of arrival; solving the Jacobian matrix of the non-linear equation set through matrix transformation; optimizing the initial iteration value in combination with the Fibonacci spherical distribution characteristics; using fixed-point arithmetic to reduce resource consumption and adjust the numerical bit width; dynamically balancing the global search and local convergence speed through an adaptive mechanism.

[0065] Specifically, in this application, multiple ultrasonic receiving base stations are optimized and deployed according to the Fibonacci spherical distribution to ensure the rationality of the receiver distribution, thus laying a foundation for subsequent positioning calculations. The initial parameters, including receiver coordinates, sound velocity, iteration count threshold, residual threshold, initial value of the weighting matrix, and parameters related to global optimization and local optimization, are stored in the ARM end in advance. Through direct memory access (DMA), high-speed data transmission can be achieved between the ARM and the FPGA without excessive intervention from the CPU. Configure the DMA controller at the ARM end, map the memory space at the ARM end to the address space of the FPGA by specifying the source address (data address at the ARM end) and the target address (address for receiving data at the FPGA end), and obtain the data at the ARM end by reading and writing the corresponding addresses in the FPGA. At the same time, configure the FPGA to connect multiple ultrasonic receivers to ensure that TDOA data can be obtained in real time. During the process of obtaining TDOA data, each receiver receives ultrasonic signals, measures the time difference of arrival of the signals, and converts the time difference data into distance differences. Select one base station as a reference and calculate the distance differences between other base stations and the reference base station. To improve the representativeness of the data, select the TDOA data of the five base stations closest to the object to be measured and perform weighted average processing on them. In the global iterative optimization, first perform least squares optimization by constructing an error equation: h = R 2 +d 2 , where h is the error equation containing receiver coordinates and sound velocity parameters, R 2 is the square of the distance, and d 2It is the square of the time difference of arrival. And matrix transformation is used to solve the optimal estimated value, providing a basis for subsequent in-depth optimization. A non-linear equation system is constructed based on TDOA data and receiver coordinates to describe the three-dimensional coordinates of the object to be measured. The non-linear equation system is linearized, and the least squares method is used to solve the linearized equation system to obtain a preliminary estimated value of the coordinates of the object to be measured. However, when approaching the target value, due to its inherent iterative characteristics, it is easy to get stuck in a local optimal solution, resulting in the inability to further approach the true value and limited accuracy. Therefore, this application adds local optimization. In the local optimization stage, the weighted least squares method is adopted to construct a weighted matrix, which efficiently minimizes the influence of noise, adjusts the iterative direction when approaching the target value, and avoids the algorithm from getting stuck. This algorithm uses the Ga matrix to optimize and solve u_star, and continuously iterates and corrects the error until convergence to obtain a more accurate estimated value of the coordinates of the object to be measured. During the iteration process, the system monitors and adjusts the iterative path of the algorithm to ensure that when approaching the target value, it can effectively avoid falling into the trap of the local optimal solution and continuously approach the true position. Calculate the sum of the squared residuals of all receivers, and judge whether the algorithm converges based on the comparison between the sum of the squared residuals and the preset threshold, and whether the number of iterations exceeds the maximum number of iterations. If the convergence condition is met, the final positioning result, that is, the three-dimensional coordinates of the object to be measured, is output. This algorithm uses the DSP resources inside the FPGA to implement matrix operations. The on-chip RAM is used to store receiver coordinates, TDOA data, intermediate calculation results, etc. The pipeline design is used to improve the calculation throughput rate. The state machine is efficiently used to control the operations of each module to ensure the correctness of the data flow. Fixed-point arithmetic is used to reduce resource consumption, and the bit width is adjusted according to the accuracy requirements. Through global-local collaborative optimization, combining Fibonacci spherical distribution, weighted least squares method, and adaptive adjustment mechanism, this application greatly reduces noise interference and improves the accuracy and reliability of positioning.

[0066] Specifically, this application optimizes the base station layout based on the Fibonacci spherical distribution, and combines the global-local collaborative optimization algorithm to improve the positioning accuracy. The least squares method is used for fast convergence in the global optimization stage, and the weighted least squares method is introduced to suppress noise in the local optimization stage. The DSP resources inside the FPGA are used to accelerate matrix operations, and the pipeline design improves the iteration efficiency. This method avoids getting stuck in the local optimal solution by dynamically adjusting the weighted matrix, significantly improving the anti-noise ability and convergence speed of TDOA positioning.

[0067] In some embodiments, the steps of the three-dimensional positioning algorithm specifically include: using the density-based spatial clustering of applications with noise algorithm to optimize and preprocess the received point cloud data; extracting features from the point cloud data through the PointNet++ model, generating a three-dimensional point cloud model, and outputting a three-dimensional point cloud image.

[0068] Specifically, this application gives full play to the role of the ARM processor as the system core controller, deeply collaborates with the FPGA, and is committed to the refined processing of ultrasonic data and the real-time generation of high-quality three-dimensional point cloud images. This process starts after the efficient signal processing task at the FPGA end is completed. The ultrasonic echo data after being accelerated by the FPGA kernel is transmitted to the ARM processor in digital form through the high-speed AXI bus interface, making full use of the high-bandwidth and low-latency data transmission characteristics of the AXI bus to ensure the real-time transmission requirement of massive data. At the ARM processor end, the data processing process first conducts detailed data reception and collation. The ARM processor receives the data stream from the FPGA and performs fine packet parsing, parsing the continuous data stream into structured data units for subsequent processing. Then, the ARM processor executes the coordinate and unit conversion steps. According to the calibration parameters and coordinate mapping relationships preset by the system, it converts the intermediate data calculated inside the FPGA into coordinate information that conforms to the physical world measurement standard and unifies the data units to ensure that the final output three-dimensional image has clear physical meaning and measurability. The preprocessed data is stored in the high-speed DDR3 memory of the ARM processor, and a strict data verification mechanism is immediately started to verify whether errors or damages occur during data transmission, ensuring the accuracy of the data entering the subsequent three-dimensional point cloud image reconstruction process.

[0069] After data processing, the ARM processor further executes the core algorithm for three-dimensional point cloud image reconstruction. In order to effectively suppress possible residual noise interference in the data and improve the purity and quality of point cloud data, this application uses the DBSCA (Density-Based Spatial Clustering of Applications with Noise) algorithm to optimize the preprocessing of the received point cloud data. The DBSCAN algorithm, with its density-based clustering characteristics, can effectively identify and remove outliers with sparse spatial distribution and small numbers. These points usually originate from random noise or non-ideal measurement conditions. Their filtering helps to significantly improve the signal-to-noise ratio and visual perception of the point cloud model. On this basis, in order to fully tap the deep value of ultrasonic data and achieve higher quality three-dimensional point cloud imaging effects, this application innovatively applies PointNet++, an advanced deep learning algorithm, to perform advanced repair, refined optimization and multi-level feature extraction on point cloud data preprocessed by DBSCAN. As a deep neural network designed specifically for point cloud data processing, the PointNet++ algorithm can directly learn complex geometric features and semantic information from disordered point cloud data, intelligently complete and reconstruct the surface of point cloud data, optimize the density and uniformity of point clouds, and extract rich point cloud feature vectors. It ultimately generates a high-precision, high-resolution three-dimensional point cloud model, which not only achieves accurate perception and three-dimensional expression of the surrounding environment, but also enables the generated three-dimensional point cloud model to directly serve subsequent visualization presentation and more advanced application requirements.

[0070] Specifically, this application integrates the PointNet++ deep learning model with the density-based noise spatial clustering algorithm DBSCAN to achieve adaptive denoising and feature extraction of point cloud data. The DBSCAN algorithm removes outliers through density clustering, and the PointNet++ model extracts deep geometric features and optimizes the density distribution of point clouds. The ARM processor and FPGA work together to achieve high-speed and stable transmission of data streams. This method significantly improves the quality of point cloud data and provides high-precision environmental perception information for autonomous driving.

[0071] Please refer to Figure 8 On the other hand, the present application also provides an FPGA-based ultrasonic three-dimensional imaging system, including: a signal transceiver module, used to transmit chirp signals to the outside, receive echo signals reflected by the target object, and perform preprocessing; a signal processing module, used to perform adaptive filtering, constant false alarm rate detection, adaptive beamforming and three-dimensional positioning algorithm processing on the preprocessed signal to generate target position data; an image generation module, used to use a density-based spatial clustering algorithm and a deep learning model to reconstruct a three-dimensional point cloud image of the target position data, and output a target three-dimensional image.

[0072] Specifically, the system of the present application is an integrated architecture for transmission, acquisition, processing, and imaging based on FPGA. It uses a self-developed signal acquisition platform for data acquisition and performs real-time signal processing through the Zynq platform to generate three-dimensional coordinate data for real-time imaging. The ultrasonic three-dimensional imaging system includes an ultrasonic sensor 1, a signal transmitter 2, a signal receiver 3, a signal processor 4, and a signal imaging module 5. The signal transmission module 2 is used to generate a transmission signal that meets the requirements of ultrasonic three-dimensional imaging; the signal reception module 3 is responsible for receiving the ultrasonic signals returned from the outside world and preprocessing them to optimize the signal quality; the signal processing module 4 performs a series of processes on the signals output by the reception module 3 to obtain relevant information about the target object; the signal imaging module 5 processes the data output by the signal processing module 4 to generate a three-dimensional image and display it on the terminal.

[0073] Aiming at the limitations of traditional constant false alarm rate (CFAR) detection algorithms (such as CA-CFAR, GO-CFAR, SO-CFAR, OS-CFAR algorithms) in complex environments, the present invention introduces an innovative adaptive CFAR algorithm. By introducing two key indicators, namely the window variability index VI and the leading and lagging window mean ratio MR, it realizes a comprehensive and dynamic judgment of the background environment and can more accurately identify different background environments. According to the judgment result of the environment, this algorithm can dynamically select the target detection algorithm with the best performance in this environment, achieving dynamic adaptation to different complex background environments and thus overcoming the single applicability of traditional algorithms.

[0074] The present invention proposes an innovative Time Difference of Arrival (TDOA) positioning algorithm. Through the coordination of global optimization and local optimization, it realizes high-precision and high-robustness positioning of the three-dimensional position of the signal source, thereby improving the overall performance of the positioning system. The present invention proposes a TDOA positioning algorithm based on global-local collaborative optimization, optimizes the base station layout with Fibonacci spherical distribution, combines the weighted average TDOA data of the nearest five base stations, and uses the least squares method for global optimization to obtain a preliminary estimate of the signal source position, providing a high-quality initial value for local optimization, reducing the risk of falling into local optimal solutions, and ensuring global convergence. Local optimization uses the weighted least squares method, constructs a weighted matrix to suppress noise, solves it with the iteratively optimized Ga matrix, and cooperates with the standard deviation and error matrix optimization to achieve fast convergence and precise positioning. Even when the noise is large, it can converge stably, and finally accurately locate the three-dimensional position of the signal source, enhancing the stability and reliability of the system. It realizes high-precision and high-robustness positioning of the three-dimensional position of the signal source and improves the overall performance of the positioning system.

[0075] The present invention innovatively implements an adaptive beamforming algorithm through FPGA, achieving real-time optimization of ultrasonic signal transmission and reception at the hardware level, thereby significantly improving the performance of the system in harsh environments. In the face of signal attenuation and interference caused by factors such as rain, fog, and smoke, the adaptive beamforming algorithm proposed by the present invention can dynamically adjust the direction and gain of the beam. Compared with the traditional fixed beamforming method, its advantage lies in its ability to adapt to environmental changes in real time, thus significantly enhancing the clarity and stability of imaging, providing key technical support for achieving high-quality ultrasonic imaging.

[0076] In addition, the present invention cleverly applies adaptive filtering techniques such as the NLMS algorithm to ultrasonic signal processing, effectively suppressing signal noise and significantly improving signal quality. With the powerful high-speed parallel processing ability of FPGA, the present invention can execute complex adaptive beamforming algorithms in real time and efficiently without relying on external processors, thereby significantly reducing the system latency, increasing the response speed, and greatly reducing the power consumption of the system, achieving the combination of high performance and low power consumption.

[0077] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in various embodiments of the present application. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs and other various media that can store program codes.

[0078] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in this application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0079] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in the relevant technical field, shall be equally included in the patent protection scope of the present application.

Claims

1. An ultrasonic three-dimensional imaging method based on FPGA, characterized in that the steps Including: Transmitting a chirp signal externally, receiving the echo signal reflected by the target object, and performing preprocessing; Performing adaptive filtering, constant false alarm rate detection, adaptive beamforming, and three-dimensional positioning algorithm processing on the preprocessed signal to generate target position data; Using a density-based spatial clustering algorithm and a deep learning model to reconstruct a three-dimensional point cloud image from the target position data and output a target three-dimensional image.

2. The ultrasonic three-dimensional imaging method based on FPGA according to claim 1, wherein The generation steps of the chirp signal include: Based on preset start frequency, stop frequency, chirp rate, and signal duration parameters, generating waveform data with linearly varying frequency over time through direct digital frequency synthesis method, outputting a linear frequency modulated continuous wave signal through digital-to-analog conversion, and amplifying the signal power through a power amplifier to output a chirp signal that meets the detection distance.

3. The ultrasonic three-dimensional imaging method based on FPGA according to claim 1, wherein The preprocessing steps specifically include: Preliminarily amplifying the echo signal using a low-noise amplifier; Dynamically adjusting the signal gain through a time gain compensation mechanism; Filtering out high-frequency aliasing components and suppressing DC offset and flicker noise by cascading an anti-aliasing filter and a baseline correction filter; Stabilizing the signal amplitude using a voltage-controlled amplifier combined with automatic gain control; Using a field programmable gate array for data deserialization and buffering, compensating for timing deviation through phase-locked loop synchronous sampling and an elastic buffer.

4. The ultrasonic three-dimensional imaging method based on FPGA according to claim 1, wherein, The steps of the adaptive filtering specifically include: Pre-storing the number of taps of a finite impulse response filter, initial filter coefficients, and initial step size parameters in the on-chip random access memory of the field programmable gate array; Configuring the sampling rate and channel parameters of the analog-to-digital converter to ensure synchronous acquisition of multi-channel signals; Performing shift register delay processing on the multi-channel microphone input signals to generate an input signal vector containing the current and the signals at the previous N-1 moments; Calculating the element delay time in the direction of the desired signal based on the principle of delay summation to generate initial weighting coefficients; Obtaining an intermediate output of beamforming through weighted summation operation; Calculating the error between the desired signal and the output, and dynamically adjusting the step size parameter according to the power value of the input signal vector; Performing weighted summation based on the error signal and the current weighting coefficients, and dynamically adjusting the weighting coefficients; Storing the updated weighting coefficients back into the on-chip random access memory and repeating the iteration until the mean square error is less than a preset threshold or the maximum number of iterations is reached; Storing intermediate data through a block random access memory or an external synchronous dynamic random access memory, and implementing parallel computing using a pipeline architecture.

5. The ultrasonic three-dimensional imaging method based on FPGA according to claim 4, characterized in that, The process of updating the weighting coefficients is implemented using a hardware multiplier and an accumulator, and the coordinated operation of the signal delay, weighted summation, error calculation, and coefficient update modules is coordinated by a state machine; Among them, the state machine includes five state nodes: signal acquisition state, delay processing state, weighted operation state, error feedback state, and coefficient update state.

6. The ultrasonic three-dimensional imaging method based on FPGA according to claim 1, wherein The steps of the constant false alarm rate detection specifically include: Initializing the parameters of the constant false alarm rate algorithm, including setting the number of reference cells, the number of guard cells, the false alarm rate control factor, and the dimension and format of the input data; Receiving and storing the amplitude or power value of the ultrasonic echo signal; For each cell to be detected, selecting the surrounding reference cells to form a reference window, and calculating the statistical characteristics of the background noise by dividing into multiple sub-windows; Generate the variability index and mean ratio according to the statistical characteristics of the sub-windows to judge the uniformity of the signal environment and the existence of clutter edges; Dynamically select the constant false alarm rate algorithm based on the environmental judgment result: select the cell-averaging constant false alarm rate algorithm and adjust the weight in a uniform environment, select the improved ordered-statistic constant false alarm rate algorithm to correct the maximum value in a clutter edge environment, and select the ordered-statistic constant false alarm rate algorithm in a multi-target environment; Generate an adaptive detection threshold based on the selected algorithm, and perform cyclic scanning on all cells to be detected to complete target detection; Output the detection result including the target position information.

7. The ultrasonic three-dimensional imaging method based on FPGA according to claim 6, characterized in that For each cell to be detected, the step of selecting the reference cells around it to form a reference window and calculating the statistical characteristics of the background noise by dividing into multiple sub-windows specifically includes: Equally divide the reference window into several sub-windows, calculate the mean and variance of each sub-window respectively, characterize the signal distribution uniformity by the ratio of the sum of the squares of the sub-window means to the square of the sum of the means, and locate the clutter edge position in combination with the sub-window mean ratio relationship.

8. The ultrasonic three-dimensional imaging method based on FPGA according to claim 1, characterized in that The steps of the adaptive beamforming specifically include: Deploy multiple ultrasonic receiving base stations, and the base stations are optimally arranged according to the Fibonacci spherical distribution; Through the direct memory access transmission method, transfer the pre-stored receiver coordinates, sound speed, iteration parameters and initial values of the weighting matrix from the ARM processor side to the field programmable gate array; Real-time collect the time difference of arrival data of each base station, and select the time difference of arrival data of the five base stations closest to the object to be measured for weighted average processing; Construct a non-linear equation set based on the time difference of arrival data and linearize it, and use the least squares method to obtain a preliminary estimate of the coordinates of the object to be measured; Introduce the weighted least squares method in the local optimization stage, and avoid falling into the local optimal solution by dynamically adjusting the weighting matrix; Utilize the internal digital signal processor resources of the field programmable gate array to implement matrix operations, and complete the iteration convergence judgment through pipeline design and state machine control; When the sum of the squared residuals is less than the preset threshold or the maximum number of iterations is reached, output the three-dimensional coordinate positioning result of the object to be measured; Construct a non-linear error equation set in the global optimization stage to describe the relationship between the three-dimensional coordinates of the object to be measured and the time difference of arrival; Solve the Jacobian matrix of the non-linear equation set through matrix transformation; Optimize the initial iteration value in combination with the Fibonacci spherical distribution characteristics; Use fixed-point number operations to reduce resource consumption and adjust the numerical bit width; Dynamically balance the global search and local convergence speed through an adaptive mechanism.

9. The ultrasonic three-dimensional imaging method based on FPGA according to claim 1, wherein The steps of the three-dimensional positioning algorithm specifically include: Use the density-based spatial clustering of applications with noise algorithm to optimize and preprocess the received point cloud data; Extract features from the point cloud data through the PointNet++ model, generate a three-dimensional point cloud model, and output a three-dimensional point cloud image.

10. An ultrasonic three-dimensional imaging system based on FPGA, characterized in that, Include: A signal transceiver module for transmitting chirp signals externally, receiving echo signals reflected by the target object, and performing preprocessing; A signal processing module for performing adaptive filtering, constant false alarm rate detection, adaptive beamforming and three-dimensional positioning algorithm processing on the preprocessed signals to generate target position data; An image generation module, configured to perform three-dimensional point cloud image reconstruction on the target location data by using a density-based spatial clustering algorithm and a deep learning model, and output a target three-dimensional image.

Images