Memory, operation method thereof and electronic equipment

Abstract

The embodiment of the invention provides a memory, an operation method thereof and electronic equipment. The memory includes: a memory cell array including a plurality of memory cells organized into a plurality of memory cell sets, conductivity values of the memory cells in one memory cell set being determined based on a weight vector; word lines and bit lines coupled to the plurality of memory cells; the word line driver is coupled to the word lines, and is configured to apply a plurality of read voltages to the plurality of word lines coupled to each memory cell set, respectively, voltage values of some of the plurality of read voltages being determined based on an input vector; the reading circuit is coupled to the bit line and is configured to obtain a plurality of output currents of the bit line coupled to each memory cell set in the plurality of memory cell sets, and calculate and measure the plurality of output currents of each memory cell set to obtain a first measurement signal of each memory cell set; wherein different first measurement signals are used for representing different distances between the weight vector and the input vector.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a memory, an operation method thereof, and an electronic device. Background Art

[0002] With the continuous development of current science and technology, semiconductor devices are widely used in various electronic devices and electronic products. For example, as a non-volatile memory, a NAND memory is a commonly used semiconductor storage device in a computer. How to expand the functions of the memory to better improve the performance of electronic devices including the memory is a topic worthy of discussion. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory, an operation method thereof, and an electronic device.

[0004] According to a first aspect of the present disclosure, there is provided a memory, including:

[0005] A memory cell array, including: a plurality of memory cells, the plurality of memory cells being organized into a plurality of memory cell sets, and the conductance values of the memory cells in one of the memory cell sets being determined based on a weight vector;

[0006] A plurality of word lines and a plurality of bit lines, coupled to the plurality of memory cells;

[0007] A peripheral circuit, including: a word line driver coupled to the plurality of word lines and a readout circuit coupled to the plurality of bit lines; wherein:

[0008] The word line driver is configured to: apply the plurality of read voltages to the plurality of word lines coupled to each of the memory cell sets respectively, and the voltage values of some of the plurality of read voltages being determined based on an input vector;

[0009] The readout circuit is configured to: obtain a plurality of output currents of the bit lines coupled to each of the memory cell sets in the plurality of memory cell sets, perform operations and measurements on the plurality of output currents of each of the plurality of memory cell sets, and obtain a first measurement signal of each of the plurality of memory cell sets; wherein, different first measurement signals are used to characterize different distances between the weight vector and the input vector.

[0010] According to a second aspect of the present disclosure, there is provided an electronic device, including: a host and a memory coupled to the host;

[0011] The host is configured to: provide a plurality of read voltage values to the memory; wherein, some of the read voltage values are determined based on an input vector;

[0012] The memory includes a memory cell array, and the memory cell array includes: a plurality of memory cells, which are organized into a plurality of memory cell sets, and the conductance values of the memory cells in one memory cell set are determined based on a weight vector; the memory is configured to: perform a read operation on the plurality of memory cells in each memory cell set based on the plurality of read voltage values, and obtain a first measurement signal corresponding to each memory cell set among the plurality of memory cell sets; wherein, different first measurement signals are used to characterize different distances between the weight vector and the input vector.

[0013] According to a third aspect of the present disclosure, there is provided a method for operating a memory. The memory includes a memory cell array, and the memory cell array includes: a plurality of memory cells, which are organized into a plurality of memory cell sets, and the conductance values of the memory cells in one memory cell set are determined based on a weight vector; the operation method includes:

[0014] Applying a plurality of read voltages to a plurality of word lines coupled to each memory cell set respectively; wherein, the voltage values of some of the plurality of read voltages are determined based on an input vector;

[0015] Obtaining a plurality of output currents of bit lines coupled to each memory cell set among the plurality of memory cell sets, performing operations and measurements on the plurality of output currents of each of the plurality of memory cell sets, and obtaining a first measurement signal for each of the plurality of memory cell sets; wherein, different first measurement signals are used to characterize different distances between the weight vector and the input vector.

[0016] The embodiments of the present disclosure provide a memory that uses the conductance values of a plurality of memory cells in a memory cell set to map a weight vector, uses a plurality of read voltages to map an input vector, and further uses the magnitude of the operation value of the read currents of a plurality of memory cells under a plurality of read voltages, that is, the first measurement signal, to characterize the magnitude of the Euclidean distance between the weight vector and the input vector. In other words, the embodiments of the present disclosure can use in-memory computing of the memory to implement the calculation of the Euclidean distance between the weight vector and the input vector. This method of calculating the Euclidean distance can be applied to the SOM neural network, which can reduce the computing power consumption of an electronic device including the memory when implementing the SOM neural network and improve the performance of the electronic device. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of a self-mapping neural network provided by an embodiment of the present disclosure;

[0018] Figure 2 It is a schematic diagram of Euclidean distance calculation in a three-dimensional space provided by an embodiment of the present disclosure;

[0019] Figure 3 Schematic diagram of a computer system with a von Neumann architecture provided by an embodiment of the present disclosure;

[0020] Figure 4 Schematic diagram of a memory structure provided by an embodiment of the present disclosure;

[0021] Figure 5 Schematic diagram of mapping a SOM neural network using a memory cell array of a NAND memory provided by an embodiment of the present disclosure;

[0022] Figure 6 Another schematic diagram of mapping a SOM neural network using a memory cell array of a NAND memory provided by an embodiment of the present disclosure;

[0023] Figure 7 Another schematic diagram of mapping a SOM neural network using a memory cell array of a NAND memory provided by an embodiment of the present disclosure;

[0024] Figure 8 Schematic diagram of a readout circuit provided by an embodiment of the present disclosure;

[0025] Figure 9 Schematic diagram of a measurement circuit provided by an embodiment of the present disclosure;

[0026] Figure 10 Schematic diagram of an arithmetic circuit provided by an embodiment of the present disclosure;

[0027] Figure 11 Schematic diagram of an analog-to-digital conversion circuit provided by an embodiment of the present disclosure;

[0028] Figure 12 Another schematic diagram of an arithmetic circuit provided by an embodiment of the present disclosure;

[0029] Figure 13 Schematic diagram of an electronic device provided by an embodiment of the present disclosure;

[0030] Figure 14 Flow chart of an electronic device implementing a SOM neural network algorithm provided by an embodiment of the present disclosure;

[0031] Figure 15 Flow of an operation method of a memory provided by an embodiment of the present disclosure. Detailed implementation manners

[0032] In order to make the objectives, technical solutions, and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be construed as limitations on the present disclosure. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0033] In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0034] In the following description, the terms "first / second / third" only distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged in a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0036] The Self-organizing Mapping (SOM) neural network is an unsupervised machine learning algorithm that mimics the "lateral inhibition phenomenon" of the human brain and can be used in data clustering, visualization, feature extraction, etc. Lateral inhibition in the human brain means that after a nerve cell is excited, it will inhibit other surrounding nerve cells. This inhibitory effect will cause competition among nerve cells, and the result is that some win and some lose. The manifestation is that the winning nerve cells are excited and the losing nerve cells are inhibited. The SOM neural network is an artificial neural network that simulates the above-mentioned lateral inhibition mechanism of the human brain.

[0037] As Figure 1 shown, the SOM neural network includes a two-layer network composed of an input layer and an output layer (also called a competitive layer), and each neuron in the output layer can be connected to all input units in the input layer. Figure 1 In the output layer, there are 3×5 neurons, and each neuron is connected to all input units in the input layer. In one example, there are also lateral connections between the neurons in the output layer. The SOM neural network belongs to a competitive neural network. Its basic idea is that the neurons in the output layer of the network compete for the opportunity to respond to the input, and finally only one neuron wins, and this neuron can represent the classification of the input.

[0038] Next, continue to describe in detail the training process of the SOM neural network in combination with Figure 1 and Figure 2 In the SOM neural network, the input layer includes multiple input units, and the input vector X(x1, x2,..x i ..x M) is represented. Each neuron in the output layer is assigned a weight vector W(w1, w2,..w i ..w M ), also known as weights. The dimension of the weight vector is equal to the dimension of the input vector, that is, the number of elements included in the weight vector is equal to the number of elements included in the input vector. For example, the input vector can be a three-dimensional vector X(x1, x2, x3), and the corresponding weight vector is a three-dimensional vector W(w1, w2, w3).

[0039] The first step in training the SOM neural network is to initialize the weight vectors corresponding to all neurons in the output layer. Exemplarily, the weight vectors can be randomly assigned values or assigned values according to methods commonly used in the art.

[0040] The second step is to provide an input vector. The neurons in the output layer compete with each other, and finally only one neuron wins for each input vector. In some embodiments, by calculating the Euclidean distance (also known as the Euclidean distance) between the weight vector corresponding to each neuron and the input vector, the neuron with the smallest Euclidean distance is determined as the winning neuron. The expression of the Euclidean distance ED is:

[0041] ED 2 =‖X - W‖ 2 =∑ i (x i - w i ) 2 (1)

[0042] where i is any positive integer from 1 to M. The Euclidean distance represents the straight-line distance between two points in space. Therefore, the winning neuron is the neuron with the smallest distance from the input vector.

[0043] Figure 2 shows a schematic diagram of Euclidean distance calculation in three-dimensional space, as Figure 2 shown. The three-dimensional input vector X(x1, x2, x3) can represent the position of point X in three-dimensional space; the weight vector W(w1, w2, w3) of any neuron can represent the position of point W in three-dimensional space. According to formula (1), the Euclidean distance ED between the weight vector and the input vector can be obtained 2 =(x1 - w1) 2 +(x2 - w2) 2 +(x3 - w3) 2 , that is This formula represents the straight-line distance between point X and point W in three-dimensional space.

[0044] In the third step, according to the lateral inhibition mechanism, when the winning neuron is excited, other losing neurons are inhibited. Therefore, it is necessary to adjust not only the weight vector of the winning neuron but also the weight vectors of the neurons adjacent to the winning neuron so that the response of the winning neuron to subsequent similar input vectors is enhanced, and the response of the adjacent neurons to the similar input vector is weakened.

[0045] The SOM neural network uses a neighborhood function to determine which weight vectors of the neighboring neurons around the winning neuron need to be adjusted. In one example, the Mexican hat function can be used as the neighborhood function, and its mathematical expression is as follows:

[0046]

[0047] where h i represents the influence degree of the winning neuron c on any neuron i in the output layer; η represents the learning rate, which usually decreases monotonically with the number of training times; ED 2 (c, i) represents the Euclidean distance between any neuron i in the output layer and the winning neuron c, and the calculation formula can refer to formula (1); σ is the kernel radius, that is, the neighborhood radius of the winning neuron, which usually decreases monotonically with the number of training times.

[0048] The neighborhood function indicates that all neurons within the neighborhood radius adjust their weights to different degrees according to their distances from the winning neuron.

[0049] The SOM neural network adjusts the weights corresponding to the winning neuron and the neurons within its neighborhood using the following formula (3).

[0050] W(t + 1) = W(t) + ΔW(t) = W(t) + η(t)·h i ·[X(t) - W(t)] (3)

[0051] where W(t + 1) represents the updated value of the weight vector of the neuron, W(t) represents the current weight of the weight vector of the neuron, and X(t) represents the current value of the input vector.

[0052] Continue to process new input vectors according to the above steps two and three until the given number of iterations is completed, and the training of the SOM neural network is completed.

[0053] Figure 3A computer system with a von Neumann architecture is shown. The computer system with a von Neumann architecture includes a central processing unit (CPU) 10 and a memory 20. The CPU 10 and the memory 20 are connected by a bus. The bus can transmit data, instructions, and control signals, enabling communication and data exchange between the CPU 10 and the memory 20. The CPU 10 further includes a control unit 11 and a logic unit 12. Among them, the control unit 11 is used to control the operation of the CPU and execute instructions, and the logic unit 12 is used to perform arithmetic and logical operations. The logic unit 12 can perform mathematical operations such as addition, subtraction, multiplication, and division, and can also perform logical operations such as AND, OR, NOT, and exclusive OR.

[0054] When implementing the SOM algorithm using a computer system with a von Neumann architecture, the CPU is used for operations such as Euclidean distance calculation, neighborhood function calculation, and weight update calculation. During the calculation process, data can be temporarily stored in the memory. Due to the high complexity of these calculations, using the CPU for calculation requires a large amount of computing power and power consumption. Moreover, the Euclidean distance of the cumulative bits and the continuous comparison circuit further increase the hardware overhead, making it challenging to implement the SOM algorithm using hardware. In addition, when implementing the SOM algorithm using a computer system with a von Neumann architecture, a large amount of data transmission between the CPU and the memory is involved, which also causes serious computing power consumption. Therefore, how to reduce the computing power consumption when implementing the SOM algorithm is crucial.

[0055] Embodiments of the present disclosure provide a method for implementing a SOM neural network using in-memory computing. In-memory computing refers to performing arithmetic operations within the memory to reduce the latency and power consumption of data transfer between the CPU and the memory, and can also reduce the computing power consumption of the CPU. Figure 4 A schematic structural diagram of a memory provided by an embodiment of the present disclosure is as Figure 4 shown. The memory includes:

[0056] A memory cell array 100, which includes: a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. The plurality of memory cells are organized into a plurality of memory cell sets 110. The conductance values of the memory cells in one memory cell set are determined based on one weight vector; the plurality of word lines 410 and the plurality of bit lines 420 are coupled to the plurality of memory cells;

[0057] Peripheral circuits, including: a word line driver 200 coupled to the plurality of word lines 410 and a readout circuit 300 coupled to the plurality of bit lines 420; where:

[0058] The word line driver 200 is configured to: apply a plurality of read voltages to the plurality of word lines 410 coupled to each memory cell set 110 respectively. The voltage values of some of the plurality of read voltages are determined based on the input vector;

[0059] The readout circuit 300 is configured to: obtain a plurality of output currents of bit lines 420 coupled to each of a plurality of memory cell sets 110, perform operations and measurements on the plurality of output currents of each of the plurality of memory cell sets 110, and obtain a first measurement signal for each of the plurality of memory cell sets 110; wherein, different first measurement signals are used to characterize different distances between the weight vector and the input vector.

[0060] In the embodiments of the present disclosure, the Euclidean distance of different weight vectors is compared by using the memory cell array 100 and the readout circuit 300. According to formula (1), the expression of the Euclidean distance ED can be further transformed into:

[0061]

[0062] In the process of determining the winning neuron, the input vectors for different neurons are the same, that is, in the Euclidean distance expression (4) of different neurons the values of the terms are equal. Therefore, when comparing the Euclidean distances of different neurons, the influence of can be ignored, and only the values of the two terms are compared.

[0063] According to Ohm's law, the current I, voltage V, and conductance G satisfy I = VG. The embodiments of the present disclosure propose to map the element value w i of the weight vector by using the conductance value G of the memory cell, and map the element value x i of the input vector by using the read voltage V. Then, when the read voltage V is applied to the gate of the memory cell, the magnitude of the read current value I of the memory cell can reflect the magnitude of x i w i Similarly, map the sum of squares of the elements of the weight vector by using the conductance value G of the memory cell Map by using the read voltage V the coefficient of the term, then the magnitude of the read current of the memory cell can also reflect the magnitude of the product of and its coefficient. Based on this, the embodiments of the present disclosure propose that the magnitude of the operation value I of the read currents of a plurality of memory cells can be used to reflect the magnitude of the value in the Euclidean distance formula.

[0064] In one example, a mapping relationship between the operation value i of the read currents of a plurality of memory cells and can be established:

[0065]

[0066] This mapping relationship converts the comparison of the Euclidean distances ED of different neurons into the comparison of the operation values i of the readout currents corresponding to different neurons. Moreover, the larger the operation value i of the readout current, the smaller the corresponding Euclidean distance ED. Therefore, the neuron corresponding to the largest operation value i of the readout current can be determined as the winning neuron.

[0067] In this embodiment, a plurality of memory cells corresponding to a weight vector are defined as a memory cell set 110, and the conductance values of the memory cells in the memory cell set 110 are determined based on the element values of the weight vector. Specifically, the conductance values of some memory cells in the memory cell set 110 have a mapping relationship with the element values w i of the weight vector, and the conductance values of some memory cells have a mapping relationship with the weight vector.

[0068] In this embodiment, the voltage values of a group of read voltages are used to map the multiple element values x i of the input vector, and the coefficients of the input vector, that is, the voltage values of some of the read voltages in this group of read voltages are determined based on the element values x i of the input vector, and the voltage values of some of the read voltages are determined based on the coefficients of the input vector.

[0069] Taking a memory cell set as an example, in actual operation, the word line driver 200 applies a group of read voltages to multiple word lines coupled to the memory cell set 110, and the readout circuit 300 can obtain multiple output currents of the bit lines coupled to the memory cell set 110. Here, the output current of the bit line after applying the read voltage is the readout current of the memory cell.

[0070] The readout circuit 300 is configured to be designed according to formula (5), perform operations and measurements on the multiple output currents of the memory cell set 110 according to formula (5), and obtain a first measurement signal of the memory cell set. The first measurement signal is used to indicate the operation value I of the readout current of the memory cells in the memory cell set 110. For example, the value of the first measurement signal is equal to the operation value I of the readout current of the memory cells in the memory cell set 110. Therefore, different first measurement signals can characterize different Euclidean distances between the weight vector and the input vector.

[0071] Next, in combination with Figure 5 , taking the example that the input vector in the SOM neural network includes M elements, the solution of the present disclosure will be further explained.

[0072] If the input vector in the SOM neural network includes M elements, then the weight vector also includes M elements, and the memory cell set 110 corresponding to the weight vector includes M + 1 memory cell groups, where M is a positive integer. Among them, in the first M memory cell groups, the equivalent conductance value G of the i-th memory cell groupi has a first mapping relationship with the value w of the i-th element of the weight vector, where i is any positive integer from 1 to M. The equivalent conductance value G of the memory cell group i is the calculated value of the conductance values of all the memory cells in the memory cell group. The equivalent conductance value G of the (M + 1)-th memory cell group i has a second mapping relationship with the value of the function formed by the M elements of the weight vector. Here, the value of the function formed by the M elements refers to the negative value of the sum of the squares of the M elements M+1

[0073] It should be noted that Figure 5 the w corresponding to the memory cell in i and represent that the conductance value of the memory cell is used to map w i and Similarly, the x on the word line i and represent that the voltage value of the read voltage is used to map x i and

[0074] Exemplarily, the first mapping relationship is equal to the second mapping relationship because if the first mapping relationship is not equal to the second mapping relationship, it cannot be guaranteed that the inference relationship of "if the first measurement signal corresponding to the first neuron is greater than the first measurement signal corresponding to the second neuron, then the Euclidean distance corresponding to the first neuron is less than the Euclidean distance corresponding to the second neuron" must hold.

[0075] The first mapping relationship is monotonic within the range of the element values of the weight vector and within the range of the conductance values of the memory cells. The second mapping relationship is monotonic within the range of the value of the function formed by the M elements (for example ) and within the range of the conductance values of the memory cells. Exemplarily, both the first mapping relationship and the second mapping relationship are linear relationships.

[0076] In some embodiments, both the first mapping relationship and the second mapping relationship are linear relationships and the proportionality coefficients are equal, that is, the element value w of the weight vector i is scaled by a certain multiple to obtain the equivalent conductance value G i , and is scaled by the same multiple to obtain the equivalent conductance value G M+1 .

[0077] The input vector includes M elements, and a set of read voltages corresponding to the input vector includes M + 1 read voltages. Among them, the voltage values of the first M read voltages are determined based on the M elements of the input vector, and the voltage value V of the (M + 1)-th read voltage M+1 is based on the coefficient ​Determined. Exemplarily, the voltage value V of the i-th read voltage among the first M read voltages i has a third mapping relationship with the value x of the i-th element of the input vector i There is a fourth mapping relationship between the voltage value V of the (M + 1)-th read voltage M+1 and the coefficient .

[0078] Exemplarily, the third mapping relationship is equal to the fourth mapping relationship. The third mapping relationship has monotonicity within the range of the element values of the input vector and within the range of the voltage values of the read voltages. Exemplarily, the third mapping relationship is a linear relationship, and the fourth mapping relationship can also be a linear relationship.

[0079] In some embodiments, both the third mapping relationship and the fourth mapping relationship are linear relationships and have equal proportionality coefficients. That is, the element value x of the input vector i is scaled by a certain multiple to obtain the voltage value V of the read voltage i , and is scaled by the same multiple to obtain the read voltage value V M+1 .

[0080] It should be noted that the first mapping relationship and the third mapping relationship may be the same or different. In a specific embodiment, both the first mapping relationship and the third mapping relationship may be linear relationships but have different proportionality coefficients. The magnitudes of the proportionality coefficients mainly depend on the ranges of the element values of the input vector and the read voltage values, as well as the ranges of the element values of the weight vector and the conductance values of the storage cells.

[0081] Taking a set of storage cells as an example, when the word line driver applies the first to the (M + 1)-th read voltages to the first to the (M + 1)-th storage cell groups correspondingly, the readout circuit can be configured to: obtain the output currents of the first to the (M + 1)-th storage cell groups, and obtain the sum value I of the M + 1 output currents through measurement and calculation. According to Kirchhoff's law, the sum value I of the M + 1 output currents can be expressed as:

[0082] I = ∑ i V i G i + V M+1 G M+1 (6)

[0083] where i is any positive integer from 1 to M.

[0084] Taking the example that both the first mapping relationship and the third mapping relationship are linear relationships, and the second mapping relationship is equal to the first mapping relationship, and the fourth mapping relationship is equal to the third mapping relationship, by comparing formula (6) and formula (5), it can be seen that the function F in formula (5) is equal to the pair Scaling is performed, and the scaling coefficient is equal to the product of the coefficients of the first mapping relationship and the third mapping relationship. Therefore, based on the magnitudes of the first measurement signals corresponding to different neurons, the magnitudes of the Euclidean distances between different neurons can be accurately obtained.

[0085] In this embodiment, the equivalent conductance value G of the storage cell group i is the calculated value of the conductance values of the storage cells in the storage cell group, including two cases: one is when the storage cell group includes one storage cell, and the equivalent conductance value G of the storage cell group i is the conductance value of the storage cell. The other is when the storage cell group includes multiple storage cells, and the equivalent conductance value of the storage cell group is the first-level calculated value of the conductance values of all the storage cells in the storage cell group. The first-level calculation refers to addition and subtraction operations. The equivalent conductance value of the storage cell group can be obtained by performing an addition operation, a subtraction operation, or both an addition operation and a subtraction operation on the conductance values of multiple storage cells.

[0086] In one embodiment, when the storage cell group includes multiple storage cells, the equivalent conductance value of the storage cell group can be: the difference between the conductance values of all the storage cells in the storage cell group. This is because the element value w of the weight vector i may be positive or negative. is negative, but the conductance value of the storage cell is always positive, and it is impossible to establish a mapping relationship with the negative element value of the weight vector. Based on this, in this embodiment, a subtraction operation is performed on the conductance values of multiple storage cells, and their difference is used as the equivalent conductance value of the storage cell group, so that the equivalent conductance value can include negative numbers.

[0087] The following takes the storage cell group including two storage cells as an example for illustration. As Figure 6 shown, the two storage cells are the first storage cell and the second storage cell respectively. The first storage cell has a first conductance value The second storage cell has a second conductance value The equivalent conductance value G of the storage cell group i is equal to the difference between the conductance values of the two storage cells According to Kirchhoff's law, formula (6) can be converted to:

[0088]

[0089] i is any positive integer from 1 to M.

[0090] That is, there is a first mapping relationship between the difference between the conductance values of the two storage cells and the element value w of the weight vector. The value of the function formed by the difference between the conductance values of the two storage cells and the M elements of the weight vector (for example, i ​) There is a second mapping relationship therebetween. It can also be understood that there is a first mapping relationship between the conductance values of the two storage units and the element values of the weight vector, and there is a second mapping relationship between the conductance values of the two storage units and the values of the function composed of M elements of the weight vector.

[0091] It should be understood that the embodiments of the present disclosure do not limit the number of storage units in the storage unit group, nor do they limit the addition operation and / or subtraction operation on the conductance values of multiple storage units in the storage unit group. Performing an addition operation on the conductance values of multiple storage units can increase the positive range of the equivalent conductance value. Performing a subtraction operation on the conductance values of multiple storage units can make the equivalent conductance value include zero and negative numbers. In practical applications, the number of storage units in the storage unit group can be designed according to needs, and different operations on the conductance values of multiple storage units can be implemented through a readout circuit.

[0092] In some embodiments, the memory can be a NAND memory, and the storage units of the NAND memory can be floating-gate field-effect transistors or charge-trapping field-effect transistors. The storage units of the NAND memory can have multiple states for storing multiple bits of data. When the same read voltage is applied, the read currents of the storage units in different states are different, and it can be deduced that the conductance values of the storage units in different states are different. In other words, the storage units of the NAND memory have multiple conductance values for multiple states. Exemplarily, the state of the storage unit can be changed by a programming operation and / or an erasing operation, so as to change the conductance value of the storage unit.

[0093] In some embodiments, as the programming voltage increases, the storage unit is programmed to a state with a larger threshold voltage. At the same read voltage, the read current corresponding to the state with a larger threshold voltage is smaller, and the corresponding conductance value is also smaller. Therefore, increasing the programming voltage in the programming operation can reduce the conductance value. On the contrary, the erasing operation can reduce the threshold voltage, making the conductance value increase. Exemplarily, a Gate Induced Drain Leakage (GIDL) erasing mechanism can be adopted to perform an erasing operation on each storage unit in the storage unit array one by one.

[0094] It should be understood that the memory in the embodiments of the present disclosure includes but is not limited to NAND memories. The memory in the embodiments of the present disclosure can be any memory with continuously adjustable states of storage units. For example, a NOR memory or a PRAM memory. The storage units of the NOR memory can be floating-gate field-effect transistors, having continuously adjustable states and conductance values. The storage units of the PRAM memory include a phase change storage layer using a phase change material. The resistance values of the phase change material in the crystalline state and the amorphous state are different. Therefore, by adjusting the proportion of the crystalline material and the amorphous material in the phase change storage layer, the phase change storage layer can have continuously adjustable resistance values, that is, continuously adjustable states and conductance values.

[0095] Exemplarily, in combination with Figure 5 and Figure 6 , taking the memory as a NAND memory as an example, the solution of the present disclosure will be further explained. As Figure 5 and Figure 6 shown, the memory cell array 100 of the NAND memory includes a plurality of memory strings 120. The upper end of each memory string 120 is coupled to a bit line (BL) 420, and the lower end is coupled to an array common source ACS. The memory string 120 includes an upper selection transistor, a plurality of memory cells 121, and a lower selection transistor connected in series in sequence. The plurality of memory strings 120 are arranged in an array along intersecting first and second directions, and the first and second directions intersect and are both perpendicular to the extending direction of the memory string. Exemplarily, the first direction is the X direction, the second direction is the Y direction, and the extending direction of the memory string 120 is the Z direction. The upper selection gate line (TSG) 430 extends along the first direction and is coupled to the gates of the upper selection transistors of the plurality of memory strings 120 arranged side by side along the first direction. A plurality of upper selection gate lines TSG1, TSG2... are arranged side by side along the second direction. The bit line 420 extends along the second direction and is coupled to the upper ends of the plurality of memory strings 120 arranged side by side along the first direction. A plurality of bit lines BL1, BL2... are arranged side by side along the second direction. The word line 410 extends in the plane where the first direction and the second direction are located and is coupled to the gate of one memory cell in each memory string 120. A plurality of word lines are arranged side by side along the extending direction of the memory string 120. For one memory string, different memory cells are coupled to different word lines. The lower selection gate line (BSG) 440 is coupled to the gates of the lower selection transistors of all memory strings. By controlling the voltages applied to the bit line 420, the word line 410, the upper selection gate line 430, and the lower selection gate line 440, programming operations and erasing operations can be performed on a certain memory cell individually.

[0096] In some embodiments, the multiple memory cells 121 in each memory cell set are organized into a plurality of memory strings 120, and each memory string 120 includes M + 1 memory cells connected in series; wherein, a plurality of memory cells located in different memory strings 120 and coupled to the same word line 410 form a memory cell group, and the M + 1 memory cell groups in the memory cell set are sequentially coupled to M + 1 word lines 410.

[0097] The memory cell set includes M + 1 memory cell groups. Since the same read voltage is applied to the multiple memory cells in the same memory cell group, the multiple memory cells in the same memory cell group can be coupled to the same word line 410. And M + 1 read voltages are correspondingly applied to the M + 1 memory cell groups, so that the M + 1 memory cell groups can be coupled to M + 1 word lines 410.

[0098] Continue to refer to Figure 6, the number of memory strings where a set of memory cells is located is equal to the number of memory cells within a memory cell group. For example, in this embodiment, a memory cell group includes two memory cells 121, and the difference in the conductance values of the two memory cells is the equivalent conductance value G of the memory cell group i , then all the memory cells of a set of memory cells are located in two memory strings. Different sets of memory cells are located in different memory strings.

[0099] In some embodiments, the i-th memory cell groups of different sets of memory cells are commonly coupled to the i-th word line 410, where i is any positive integer from 1 to M + 1. It should be understood that the i-th memory cell groups of different sets of memory cells are all applied with the i-th read voltage v i , coupling them to the same word line 410 facilitates applying the i-th read voltage v to all sets of memory cells simultaneously i , so as to shorten the time of the read operation, and further shorten the calculation time of the Euclidean distance. In some other embodiments, the i-th memory cell groups of different sets of memory cells can also be coupled to different word lines, then multiple read operations are required to obtain the output currents of the i-th memory cell groups of all sets of memory cells.

[0100] Refer to Figure 6 , in this embodiment, it is equivalent to selecting the memory cells coupled to M + 1 word lines 410 from the memory cell array to participate in the Euclidean distance calculation. Here, it can be either continuously selecting M + 1 word lines from multiple word lines or discontinuously selecting M + 1 word lines. The number of selected word lines depends on the number of elements of the input vector. In this embodiment, the input vector includes M elements, so M + 1 word lines are selected.

[0101] In some embodiments, as Figure 6 shown, multiple memory strings 120 where a set of memory cells is located can be coupled to the same upper select gate line 430 and coupled to different bit lines 420, so as to simultaneously obtain the readout currents of multiple memory cells within the memory cell group. The memory strings 120 where multiple sets of memory cells are located can be coupled to multiple upper select gate lines 430, and the bit lines 420 to which the memory strings where multiple sets of memory cells are located are coupled can be partially the same.

[0102] It should be understood that in some other embodiments, as Figure 7 shown, multiple memory strings 120 where different sets of memory cells 110 are located can also be coupled to the same upper select gate line 430 and coupled to different bit lines 420, that is, the multiple memory strings 120 participating in the Euclidean distance calculation are coupled to the same upper select gate line 430, and the readout circuit can simultaneously obtain the readout currents of multiple memory cells of the i-th memory cell group within all sets of memory cells.

[0103] In the embodiments of the present disclosure, the coupling manner of the memory string 120 where multiple memory cell sets are located to the bit line 420 and the upper select gate line 430 (or rather, the positions of these memory strings in the memory array) are not limited herein. However, their coupling manner to the bit line and the upper select gate line will affect the reading manner and / or the number of reading operations, thereby affecting the overall computing speed.

[0104] In some embodiments, when performing a reading operation on a memory cell array, the word line driver sequentially applies the first to the (M + 1)-th reading voltages to the first to the (M + 1)-th word lines; wherein, the voltage value of the i-th reading voltage v i has a third mapping relationship with the value of the i-th element of the input vector, where i is any positive integer from 1 to M; the voltage value of the (M + 1)-th reading voltage v M+1 has a fourth mapping relationship with the preset coefficients of the function formed by the M elements of the weight vector (for example, ).

[0105] In some embodiments, in one reading operation, only one upper select gate line 430 is activated, and the word line driver only applies the corresponding reading voltage v i to one word line 410 among the M + 1 word lines. After the readout circuit obtains the output current on the bit line, the next reading operation is performed. In other words, in this embodiment, only the reading operation on the memory array is used to obtain the output current of each memory cell, and the reading operation is not used to perform operations on the output current of the memory cell.

[0106] For example, in another embodiment, if two memory strings are coupled to the same bit line, then activating the upper select gate line to which they are coupled during the reading operation can obtain the sum of the readout currents of the memory cells of the two memory strings on the bit line, that is, a sum operation is performed on the readout currents of the two memory cells. In this embodiment, the reading operation is performed in units of pages, and the sum and difference operations are not performed on the readout currents of the memory cells by using the reading operation, but the readout circuit is used for the operations, which can reduce the mutual influence between the readout currents of different memory cells and improve the accuracy of the final calculation result.

[0107] Figure 8 is a schematic diagram of the readout circuit provided by the embodiments of the present disclosure. As Figure 8 shown, the readout circuit 300 includes a current interface circuit 310, and the current interface circuit 310 is connected to the bit line coupled to the same memory cell set; the current interface circuit includes: a measurement circuit 311 and an arithmetic circuit 312 connected to the measurement circuit 311.

[0108] The measurement circuit 311 is correspondingly connected to the bit line 420. The number of measurement circuits 311 is equal to the number of bit lines 420 coupled to the same set of memory cells. The measurement circuit 311 is configured to: in response to the word line driver applying a corresponding read voltage to any one of the multiple word lines, obtain the output current of the bit line, convert the output current into an output voltage and output it; wherein, the multiple output voltages form a set of output voltages.

[0109] The arithmetic circuit is configured to: in response to the word line driver applying multiple read voltages to the multiple word lines, perform arithmetic operations on the output voltages received multiple times to obtain a first measurement signal corresponding to the set of memory cells. Here, the arithmetic circuit is configured to perform arithmetic operations on multiple sets of output voltages according to the arithmetic relationship between the equivalent conductance value of the memory cell group and the conductance values of multiple memory cells within the memory cell group, the first to fourth mapping relationships, and the Euclidean distance calculation formula to obtain the first measurement signal.

[0110] Here, it should be noted that the readout circuit may be different according to the connection manner between the memory string where the set of memory cells is located and the bit line. For example, Figure 5 In the corresponding memory cell array, the memory strings where all sets of memory cells are located are coupled to the same set of bit lines. Therefore, only one current interface circuit is required for the readout circuit. In this embodiment, as Figure 8 shown, different sets of memory cells are coupled to different sets of bit lines. Therefore, multiple current interface circuits are required.

[0111] Next, taking Figure 8 the shown set of memory cells as an example, the current interface circuit 300 will be described in detail. The memory cells of a set of memory cells 110 are located in two memory strings 120. The two memory strings 120 are coupled to two bit lines 420. Each current interface circuit 310 includes two measurement circuits 311. When the word line driver applies the i-th read voltage to the i-th word line among the M + 1 word lines, the two measurement circuits 311 can simultaneously obtain the readout currents of the two memory cells within the i-th set of memory cells from the two bit lines 420, and convert the two readout currents into two output voltages. The two output voltages form a set of output voltages of the i-th set of memory cells.

[0112] After the word line driver sequentially applies the corresponding M + 1 read voltages to the M + 1 word lines, the two measurement circuits 311 will output M + 1 sets of output voltages corresponding to the M + 1 sets of memory cells. Each set of output voltages includes two output voltages. The arithmetic circuit 312 receives the M + 1 sets of output voltages and performs arithmetic operations on the M + 1 sets of output voltages according to the following formula (7), that is, performs subtraction operations on the two output voltages within the set, and performs addition operations on the results of the subtraction operations on the multiple sets of output voltages to obtain the first measurement signal, which is used to characterize the magnitude of the Euclidean distance between the weight vector corresponding to the set of memory cells and the input vector.

[0113] Figure 9 Schematic diagram of the measurement circuit provided by the embodiments of the present disclosure. As Figure 9 shown, the measurement circuit 311 includes: a current-voltage conversion circuit, the current conversion circuit is connected to the bit line 420 and is configured to: obtain the output current of the bit line, convert the output current into an output voltage and output it.

[0114] The present disclosure does not limit the specific circuit structure of the current-voltage conversion circuit, and it can be any current-voltage conversion circuit commonly used in the art. In some embodiments, as Figure 9 shown, the current-voltage conversion circuit includes an operational amplifier OP1 and a first resistor R1. The positive input terminal of the operational amplifier OP1 is connected to the bit line 420 for receiving the output current of the bit line; the negative input terminal of the operational amplifier OP1 is connected to a power supply node, such as connected to the ground wire. One end of the first resistor R1 is connected to the positive input terminal of the operational amplifier OP1, and the other end is connected to the output terminal of the operational amplifier OP1. The output terminal of the operational amplifier OP1 is used to output / transmit the output voltage.

[0115] In some embodiments, as Figure 10 shown, the arithmetic circuit includes:

[0116] an analog-to-digital conversion circuit 3121, connected to the measurement circuit and configured to: receive multiple groups of output voltages, convert the multiple groups of output voltages into multiple groups of digital signals and output them;

[0117] a first-stage arithmetic circuit 3122, connected to the analog-to-digital conversion circuit 3121 and configured to: perform a first-stage arithmetic operation on multiple digital signals in each group of digital signals received each time according to the arithmetic operation between the equivalent conductance value and the conductance value of the storage units in the storage unit group, and generate an arithmetic signal;

[0118] an accumulation circuit 3123, connected to the first-stage arithmetic circuit 3122 and configured to: sum multiple arithmetic signals received multiple times to obtain a first measurement signal.

[0119] The present disclosure does not limit the specific circuit structures of the analog-to-digital conversion circuit 3121, the first-stage arithmetic circuit 3122, and the accumulation circuit 3123, and they can be any circuits commonly used in the art. In some embodiments, the analog-to-digital conversion voltage 3121 can be any one of a flash analog-to-digital conversion circuit, a capacitive integration analog-to-digital conversion circuit, a Σ-Δ analog-to-digital conversion circuit, and a pipelined analog-to-digital conversion circuit. Figure 11 Shows a schematic diagram of a flash analog-to-digital conversion circuit. As Figure 11As shown, the analog-to-digital conversion circuit 3121 may include a reference voltage circuit, a comparator circuit, and an encoding circuit. Among them, the reference voltage circuit includes a plurality of second resistors 31211 connected in series, such that the reference voltage circuit has a plurality of nodes with different electric potentials. The comparator circuit may include a plurality of comparators 31212. The first input terminal of each comparator 31212 is connected to the reference voltage circuit, and the second input terminal is for receiving an output voltage. The first input terminals of different comparators 31212 are connected to different nodes in the reference voltage circuit. The output terminal of the comparator 31212 is connected to the encoding circuit 31213, and the encoding circuit 31213 is used to output a digital signal. Exemplarily, the comparator circuit includes 2 N -1 comparators 31112, and the encoding circuit 31213 is used to output an N-bit digital signal.

[0120] Exemplarily, as Figure 10 shown, taking the example that the memory cell group includes two memory cells and the equivalent conductance value of the memory cell group is equal to the difference between the conductance values of the two memory cells, the number of analog-to-digital conversion circuits is 2. The input terminals of the analog-to-digital conversion circuits 3121-1 and 3121-2 are respectively connected and coupled to two measurement circuits of the same memory cell set. The analog-to-digital conversion circuits 3121-1 and 3121-2 are used to receive two output voltages from the two measurement circuits when the word line driver applies a corresponding read voltage to any one of the M + 1 word lines, convert the two output voltages into two digital signals and output them. In response to the word line driver applying the corresponding M + 1 read voltages to the M + 1 word lines, the multiple analog-to-digital conversion circuits output M + 1 groups of digital signals and operation signals.

[0121] The first-level operation circuit 3122 includes a subtractor. The two input terminals of the subtractor are respectively connected to the output terminals of the two analog-to-digital conversion circuits 3121-1 and 3121-2, and are used to receive two digital signals from the two analog-to-digital conversion circuits 3121-1 and 3121-2 and subtract the two digital signals to generate an operation signal when the word line driver applies a corresponding read voltage to any one of the M + 1 word lines. In response to the word line driver applying the corresponding M + 1 read voltages to the M + 1 word lines, the subtractor outputs M + 1 operation signals.

[0122] Exemplarily, the accumulation circuit includes an adder, and the adder is configured to sum the received M + 1 operation signals to obtain a first measurement signal.

[0123] It should be understood that according to the above formula (7), in some other embodiments, the digital signals can also be summed first and then a first-level operation is performed. Exemplarily, the operation circuit may include a plurality of accumulation circuits and a first-level operation circuit. Each accumulation circuit is used to connect an analog-to-digital conversion circuit. The accumulation circuit responds to the word line driver applying corresponding M + 1 read voltages to M + 1 word lines, sums the received M + 1 digital signals, and generates M + 1 sum signals. The first-level operation circuit is connected to a plurality of accumulation circuits and is configured to perform a first-level operation on the plurality of sum signals according to the operation between the equivalent conductance value and the conductance values of the memory cells in the memory cell group to generate a first measurement signal. Still taking the memory cell group including two memory cells as an example, the accumulation circuit includes an adder. The input terminals of the adder are respectively connected to the analog-to-digital conversion circuit. The adder responds to the word line driver applying corresponding M + 1 read voltages to M + 1 word lines, sums the received M + 1 digital signals, and generates a sum signal. The first-level operation circuit includes a subtractor, which is connected to two adders and is used to subtract the two sum signals to generate a first measurement signal.

[0124] In some other embodiments, as Figure 12 shown, the operation circuit 312 includes:

[0125] A first-level operation circuit 3122, connected to a plurality of measurement circuits, and configured to: perform a first-level operation on a plurality of output voltages in each received set of output voltages according to the operation between the equivalent conductance value and the conductance values of the memory cells in the memory cell group to obtain an operation result;

[0126] An analog-to-digital conversion circuit 3121, connected to the first-level operation circuit 3122, and configured to: receive the operation result, convert the operation result into a result digital signal and output it;

[0127] An accumulation circuit 3123, connected to the analog-to-digital conversion circuit 3121, and configured to: sum the multiple result digital signals received multiple times to obtain a first measurement signal.

[0128] Exemplarily, as Figure 12 shown, taking the memory cell group including two memory cells and the equivalent conductance value of the memory cell group being equal to the difference between the conductance values of the two memory cells as an example. The number of measurement circuits is 2. In response to the word line driver applying corresponding M + 1 read voltages to M + 1 word lines, the measurement circuits output M + 1 sets of output voltages, and each set includes two output voltages.

[0129] The first-level operation circuit 3122 is an Analog-shift Amplifier, which includes a second operational amplifier OP2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. One end of the third resistor R3 is used to connect to one of the two measurement circuits to receive an output voltage, and the other end of the third resistor R3 is connected to the negative input terminal of the second operational amplifier OP2. One end of the fifth resistor R5 is used to connect to the other of the two measurement circuits to receive another output voltage, and the other end of the fifth resistor is connected to the positive input terminal of the second operational amplifier OP2. The fourth resistor R4 is connected in parallel between the negative input terminal and the output terminal of the second operational amplifier OP2, and the sixth resistor R6 is connected between the negative input terminal of the second operational amplifier OP2 and the ground terminal. The analog shift amplifier is used to calculate the difference between the two output voltages. Among them, the output terminal of the second operational amplifier OP2 is used to output the voltage difference between the two output voltages as the operation result.

[0130] In some embodiments, when the same read voltage is applied to multiple memory cells with the same conductance value, the output current on the bit line may not be a fixed value but fluctuate within a certain range. The first-level operation circuit 3122 adopts an analog shift amplifier, which can convert currents in different ranges into different voltages, making the operation result of the first-level operation circuit 3122 more accurate.

[0131] As Figure 12 shown, the analog-to-digital conversion circuit 3121 is connected to the first-level operation circuit 3122. In response to the word line driver applying corresponding M + 1 read voltages to M + 1 word lines, the analog-to-digital conversion circuit 3121 receives M + 1 operation results, and sequentially converts the M + 1 operation results into M + 1 result digital signals and outputs them.

[0132] Exemplarily, the accumulation circuit includes an adder configured to sum the received M + 1 result digital signals to obtain a first measurement signal.

[0133] Continuing to refer to Figure 8 , the peripheral circuit further includes:

[0134] A comparison circuit 320, connected to the current interface circuit 310, is configured to: obtain multiple first measurement signals, compare the magnitudes of the multiple measurement signals, and output a comparison result;

[0135] A control logic 400, connected to the comparison circuit 320, is configured to: determine a winning memory cell set according to the comparison result, where the weight vector corresponding to the winning memory cell set is the winning weight vector.

[0136] As Figure 8As shown, multiple input terminals of the comparison circuit 320 are connected to output terminals of multiple operational circuits in the current interface circuit 310. In response to the word line driver applying corresponding M + 1 read voltages to M + 1 word lines, the comparison circuit receives M + 1 first measurement signals, compares the magnitudes of the M + 1 measurement signals, and then outputs a comparison result.

[0137] In some embodiments, the control logic 400 is configured to: according to the comparison result output by the comparison circuit, determine the set of memory cells corresponding to the largest first measurement signal among the multiple first measurement signals as the winning set of memory cells. The weight vector corresponding to the winning set of memory cells is the winning weight vector, and the Euclidean distance between the winning weight vector and the input vector is the smallest. Refer back Figure 5 , where the set of memory cells corresponding to the largest first measurement signal I2 is the winning set of memory cells, corresponding to the winning weight vector.

[0138] The neuron corresponding to the winning weight vector is the winning neuron. In the algorithm of the SOM neural network as described above, after determining the winning neuron, the third step is executed to update the winning weight vector of the winning neuron to obtain the updated winning weight vector. In addition, neighboring neurons can also be determined according to the winning neuron and the neighborhood function, and the weight vectors of the neighboring neurons are updated.

[0139] Exemplarily, the external device obtains the winning weight vector, and after updating the winning weight vector of the winning neuron, obtains the updated winning weight vector; and, based on the updated winning weight vector, the first mapping relationship, and the second mapping relationship, determines the target conductance value of the memory cells in the winning set of memory cells. The external device sends the target conductance value of the winning set of memory cells to the memory.

[0140] The peripheral circuit of the memory is configured to: at least update the conductance value of the memory cells in the winning set of memory cells to the target conductance value; as described above, the target conductance value is determined based on the updated winning weight vector.

[0141] In some embodiments, the conductance value of the memory cells in the winning set of memory cells is updated as follows: the peripheral circuit performs a programming operation or an erasing operation on the memory cells in the winning set of memory cells to update the conductance value of the memory cells to the target conductance value.

[0142] As described above, different states of the memory cells correspond to different conductance values. Therefore, by performing a programming operation or an erasing operation, the state of the memory cells is updated, thereby updating the conductance value of the memory cells.

[0143] Taking the programming operation as an example, exemplarily, the word line driver is configured to: sequentially apply a first programming voltage and a programming verification voltage to the word lines coupled to the memory cells to be programmed in the winning set of memory cells;

[0144] The sense circuit is configured to: when the word line driver applies a programming verification voltage, obtain a verification current on the bit line to which the memory cell to be programmed is coupled, measure the verification current, and output a second measurement signal;

[0145] The control logic, coupled to the sense circuit and the word line driver, is configured to: receive the second measurement signal, obtain the current value of the verification current based on the second measurement signal, and obtain the actual conductance value of the memory cell according to the programming verification voltage and the current value of the verification current; compare the actual conductance value with the target conductance value, and if the actual conductance value is different from the target conductance value, control the word line driver to apply a second programming voltage and a programming verification voltage to the word line.

[0146] Here, the memory cell to be programmed is one of the M + 1 memory cells in the winning memory cell set.

[0147] The measurement circuit in the sense circuit is used to receive the verification current on the bit line, measure the verification current, and output a second measurement signal. The control logic is coupled to the output terminal of the measurement circuit in the sense circuit, and the control logic obtains the current value of the verification current according to the second measurement signal. Exemplarily, the second measurement signal is a voltage value, and an analog-to-digital conversion circuit may also be connected between the control logic and the measurement circuit to convert the voltage value into a numerical value, which directly shows the magnitude of the verification current. The control logic divides the current value of the verification current by the voltage value of the programming verification voltage to obtain the actual conductance value of the memory cell. Then, the control logic compares the magnitudes of the actual conductance value and the target conductance value. If the actual conductance value is greater than the target conductance value, the control logic controls the word line driver to apply a second programming voltage with a larger voltage value and a programming verification voltage to the word line. If the actual conductance value is less than the target conductance value, the peripheral circuit performs a GIDL erase operation on the memory cell to be programmed. After the GIDL erase operation, it is also necessary to apply a programming verification voltage to the memory cell to be programmed to verify whether the actual conductance value is equal to the target conductance value after the GIDL erase operation. The GIDL erase operation may be any GIDL erase operation commonly used in the art, and the present disclosure does not limit this.

[0148] In some embodiments, the external device may also determine the neighboring neurons of the winning neuron according to the neighborhood function, update the neighboring weight vectors corresponding to the neighboring neurons according to the neighborhood function, and determine the target conductance values of the neighboring weight vectors according to the updated neighboring weight vectors, the first mapping relationship, and the second mapping relationship, and send the target conductance values to the memory.

[0149] The memory is further configured to: update the conductance values of the memory cells in the neighboring memory cell set, and the updated conductance values are determined based on the updated neighboring weight vectors.

[0150] Exemplarily, the peripheral circuit of the memory updates the conductance values of the memory cells in the neighboring memory cell sets through an erase operation and a program operation. The erase operation and the program operation are the same as those for the memory cells to be programmed in the winning memory cell set described above, so they will not be elaborated here.

[0151] Return to Figure 5 , the neighboring weight vector is the weight vector to be updated. There are also some neurons in the output layer that are far from the winning neuron, and the weight vectors corresponding to them do not need to be updated, that is, they belong to the weight vectors that remain unchanged. Therefore, the conductance values of the memory cell sets corresponding to them do not need to be updated in the current training.

[0152] After updating the conductance values of the memory cells in the memory cell sets corresponding to the winning weight vector and the neighboring weight vector, the external device then performs the next training. Specifically: according to the next input vector, a set of read voltages corresponding to the next input vector is determined, and this set of read voltages is sent to the memory, and the memory performs read operations multiple times. By looping the above read operation - program / erase operation, the training of the SOM neural network model for all input vectors is completed.

[0153] The embodiments of the present disclosure also provide an electronic device for implementing the SOM neural network algorithm, such as Figure 13 shown, the electronic device includes: an external device 30 and a memory 20;

[0154] The external device 30 is configured to: provide a plurality of read voltage values to the memory; wherein, some of the read voltage values are determined based on the input vector;

[0155] The memory 20 includes a memory cell array, and the memory cell array includes: a plurality of memory cells, and the plurality of memory cells are organized into a plurality of memory cell sets. The conductance value of the memory cells in one memory cell set is determined based on one weight vector; the memory is configured to: perform read operations on the plurality of memory cells in each memory cell set based on the plurality of read voltage values, and obtain a first measurement signal corresponding to each memory cell set in the plurality of memory cell sets; wherein, different first measurement signals are used to characterize different distances between the weight vector and the input vector.

[0156] Here, the memory includes any of the memories described above, and is used to implement the comparison of the magnitudes of the Euclidean distances between different weight vectors and input vectors.

[0157] The external device 20 includes a host 31. A memory controller may be integrated in the host, and the host can communicate with a memory through the memory controller. Alternatively, the external device includes a host 31 and a memory controller. The memory controller is connected to the host and the memory, and the memory controller is used to implement communication between the host and the memory. It should be noted that the signal interactions between the host and the memory mentioned in the embodiments of the present disclosure, such as "the host sends a read voltage value and a conductance value to the memory" and "the memory sends a winning right vector to the host", include both direct signal interactions between the host and the memory and signal interactions between the host and the memory through the memory controller.

[0158] In some embodiments, the input vector includes M elements;

[0159] The host is configured to: provide M + 1 read voltage values to the memory; wherein, the first to the Mth read voltage values are determined based on the values of the first to the Mth elements of the input vector, and the (M + 1)th read voltage is a fixed read voltage value.

[0160] The data for training the SOM neural network model includes multiple input vectors, and each input vector corresponds to a set of read voltage values. Among the different sets of read voltages corresponding to different input vectors, the first to the Mth read voltage values are determined based on the input vector, and the (M + 1)th read voltage value is a fixed read voltage value.

[0161] In some embodiments, the host stores: a third mapping relationship between the voltage value of the read voltage and the element value of the input vector, and a fourth mapping relationship between the voltage value of the read voltage and the preset coefficients of the function composed of the M elements of the weight vector. The fourth mapping relationship is the same as the third mapping relationship.

[0162] The host is configured to: based on the third mapping relationship, map the values of the first to the Mth elements of the input vector to the voltage values of the first to the Mth read voltages; based on the fourth mapping relationship, map the preset coefficients to the voltage value of the (M + 1)th read voltage.

[0163] Exemplarily, the range of the voltage value of the read voltage is in the amplification region of the storage unit. The storage unit is a kind of transistor. When the storage unit is in the amplification region, the output current changes linearly with the input voltage basically, and has a basically fixed conductance value.

[0164] Exemplarily, different input vectors may correspond to different third mapping relationships and fourth mapping relationships.

[0165] The input vector corresponds to including M elements, and the weight vector also includes M elements. As described above, the set of memory cells includes M + 1 groups of memory cells, where M is a positive integer; among them, the conductance value of the memory cells in the i-th group of memory cells is determined based on the value of the i-th element of the weight vector, and i is any one of 1 to M; the conductance value of the memory cells in the (M + 1)-th group of memory cells is determined based on the function value of the function composed of M elements of the base weight vector.

[0166] The host is configured to: provide the conductance values of the memory cells in M + 1 groups of memory cells to the memory.

[0167] In some embodiments, the host stores: a first mapping relationship between the element values of the weight vector and the conductance values of the memory cells in the group of memory cells, and a second mapping relationship between the function values of the function composed of M elements of the weight vector and the conductance values of the memory cells in the group of memory cells; the second mapping relationship is the same as the first mapping relationship.

[0168] The host is configured to: based on the first mapping relationship and the second mapping relationship, map the values of the M elements of the weight vector to the conductance values of the memory cells in M + 1 groups of memory cells.

[0169] Taking the group of memory cells including two memory cells (i.e., the first memory cell and the second memory cell) as an example, the first mapping relationship is the mapping relationship between the conductance value of the first memory cell, the conductance value of the second memory cell, and the element value of the weight vector. The second mapping relationship is the mapping relationship between the conductance value of the first memory cell, the conductance value of the second memory cell, and the function value of the function of all elements of the weight vector (for example,).

[0170] The first mapping relationship and the second mapping relationship in the host can exist in the form of a mapping relationship table, or in the form of a formula, etc., and the present disclosure does not limit this.

[0171] In a data training, after the host sends the voltage values of a set of read voltages obtained based on the input vector to the memory, the memory performs multiple read operations to obtain multiple first measurement signals. The memory is also configured to: compare the magnitudes of the multiple first measurement signals to determine the winning set of memory cells;

[0172] The host is configured to: determine the winning weight vector based on the winning set of memory cells.

[0173] Exemplarily, the control logic in the memory determines, according to the comparison result output by the comparison circuit, that the set of memory cells corresponding to the largest first measurement signal among the multiple first measurement signals is the winning set of memory cells.

[0174] Exemplarily, the memory cells in the winning memory cell set are distributed in multiple memory strings, and the control logic can send the address information of the memory strings to the host. The host can determine the winning right vector based on the address information of the winning memory cell set provided by the memory.

[0175] The host is further configured to: at least update the winning right vector; and determine the target conductance value of the memory cells in the winning memory cell set according to the updated winning right vector and provide it to the memory. The memory is further configured to: update the conductance value of the memory cells in the winning memory cell set to the target conductance value.

[0176] In addition, the host can also be configured to: determine the neighboring right vector of the winning right vector according to the neighborhood function, update the neighboring right vector; and determine the target conductance value of the memory cells in the neighboring memory cell set according to the updated neighboring right vector and provide it to the memory. The memory is further configured to: update the conductance value of the memory cells in the neighboring memory cell set corresponding to the neighboring right vector to the target conductance value.

[0177] The manner in which the host updates the winning right vector and the neighboring right vector, and determines the target conductance values of the winning memory cell set and the neighboring memory cell set is as described above, so it will not be elaborated. Exemplarily, the host is configured to: update the winning right vector and the neighboring right vector according to the neighborhood function.

[0178] In some embodiments, corresponding to the first step of SOM neural network training, the right vectors corresponding to all neurons are initialized. The electronic device according to the embodiments of the present disclosure is further configured to: the host sends the initial conductance values of all memory cells to the memory, and the memory makes the memory cells have corresponding initial conductance values through the programming operation of the memory cells. In some embodiments, the initial conductance value can be a random value within the conductance value range of the memory cells. In other embodiments, the host can use any commonly used method in the art to generate the initial values of multiple right vectors, and generate the initial conductance values of the memory cell sets corresponding to the right vectors based on the initial values of the right vectors.

[0179] In an embodiment of the present disclosure, during one training, the memory cell array of the memory is used to calculate the Euclidean distance through a read operation; the peripheral circuit of the memory is used to measure and compare the read currents of the memory cell array to determine the winning memory cell set. The host determines the neighboring neurons according to the winning neurons, calculates the updated winning weight vector of the winning neurons and the updated neighboring weight vectors of the neighboring neurons; and controls the memory to perform programming operations and / or erase operations based on the updated winning weight vector and the updated neighboring weight vectors to update the conductance values of the winning memory cell set and the neighboring memory cell set. Through multiple data trainings, functions such as data classification of the SOM neural network are realized. In the embodiment of the present disclosure, the step of determining the winning neurons is realized by in-memory computing, which can reduce a large amount of host computing power consumption. And it can reduce the data interaction between the host and the memory, further reducing the computing power consumption.

[0180] The following combines Figure 14 to detail the process of the electronic device provided in the embodiment of the present disclosure to implement the SOM neural network algorithm. Figure 14 The actions within the gray background box are completed by the memory, and the actions within the white background box are independently completed by the external device. Taking the training of the SOM neural network model as an example, as Figure 14 shown, in the first step, the threshold voltage of the array is initialized. Exemplarily, the threshold voltage of the memory cell array can be initialized in the following way: the host obtains the initial values of the weight vectors of all neurons in the output layer based on a commonly used method in the art; obtains the initial conductance values of the memory cells in the memory cell set corresponding to the weight vectors based on the initial values of the weight vectors, and sends the initial conductance values to the memory. The memory performs programming operations and / or erase operations on the memory cells in the memory cell array to adjust the threshold voltage of the memory cells, thereby adjusting the states of the memory cells so that the memory cells have the initial conductance values.

[0181] In the second step, a read voltage is input on the array. In some embodiments, the host determines the voltage values of a set of read voltages (for example, M + 1 read voltages) based on an input vector and sends the voltage values of the read voltages to the memory. Exemplarily, the host can preprocess the input vector, normalize the element values of all input vectors to [0, 1], and the voltage value range of the read voltages includes the [0, 1] interval, then the element values of the normalized input vector can be directly used as the voltage values of the first M read voltages, and the voltage value of the (M + 1)-th read voltage is 0.5V. That is, the third mapping relationship means that the voltage value of the read voltage is equal to the element value of the normalized input vector; the fourth mapping relationship means that the value of the read voltage value is equal to the value of the preset coefficient. The word line driver in the memory sequentially applies the corresponding M + 1 read voltages to M + 1 word lines.

[0182] In the third step, the winning neuron corresponding to the maximum current is obtained through a sense circuit. Here, the current refers to the operation value I of the sense currents of multiple memory cells in formula (6), that is, the first measurement signal in the embodiments of the present disclosure. Exemplarily, after the word line driver applies M + 1 read voltages, the sense circuit measures and operates on the sense currents obtained from the bit lines to obtain multiple first measurement signals, and the magnitudes of the first measurement signals are used to indicate the magnitudes of the weight vector and the input vector. The memory determines the weight vector corresponding to the maximum first measurement signal as the winning weight vector, and the winning weight vector corresponds to the winning neuron.

[0183] In the fourth step, the neighborhood function and the weight update value are calculated. Exemplarily, the host determines the neighboring weight vectors according to the neighborhood function, and calculates the update value of the winning weight vector and the update value of the neighboring weight vectors according to the neighborhood function. Based on the update value of the winning weight vector and the update value of the neighboring weight vectors, the host determines the conductance update value of the winning memory cell set and the conductance update value of the neighboring weight vectors and sends them to the memory.

[0184] In the fifth step, the conductance values of the memory cells corresponding to the array are updated through programming / erasing operations. Exemplarily, the memory updates the conductance values in the winning memory cell set and the neighboring memory cell set through programming operations and / or GIDL erasing operations.

[0185] In the sixth step, it is determined whether it is the last set of data. That is, the host determines whether it is the last input vector. If the host determines that it is not the last set of data, training continues according to the next set of data, that is, the second to sixth steps are executed according to the next input vector.

[0186] One set of data can be trained multiple times. If the host determines that it is the last set of data, the host executes the seventh step to determine whether it is the last training process. If the host determines that it is not the last training, the next training continues, and the second to seventh steps are executed. If it is the last training process, the training ends.

[0187] After training the SOM neural network, the SOM neural network can also be tested. The testing steps are the same as the second and third steps of the training steps. After the host sends the voltage values of a set of read voltages converted from the input vector to the memory, the memory can determine the winning memory cell through in-memory computing. The winning memory cell can be used to indicate the category to which the input vector belongs. Therefore, this electronic device can be used for applications such as data classification.

[0188] The electronic device provided by the embodiments of the present disclosure enables the memory to implement the SOM neural network through in-memory computing, without using the host to calculate complex Euclidean distances and determine neighboring neurons. On the one hand, compared with the traditional method of implementing the SOM neural network by the host, the in-memory computing method provided by the embodiments of the present disclosure is not limited by the von Neumann bottleneck and can greatly save the computing power consumption of the host. On the other hand, the 3D NAND memory has the advantages of high storage density, low write power consumption, and high reliability, which can reduce the occupied area of the storage units participating in the SOM algorithm and save computing power consumption.

[0189] The embodiments of the present disclosure also provide an operation method for a memory. The memory includes a storage cell array, and the storage cell array includes: a plurality of storage cells, and the plurality of storage cells are organized into a plurality of storage cell sets. The conductance values of the storage cells in one storage cell set are determined based on one weight vector. As Figure 15 shown, the operation method includes:

[0190] S100: Applying a plurality of read voltages to the multiple word lines coupled to each storage cell set respectively; wherein, the voltage values of some of the plurality of read voltages are determined based on the input vector;

[0191] S200: Obtaining a plurality of output currents of the bit lines coupled to each storage cell set in the plurality of storage cell sets, performing operations and measurements on the plurality of output currents of each in the plurality of storage cell sets, and obtaining a first measurement signal for each in the plurality of storage cell sets; wherein, different first measurement signals are used to characterize different distances between the weight vector and the input vector.

[0192] In some embodiments, as Figure 15 shown, the operation method further includes:

[0193] S300: Comparing the magnitudes of the plurality of first measurement signals to determine the winning storage cell set; wherein, the weight vector corresponding to the winning storage cell set is the winning weight vector.

[0194] In some embodiments, the weight vector includes M elements, the storage cell set includes M + 1 storage cell groups, and M is a positive integer; wherein, the conductance values of the storage cells in the i-th storage cell group are determined based on the value of the i-th element of the weight vector, and i is a positive integer from 1 to M; the conductance values of the storage cells in the (M + 1)-th storage cell group are determined based on the value of a function composed of M elements of the weight vector;

[0195] In step S100, applying a plurality of read voltages to the multiple word lines coupled to each storage cell set respectively includes:

[0196] Apply the 1st to the (M + 1)th read voltages to multiple word lines coupled to the 1st to the (M + 1)th memory cell groups in each memory cell set; wherein, the voltage values of the 1st to the Mth read voltages are determined based on the values of the 1st to the Mth elements of the input vector, and the (M + 1)th read voltage is determined based on the coefficients of a function composed of M elements of the weight vector.

[0197] In some embodiments, multiple memory cells in each memory cell set are organized into multiple memory strings, and each memory string includes (M + 1) memory cells connected in series; wherein, multiple memory cells located in different memory strings and coupled to the same word line form a memory cell group, and the ith memory cell groups of different memory cell sets are commonly coupled to the ith word line; multiple memory cell sets are coupled to (M + 1) word lines;

[0198] The above-mentioned applying the 1st to the (M + 1)th read voltages to multiple word lines coupled to the 1st to the (M + 1)th memory cell groups in each memory cell set includes: sequentially applying the 1st to the (M + 1)th read voltages to the 1st to the (M + 1)th word lines.

[0199] In some embodiments, in step S200, obtaining the first measurement signal of any one of the multiple memory cell sets includes:

[0200] After each application of a read voltage to any one of the (M + 1) word lines, obtain multiple output currents of multiple bit lines coupled to the same memory cell set, and convert the multiple output currents into multiple digital signals; wherein, the multiple digital signals form a set of digital signals;

[0201] In response to applying the corresponding read voltages to the (M + 1) word lines, perform operations on multiple sets of digital signals received multiple times to obtain the first measurement signal corresponding to the memory cell set.

[0202] In some embodiments, the above-mentioned converting multiple output currents into multiple digital signals includes:

[0203] Convert multiple output currents into multiple output voltages, and convert the multiple output voltages into multiple digital signals.

[0204] In some embodiments, in a memory cell set, there is a first mapping relationship between the equivalent conductance value of the ith memory cell group and the value of the ith element of the weight vector, where i is any positive integer from 1 to M; there is a second mapping relationship between the equivalent conductance value of the (M + 1)th memory cell group and the value of a function composed of M elements of the weight vector, and the equivalent conductance value of a memory cell group is the arithmetic value of the conductance values of the memory cells in the memory cell group;

[0205] The above-mentioned performing operations on multiple sets of digital signals received multiple times to obtain the first measurement signal corresponding to the memory cell set includes:

[0206] Based on the operation between the equivalent conductance value and the conductance values of the memory cells in the memory cell group, perform operations on multiple digital signals in each received set of digital signals to generate an operation signal; sum multiple operation signals received multiple times to obtain the first measurement signal.

[0207] Exemplarily, the second mapping relationship is the same as the first mapping relationship.

[0208] In some embodiments, the operation method further includes:

[0209] Compare the magnitudes of multiple first measurement signals to determine a winning set of memory cells; wherein, the weight vector corresponding to the winning set of memory cells is the winning weight vector.

[0210] In some embodiments, comparing the magnitudes of the multiple first measurement signals to determine a winning set of memory cells includes: determining the set of memory cells corresponding to the largest first measurement signal among the multiple first measurement signals as the winning set of memory cells.

[0211] In some embodiments, the operation method further includes: updating at least the conductance values of the memory cells in the winning set of memory cells to a target conductance value; wherein, the target conductance value is determined based on the updated winning weight vector.

[0212] In some embodiments, updating at least the conductance values of the memory cells in the winning set of memory cells to a target conductance value includes: performing a programming operation or an erasing operation on the memory cells in the winning set of memory cells to update the conductance values of the memory cells to the target conductance value.

[0213] In some embodiments, performing a programming operation on the memory cells in the winning set of memory cells includes:

[0214] Sequentially apply a first programming voltage and a programming verification voltage to the word lines coupled to the memory cells to be programmed in the winning set of memory cells;

[0215] When applying the programming verification voltage to the word line, obtain the verification current on the bit line coupled to the memory cell to be programmed, and measure the current value of the verification current;

[0216] Obtain the actual conductance value of the memory cell according to the programming verification voltage and the current value of the verification current;

[0217] Compare the actual conductance value with the target conductance value. If the actual conductance value is different from the target conductance value, apply a second programming voltage and a programming verification voltage to the word line.

[0218] The programming method of the memory provided by the embodiments of the present disclosure uses the conductance values of multiple memory cells in a memory cell set to map a weight vector, uses a read voltage to map an input vector, and further uses the magnitude of the operation value of the read current of multiple memory cells under the read voltage to characterize the magnitude of the Euclidean distance between the weight vector and the input vector. That is, it uses in-memory computing of the memory to implement some functions of the SOM neural network, thereby reducing the computing power consumption of the host.

[0219] The above embodiments are only illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present disclosure should still be covered by the claims of the present disclosure.

Claims

1. A memory, characterized in that, Comprising: A memory cell array, comprising: a plurality of memory cells, the plurality of memory cells being organized into a plurality of memory cell sets, and the conductance values of the memory cells in one of the memory cell sets being determined based on a weight vector; A plurality of word lines and a plurality of bit lines, coupled to the plurality of memory cells; A peripheral circuit, comprising: a word line driver coupled to the plurality of word lines and a sense circuit coupled to the plurality of bit lines; wherein: The word line driver is configured to: apply a plurality of read voltages to the plurality of word lines coupled to each of the memory cell sets respectively, and the voltage values of some of the plurality of read voltages are determined based on an input vector; The sense circuit is configured to: obtain a plurality of output currents of the bit lines coupled to each of the plurality of memory cell sets, perform operations and measurements on the plurality of output currents of each of the plurality of memory cell sets, and obtain a first measurement signal of each of the plurality of memory cell sets; wherein, different first measurement signals are used to characterize different distances between the weight vector and the input vector.

2. The memory according to claim 1, characterized in that The weight vector includes M elements, and the memory cell set includes M + 1 memory cell groups, where M is a positive integer; wherein, There is a first mapping relationship between the equivalent conductance value of the i-th memory cell group and the value of the i-th element of the weight vector, and i is any positive integer from 1 to M; the equivalent conductance value of the memory cell group is an operation value of the conductance values of the memory cells in the memory cell group; There is a second mapping relationship between the equivalent conductance value of the (M + 1)-th memory cell group and the value of a function formed by the M elements, and the second mapping relationship is the same as the first mapping relationship.

3. The memory according to claim 2, wherein Each of the memory cell groups includes two memory cells, and the equivalent conductance value of the memory cell group is the difference between the conductance values of the two memory cell groups.

4. The memory according to claim 2, characterized in that, The plurality of memory cells of each of the memory cell sets are organized into a plurality of memory strings, and each of the memory strings includes M + 1 of the memory cells connected in series; Wherein, a plurality of the memory cells located in different memory strings and coupled to the same word line form a memory cell group, and the M + 1 memory cell groups of the memory cell set are sequentially coupled to M + 1 word lines.

5. The memory according to claim 4, characterized in that, The i-th memory cell groups of different memory cell sets are commonly coupled to the i-th word line; The word line driver, connected to the M + 1 word lines, is configured to: sequentially apply the 1st to the (M + 1)-th read voltages to the 1st to the (M + 1)-th word lines respectively; wherein, there is a third mapping relationship between the voltage value of the i-th read voltage and the value of the i-th element of the input vector, and i is any positive integer from 1 to M; there is a fourth mapping relationship between the voltage value of the (M + 1)-th read voltage and a preset coefficient of a function formed by the M elements of the weight vector, and the fourth mapping relationship is the same as the third mapping relationship.

6. The memory according to claim 4, wherein The sense circuit includes: a current interface circuit, the current interface circuit being connected to the plurality of bit lines coupled to the same memory cell set; the current interface circuit includes: Multiple measurement circuits, which are correspondingly connected to the multiple bit lines, are configured to: in response to the word line driver applying a read voltage to any one of the multiple word lines, acquire multiple output currents of the multiple bit lines, convert the multiple output currents into multiple output voltages and output them; wherein, the multiple output voltages form a set of output voltages. An arithmetic circuit, connected to the multiple measurement circuits, is configured to: in response to the word line driver applying the multiple read voltages to the multiple word lines, perform arithmetic operations on multiple sets of output voltages received multiple times to obtain a first measurement signal corresponding to the set of memory cells.

7. The memory according to claim 6, wherein The arithmetic circuit includes: An analog-to-digital conversion circuit, connected to the measurement circuit, is configured to: receive multiple sets of the output voltages, convert the multiple sets of output voltages into multiple sets of digital signals and output them. A first-level arithmetic circuit, connected to the analog-to-digital conversion circuit, is configured to: based on the arithmetic operation between the equivalent conductance value and the conductance values of the memory cells in the memory cell group, perform a first-level arithmetic operation on multiple digital signals in each received set of digital signals to generate an arithmetic signal. An accumulation circuit, connected to the first-level arithmetic circuit, is configured to: sum multiple arithmetic signals received multiple times to obtain the first measurement signal.

8. The memory according to claim 6, wherein The arithmetic circuit includes: A first-level arithmetic circuit, connected to the multiple measurement circuits, is configured to: based on the arithmetic operation between the equivalent conductance value and the conductance values of the memory cells in the memory cell group, perform a first-level arithmetic operation on multiple output voltages in each received set of output voltages to obtain an arithmetic result. An analog-to-digital conversion circuit, connected to the first-level arithmetic circuit, is configured to: receive the arithmetic result, convert the arithmetic result into a result digital signal and output it. An accumulation circuit, connected to the first-level arithmetic circuit, is configured to: sum multiple result digital signals received multiple times to obtain the first measurement signal.

9. The memory according to claim 1, wherein, The peripheral circuit further includes: A comparison circuit, connected to the current interface circuit, is configured to: acquire the multiple first measurement signals, compare the magnitudes of the multiple measurement signals and output a comparison result. A control logic, connected to the comparison circuit, is configured to: based on the comparison result, determine a winning set of memory cells, wherein the weight vector corresponding to the winning set of memory cells is a winning weight vector.

10. The memory according to claim 9, wherein The control logic is configured to: Determine the set of memory cells corresponding to the largest first measurement signal among the multiple first measurement signals as the winning set of memory cells.

11. The memory according to claim 9, characterized in that, The peripheral circuit is further configured to: Update at least the conductance values of the memory cells in the winning set of memory cells to a target conductance value; wherein the target conductance value is determined based on the updated winning weight vector.

12. The memory according to claim 11, wherein The peripheral circuit is configured to: Perform a programming operation or an erasing operation on the memory cells in the winning set of memory cells to update the conductance values of the memory cells to the target conductance value.

13. The memory according to claim 12, wherein The word line driver is configured to: sequentially apply a first programming voltage and a programming verification voltage to the word lines coupled to the memory cells to be programmed in the winning set of memory cells. The readout circuit is configured to: when the word line driver applies the programming verification voltage, acquire a verification current on the bit line coupled to the memory cell to be programmed, measure the verification current, and output a second measurement signal; The control logic, coupled to the readout circuit and the word line driver, is configured to: receive the second measurement signal, obtain a current value of the verification current based on the second measurement signal, and obtain an actual conductance value of the memory cell according to the voltage value of the programming verification voltage and the current value of the verification current; Compare the actual conductance value with the target conductance value. If the actual conductance value is different from the target conductance value, control the word line driver to apply a second programming voltage and the programming verification voltage to the word line.

14. An electronic device, characterized in that, Comprising: A host and a memory coupled to the host; The host is configured to: provide voltage values of a plurality of read voltages to the memory; wherein, voltage values of some of the read voltages are determined based on an input vector; The memory includes a memory cell array, and the memory cell array includes: a plurality of memory cells, the plurality of memory cells are organized into a plurality of memory cell sets, and the conductance value of the memory cells in one memory cell set is determined based on one weight vector; the memory is configured to: perform a read operation on the plurality of memory cells in each memory cell set based on the plurality of read voltages, and obtain a first measurement signal corresponding to each memory cell set among the plurality of memory cell sets; wherein, different first measurement signals are used to characterize different distances between the weight vector and the input vector.

15. The electronic device according to claim 14, wherein The memory includes the memory according to any one of claims 1 to 13; The memory further includes: A plurality of word lines and a plurality of bit lines, coupled to the plurality of memory cells; A peripheral circuit, including: a word line driver coupled to the plurality of word lines and a readout circuit coupled to the plurality of bit lines; wherein, during the execution of the read operation: The word line driver is configured to: apply the plurality of read voltages to the plurality of word lines coupled to each memory cell set respectively; The readout circuit is configured to: acquire a plurality of output currents on the bit lines coupled to each memory cell set among the plurality of memory cell sets, perform operations and measurements on the plurality of corresponding output currents in each of the plurality of memory cell sets, and obtain a first measurement signal for each of the plurality of memory cell sets.

16. The electronic device according to claim 14, characterized in that, The weight vector includes M elements; The memory cell set includes M + 1 memory cell groups, where M is a positive integer; wherein, there is a first mapping relationship between the equivalent conductance value of the i-th memory cell group and the value of the i-th element of the weight vector, and i is any one of 1 to M; there is a second mapping relationship between the equivalent conductance value of the (M + 1)-th memory cell group and the value of a function formed by the M elements, and the equivalent conductance value of the memory cell group is an operation value of the conductance values of the memory cells in the memory cell group; The host is configured to: provide the conductance values of the memory cells in the M + 1 memory cell groups to the memory.

17. The electronic device according to claim 16, wherein The first mapping relationship and the second mapping relationship are stored in the host; The host is configured to map the values of the M elements of the weight vector to the conductance values of the storage units in M + 1 groups of storage units based on the first mapping relationship and the second mapping relationship.

18. The electronic device according to claim 14, wherein The input vector includes M elements; The host is configured to provide voltage values of M + 1 read voltages to the memory; wherein, there is a third mapping relationship between the voltage value of the i-th read voltage and the value of the i-th element of the input vector, where i is any positive integer from 1 to M; there is a fourth mapping relationship between the voltage value of the (M + 1)-th read voltage and the preset coefficient of the function formed by the M elements of the weight vector.

19. The electronic device according to claim 18, wherein The third mapping relationship and the fourth mapping relationship are stored in the host; The host is configured to map the values of the 1st to M-th elements of the input vector to the voltage values of the 1st to M-th read voltages based on the third mapping relationship; Map the preset coefficient to the voltage value of the (M + 1)-th read voltage based on the fourth mapping relationship.

20. The electronic device according to claim 14, wherein The memory is further configured to compare the magnitudes of the multiple first measurement signals and determine a winning set of storage units; The host is further configured to determine a winning weight vector based on the winning set of storage units.

21. The electronic device according to claim 20, wherein The host is further configured to at least update the winning weight vector; and, Based on the updated winning weight vector, determine the target conductance values of the storage units in the winning set of storage units and provide them to the memory; The memory is further configured to update the conductance values of the storage units in the winning set of storage units to the target conductance values.

22. The electronic device according to claim 21, wherein The host is configured to update the winning weight vector according to a domain function.

23. A method for operating a memory, characterized in that, The memory includes a storage cell array, and the storage cell array includes: a plurality of storage units, and the plurality of storage units are organized into a plurality of groups of storage units. The conductance values of the storage units in one group of storage units are determined based on one weight vector; The operation method includes: Applying a plurality of read voltages to the plurality of word lines coupled to each group of storage units respectively; wherein, the voltage values of some of the plurality of read voltages are determined based on an input vector; Obtaining a plurality of output currents of the bit lines coupled to each group of storage units in the plurality of groups of storage units, performing operations and measurements on the plurality of output currents of each in the plurality of groups of storage units, and obtaining a first measurement signal of each in the plurality of groups of storage units; wherein, different first measurement signals are used to represent different distances between the weight vector and the input vector.

24. The method for operating a memory according to claim 23, wherein The weight vector includes M elements, the group of storage units includes M + 1 groups of storage units, and M is a positive integer; wherein, the conductance value of the storage units in the i-th group of storage units is determined based on the value of the i-th element of the weight vector, and i is a positive integer from 1 to M; the conductance value of the storage units in the (M + 1)-th group of storage units is determined based on the value of the function formed by the M elements of the weight vector; Applying a plurality of read voltages to a plurality of word lines coupled to each of the sets of memory cells respectively includes: Applying the 1st to the (M + 1)th read voltages to a plurality of word lines coupled to the 1st to the (M + 1)th memory cell groups in each of the sets of memory cells; wherein, the voltage values of the 1st to the Mth read voltages are determined based on the values of the 1st to the Mth elements of the input vector, and the (M + 1)th read voltage is determined based on a preset coefficient of a function formed by M elements of the weight vector.

25. The method for operating a memory according to claim 24, wherein, A plurality of memory cells in each of the sets of memory cells are organized into a plurality of memory strings, and each of the memory strings includes (M + 1) memory cells connected in series; wherein, a plurality of the memory cells located in different memory strings and coupled to the same word line form a memory cell group, and the ith memory cell groups of different sets of memory cells are commonly coupled to the ith word line; the plurality of sets of memory cells are coupled to (M + 1) word lines; Applying the 1st to the (M + 1)th read voltages to a plurality of word lines coupled to the 1st to the (M + 1)th memory cell groups in each of the sets of memory cells includes: Applying the 1st to the (M + 1)th read voltages to the 1st to the (M + 1)th word lines in sequence.

26. The method for operating a memory according to claim 25, wherein, Obtaining a first measurement signal of any one of the sets of memory cells among the plurality of sets of memory cells includes: In response to applying a read voltage to any one of the (M + 1) word lines, acquiring a plurality of output currents of a plurality of bit lines coupled to the same set of memory cells, and converting the plurality of output currents into a plurality of digital signals; wherein, the plurality of digital signals form a set of digital signals; In response to applying corresponding read voltages to the (M + 1) word lines, performing an operation on multiple sets of digital signals received multiple times to obtain the first measurement signal corresponding to the set of memory cells.

27. The method for operating a memory according to claim 26, characterized in that, Converting the plurality of output currents into a plurality of digital signals includes: Converting the plurality of output currents into a plurality of output voltages; Converting the plurality of output voltages into a plurality of digital signals.

28. The method for operating a memory according to claim 26, characterized in that, In the set of memory cells, there is a first mapping relationship between the equivalent conductance value of the ith memory cell group and the value of the ith element of the weight vector, where i is any positive integer from 1 to M; there is a second mapping relationship between the equivalent conductance value of the (M + 1)th memory cell group and the value of the function formed by the M elements, and the equivalent conductance value of the memory cell group is the operation value of the conductance values of the memory cells in the memory cell group; Performing an operation on multiple sets of digital signals received multiple times to obtain the first measurement signal corresponding to the set of memory cells includes: Performing an operation on the plurality of digital signals in each received set of digital signals according to the operation between the equivalent conductance value and the conductance value of the memory cells in the memory cell group to generate an operation signal; Summing the multiple operation signals received multiple times to obtain the first measurement signal.

29. The method for operating a memory according to claim 23, characterized in that, The operation method further includes: Comparing the magnitudes of the plurality of first measurement signals to determine a winning set of memory cells; wherein, the weight vector corresponding to the winning set of memory cells is the winning weight vector.

30. The method for operating a memory according to claim 29, wherein, Comparing the magnitudes of the plurality of first measurement signals to determine a winning set of memory cells includes: Determine the set of memory cells corresponding to the largest first measurement signal among the multiple first measurement signals as the winning set of memory cells.

31. The method for operating a memory according to claim 29, wherein The operation method further includes: Updating at least the conductance values of the memory cells in the winning set of memory cells to a target conductance value; wherein the target conductance value is determined based on the updated winning weight vector.

32. The method for operating a memory according to claim 31, wherein, The step of updating at least the conductance values of the memory cells in the winning set of memory cells to a target conductance value includes: Performing a programming operation or an erasing operation on the memory cells in the winning set of memory cells to update the conductance values of the memory cells to the target conductance value.

33. The method for operating a memory according to claim 32, characterized in that, The step of performing a programming operation on the memory cells in the winning set of memory cells includes: Successively applying a first programming voltage and a programming verification voltage to the word lines coupled to the memory cells to be programmed in the winning set of memory cells; When the programming verification voltage is applied to the word line, obtaining a verification current on the bit line coupled to the memory cell to be programmed and measuring the current value of the verification current; Obtaining the actual conductance value of the memory cell according to the voltage value of the programming verification and the current value of the verification current; Comparing the actual conductance value with the target conductance value, and if the actual conductance value is different from the target conductance value, applying a second programming voltage and the programming verification voltage to the word line.

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