Verification test method and device for UFS command and medium

Abstract

The invention discloses a verification test method for a UFS command, and the method comprises the following steps: 1) dynamically generating a UFS command which is an operation command set for managing UFS equipment; 2) the sending end adds a CRC check flag bit to the UFS command; (3) a predefined CRC error is injected into the UFS command; 4) setting clock frequency, command response time, data transmission delay parameters and injection error frequency, and sending a UFS command by the sending end; (5) the UFS equipment receives UFS commands with error CRC values, after the commands are received, CRC verification is carried out, and the verification result is that when it is detected that CRC verification fails, error information is recorded; or the report is overtime; 6, the number of test cycles is set, and the error detection capacity of the UFS equipment is analyzed according to the CRC value comparison result and the overtime events. The UFS equipment verification method based on CRC verification is provided, and the data integrity and reliability of the UFS equipment are comprehensively verified.

Description

Technical Field

[0001] The present invention relates to semiconductor memory technologies, and in particular, to a verification test method, device, and medium for UFS commands. Background Art

[0002] In a computer storage system, the integrity of data transmission and storage is of crucial importance. As a widely used error detection method, CRC check can effectively detect bit errors during data transmission. UFS (Universal Flash Storage) devices, as high-performance storage devices, require a reliable error detection and correction mechanism during the process of command and data transmission. In the prior art, CRC check has been widely applied to various communication protocols and storage devices, such as Modbus, RTU, ASCII mode, etc.

[0003] The test methods for UFS devices are mainly specified by protocols of standardization organizations such as JEDEC, covering multiple aspects such as protocol consistency, performance, physical layer, and functional tests. These test methods ensure the high performance and interoperability of UFS devices. However, due to compatibility issues of the hardware or software environment and limitations of test tools, the test methods for UFS devices specified by relevant standard protocols may lead to inaccurate test results. The present invention proposes a misinjection and verification test method based on CRC check. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a verification test method, device, and medium for UFS commands aiming at the defects in the prior art.

[0005] The technical solution adopted by the present invention to solve its technical problem is: a verification test method for UFS commands, including the following steps: 1) Dynamically generate UFS commands, where the UFS commands are an operation command set for managing UFS devices; 2) The sending end adds a CRC check flag bit to the UFS commands; 2.1) Obtain the version of the UFS device; 2.2) Adopt a standard CRC-16 or CRC-32 algorithm to generate a check code according to the UFS protocol requirements of the obtained version of the UFS device; 3) Inject predefined CRC errors into the UFS commands; Among them, the ways of injecting errors include: Inject byte flip errors, for example, flip the 0xAA byte to 0x55 to simulate byte-level errors during data transmission; Timing perturbation: Modify specific bytes of the UFS commands to simulate CRC errors; Modify certain bits of the CRC value to generate an incorrect CRC value; 4) Set the clock frequency, command response time, data transmission delay parameters, and the frequency of injecting errors, and the sender sends UFS commands; 5) The UFS device as the receiver receives the UFS commands with incorrect CRC values. After the receiver receives these commands, it performs CRC verification. The verification result is: CRC verification failure is detected, and the error information is recorded; or a timeout is reported; 6) Set the number of test loops, and analyze the error detection ability of the UFS device according to the CRC value verification result.

[0006] According to the above solution, in step 2.2), the parallel CRC verification algorithm is implemented using FPGA, specifically as follows: 2.2.1) Use a linear feedback shift register LFSR to generate a pseudo-random sequence; 2.2.2) Perform an exclusive OR operation on the input data and the polynomial corresponding to the version of the UFS device, and gradually update the state of the LFSR; 2.2.3) The obtained LFSR state is the CRC verification code.

[0007] According to the above solution, in step 3), an FPGA is used to generate UFS commands with CRC errors: After the FPGA generates the CRC value, it records the position of the CRC field, modifies certain bits of the CRC value, thereby generating an incorrect CRC value.

[0008] According to the above solution, in step 2.2), the calculation process of the CRC verification code is as follows: Initialize the CRC register to FFFFh; Perform an exclusive OR operation on the first 8-bit byte of the UFS command and the low byte of the CRC register, and store the result in the CRC register; Process the subsequent bytes of the UFS command according to the above steps until all bytes are processed; The finally obtained CRC register value is used as the CRC verification code.

[0009] According to the above solution, in step 3), simulate CRC errors by modifying specific bytes of the UFS command.

[0010] According to the above solution, in step 3), intercept UFS commands at the Linux driver layer and dynamically modify the CRC field.

[0011] The present invention also provides an electronic device, including: One or more processors; And A storage device for storing one or more programs, wherein, when the one or more programs are executed by the one or more processors, the one or more processors are caused to execute the method according to any one of the above solutions.

[0012] The present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method according to any one of the above solutions is implemented.

[0013] The beneficial effects produced by the present invention are: 1. The present invention provides a verification method for a UFS device based on CRC check; 2. By simulating a variety of error injection scenarios, the present invention comprehensively verifies the data integrity and reliability of the UFS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention will be further described below in conjunction with the drawings and embodiments. In the drawings: Figure 1 is a flowchart of the method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0016] As Figure 1 shown, a verification test method for UFS commands includes the following steps: 1) Dynamically generate UFS commands, where the UFS commands are an operation command set for managing UFS devices; 2) The sending end adds a CRC check flag bit to the UFS commands; 2.1) Obtain the version of the UFS device; 2.2) Adopt a standard CRC-16 or CRC-32 algorithm to generate a check code according to the UFS protocol requirements for obtaining the version of the UFS device; 3) Inject predefined CRC errors into the UFS commands; Among them, the ways of injecting errors include: Inject byte flip errors, for example, flipping the 0xAA byte to 0x55 to simulate byte-level errors in data transmission; Timing perturbation: Modify specific bytes of the UFS commands to simulate CRC errors; Modify some bits of the CRC value to generate an incorrect CRC value; 4) Set the clock frequency, command response time, data transmission delay parameters, and the frequency of injecting errors, and the sender sends UFS commands; 5) The UFS device (receiver) receives UFS commands with incorrect CRC values. After receiving these commands, the receiver performs CRC verification. The verification result is: CRC verification failure is detected, and the error information is recorded; or a timeout is reported; 6) Set the number of test loops, and analyze the error detection ability of the UFS device based on the CRC value comparison result and timeout events.

[0017] Embodiment 1: CRC verification test based on the UART interface; A verification test method for UFS commands includes the following steps: A) Dynamically generate UFS commands; B) In UART communication, send UFS commands with CRC check codes; In UART communication, the sender needs to append a CRC check code to the UFS command. The CRC check code is usually calculated by the sender and appended to the command; After receiving the command, the receiver recalculates the CRC value and compares it with the received CRC value.

[0018] The calculation process of the CRC check code is as follows: Initialize the CRC register to FFFFh.

[0019] Perform an exclusive OR operation on the first 8-bit byte of the command message and the low byte of the CRC register, and store the result in the CRC register.

[0020] Process the subsequent bytes according to the above steps until all bytes are processed. The finally obtained CRC value is the check code.

[0021] C) Modify the data packet in UART communication through the error simulation module: When using the UART communication interface, the error simulation module modifies specific bytes in the data packet to inject CRC errors. For example, a certain byte in the data packet can be changed from 0x01 to 0x02, thereby changing its CRC value.

[0022] D) Set the clock frequency, command response time, data transmission delay parameters, and the frequency of injecting errors, and the sender sends UFS commands; E) The modified data packet will trigger CRC verification failure at the receiver, thereby verifying the error detection ability of the UFS device.

[0023] F) Verify the error detection ability of the UFS device: After the receiving end receives a data packet with an incorrect CRC value, it will detect a CRC check failure and record the error information. In this way, the error detection ability of the UFS device in UART communication can be evaluated.

[0024] Embodiment 2: Parallel CRC check test based on FPGA; A verification test method for UFS commands, comprising the following steps: a) Dynamically generate UFS commands; b) Add a CRC check flag bit to the UFS command based on FPGA; b1) Obtain the version of the UFS device; b2) Implement a parallel CRC check algorithm using FPGA: FPGA can implement a parallel CRC check algorithm through hardware, significantly improving the test efficiency. The parallel CRC check utilizes the parallel processing ability of FPGA and can complete the CRC calculation of multiple bytes within each clock cycle.

[0025] The CRC check code is generated as follows: b2.1) Generate a pseudo-random sequence using a linear feedback shift register LFSR; b2.2) Perform an exclusive OR operation on the input data and the polynomial corresponding to the version of the UFS device, and gradually update the state of the LFSR; b2.3) The finally obtained state of the LFSR is the CRC check code.

[0026] c) Generate a UFS command with a CRC error through FPGA: FPGA can not only generate the correct CRC value, but also deliberately introduce a CRC error through hardware logic. For example, certain bits can be modified during the process of generating the CRC value to generate an incorrect CRC value.

[0027] This error injection method can simulate the CRC errors that may occur in actual communication, thereby verifying the error detection ability of the UFS device in high-speed data transmission.

[0028] d) Set the clock frequency, command response time, data transmission delay parameters, and the frequency of injecting errors, and the sending end sends UFS commands; e) The receiving end verifies the error detection ability of the UFS device in high-speed data transmission: The UFS command with an incorrect CRC value generated by FPGA will be sent to the UFS device. The UFS device as the receiving end receives the UFS command with an incorrect CRC value. After the receiving end receives these commands, it will detect a CRC check failure and record the error information.

[0029] f) Set the number of test loops, and analyze the error detection ability of the UFS device according to the CRC value verification result; After the receiving end receives a data packet with an incorrect CRC value, it will detect a CRC check failure, record the error information, or report a timeout. In this way, the error detection ability and robustness of the UFS device in high-speed data transmission can be evaluated.

[0030] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations shall fall within the protection scope of the appended claims of the present invention.

Claims

1. A verification test method for UFS commands, characterized in that, It includes the following steps: 1) Dynamically generate UFS commands, where the UFS commands are an operation command set for managing UFS devices; 2) The sending end adds a CRC check flag bit to the UFS commands; 2.1) Obtain the version of the UFS device; 2.2) Generate a check code according to the UFS protocol requirements for obtaining the version of the UFS device; 3) Inject predefined CRC errors into the UFS commands; Among them, the way of injecting errors uses the following methods: Inject byte flip errors to simulate byte-level errors in data transmission; Timing perturbation: Modify specific bytes of the UFS commands to simulate CRC errors; Modify one or several bits of the CRC value to generate an incorrect CRC value; 4) Set the clock frequency, command response time, data transmission delay parameters, and the frequency of injecting errors, and the sending end sends the UFS commands; 5) The UFS device receives the UFS commands with incorrect CRC values. After receiving these commands, it performs CRC checks, and the check results are: CRC check failure is detected and error information is recorded; or a timeout is reported; 6) Set the number of test loops, and analyze the error detection ability of the UFS device according to the CRC value comparison results and timeout events.

2. The verification test method for UFS commands according to claim 1, wherein In step 2.2), the generation of the CRC check code is implemented by using an FPGA, specifically as follows: 2.2.1) Use a linear feedback shift register (LFSR) to generate a pseudo-random sequence; 2.2.2) Perform an exclusive OR operation on the input data and the polynomial corresponding to the version of the UFS device to gradually update the state of the LFSR; 2.2.3) The finally obtained state of the LFSR is the CRC check code.

3. The verification test method for UFS commands according to claim 1, wherein In step 3), the FPGA generates UFS commands with CRC errors: After the FPGA generates the CRC value, it records the position of the CRC field and modifies some bits of the CRC value to generate an incorrect CRC value.

4. The verification test method for UFS commands according to claim 1, wherein In step 2.2), the calculation process of the CRC check code is as follows: Initialize the CRC register to FFFFh; Perform an exclusive OR operation on the first 8-bit byte of the UFS command and the low byte of the CRC register, and store the result in the CRC register; Process the subsequent bytes of the UFS command according to the above steps until all bytes are processed; Use the finally obtained value of the CRC register as the CRC check code.

5. The verification test method for UFS commands according to claim 1, characterized in that, In step 3), simulate CRC errors by modifying specific bytes of the UFS commands.

6. The verification test method for UFS commands according to claim 1, wherein In step 3), intercept the UFS commands at the Linux driver layer and dynamically modify the CRC field.

7. An electronic device, characterized in that it includes: one or more processors; and a storage device for storing one or more programs, wherein, when the one or more programs are executed by the one or more processors, the one or more processors are caused to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program, when executed by a processor, implements the method according to any one of claims 1 to 6.

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