Integrated circuit chip test system based on AI algorithm

Abstract

The invention discloses an integrated circuit chip test system based on an AI algorithm, and relates to the technical field of integrated circuit chip testing, the integrated circuit chip test system comprises a chip test platform, the chip test platform is in communication connection with the following modules: a data acquisition module, which is used for collecting historical test data from existing integrated circuit chip test equipment, and sending the collected historical test data to the chip test platform; carrying out preprocessing and integration on the chip test data set to obtain a chip test data set; and the model training optimization module is used for analyzing the chip test data set, learning the relationship between the chip performance and the test vector, and training a test vector AI optimization model. According to the method, by analyzing historical test data and automatically generating the optimized test vector, a redundant item-by-item test process in a traditional test is avoided, key test nodes are accurately positioned through the test vector AI optimization model, and unnecessary test steps are reduced, so that the test time is remarkably shortened, and the test efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit chip testing, and particularly relates to an integrated circuit chip testing system based on an AI algorithm. Background Art

[0002] With the continuous development of semiconductor manufacturing processes towards smaller line widths and higher integration levels, the number of transistors inside chips has increased exponentially, and the structure has become increasingly complex. This poses higher requirements for chip testing. Moreover, the chip market is highly competitive, and product updates are rapid. In order to gain an advantage in the market, it is necessary to quickly introduce high-quality and high-performance chip products. As an important link in the chip production process, the testing system's testing efficiency and accuracy directly affect the chip's time to market and product quality. An efficient testing system can shorten the chip production cycle, reduce production costs, and improve the enterprise's market competitiveness.

[0003] In the prior art, the testing of integrated circuit chips usually adopts fixed test vectors and test processes, and all chips are tested item by item. For chips produced on a large scale, the testing time is relatively long, which will lead to an extended production cycle and increased costs. Therefore, how to use machine learning algorithms to analyze historical test data, automatically generate optimized test vectors, reduce redundant testing, and improve testing efficiency is the problem to be solved by the present invention. For this purpose, an integrated circuit chip testing system based on an AI algorithm is proposed. Summary of the Invention

[0004] The purpose of the present invention is to provide an integrated circuit chip testing system based on an AI algorithm to solve the problems raised in the above background art.

[0005] To solve the above technical problems, the technical solution adopted by the present invention is: An integrated circuit chip testing system based on an AI algorithm, including a chip testing platform, which is communicatively connected to the following modules, where: A data acquisition module, which is used to collect historical test data from existing integrated circuit chip testing equipment, preprocess it, and integrate it to obtain a chip test data set; A model training and optimization module, which is used to analyze the chip test data set, learn the relationship between chip performance and test vectors, and train a test vector AI optimization model; A test vector generation module, which is used to automatically generate an initial test vector according to the trained test vector AI optimization model, customize the test vector according to the test characteristics of the chip, avoid repeated testing, and ensure the comprehensiveness of the test; A test vector evaluation module, which is used to evaluate the generated test vector, analyze its effect in chip testing, and optimize the initial test vector; The test execution feedback module is used to apply the optimized test vectors to test the integrated circuit chip, and further optimize the test vector AI optimization model and test vectors based on the test execution results.

[0006] A further improvement of the technical solution of the present invention is that the data acquisition module specifically includes: Establish a connection with the existing integrated circuit chip test equipment through a standard communication interface (TCP / IP, GPIB, USB, etc.), automatically scan the historical test data files stored in the equipment, and encapsulate the collected original data of the historical test data files in a unified format and temporarily store them in a temporary buffer; Preprocess the raw data in the buffer, identify and remove missing values, outliers and duplicate records, and then convert the preprocessed data into a unified JSON format to generate an intermediate data set to ensure data standardization and consistency; The intermediate data sets are classified and integrated according to the dimensions of integrated circuit chip models and test batches, and a data association index is established. A distributed storage architecture is used to partition and store the integrated data according to feature dimensions, and the data source, processing process and version information are recorded to form a chip test data set that contains a complete test context.

[0007] A further improvement of the technical solution of the present invention is that: the model training optimization module includes a feature analysis unit and a model training optimization unit; The feature analysis unit is used to analyze the historical test data in the chip test data set, extract the test features related to the test vector optimization, and obtain the test feature sequence table; The model training optimization unit is used to combine the test feature sequence table and historical test data, use the support vector machine model as the basic architecture, learn the relationship between chip performance and test vectors, and train the test vector AI optimization model.

[0008] A further improvement of the technical solution of the present invention is that the feature analysis unit specifically includes: Perform structured analysis on chip test data sets to identify potential feature domains contained in the data. By analyzing the semantic labels, data types, and associations of data fields, we divide the core feature categories directly related to test vector optimization, including electrical performance parameters, functional test results, process parameters, and test environment variables. Combined with the domain knowledge base of integrated circuit chip testing, we establish a mapping relationship between features and test vector optimization goals, clarify the potential role of each feature in test efficiency, coverage, and cost optimization, and form a list of features to be extracted. According to the list of features to be extracted, specific test feature categories are extracted from historical test data, including test vector coverage rate, fault detection rate, test time, test vector length, efficiency of improving fault coverage rate, and test redundancy, and multi-dimensional correlation analysis is carried out to quantify the correlation strength between test features and the effectiveness of test vectors, generating a structured test feature sequence table containing feature names and definitions.

[0009] A further improvement of the technical solution of the present invention lies in that: the model training and optimization unit specifically includes: Integrate the test feature sequence table with historical test data to ensure data consistency and integrity, and match the extracted test features with the corresponding records in the historical data through the feature name and the unique identifier (chip batch number) of the data record, forming a unified training data set, and divide the training data set into a training set, a validation set, and a test set; With a support vector machine (SVM) as the core architecture, construct a test vector AI optimization model, select a radial basis function (RBF) to process non-linear feature relationships, set the search range of the regularization parameter C and the candidate values of the kernel function parameter γ, input the training set into the support vector machine model, use 5-fold cross-validation to evaluate the generalization ability of the model, calculate the average accuracy and standard deviation, iteratively adjust C and γ on the validation set based on grid search, select the parameter combination that minimizes the cross-validation error, output the trained support vector machine model, and record the optimal hyperparameters and performance indicators during the training process; Execute model prediction on the test set, calculate the deviation between the prediction result of the support vector machine model and the actual label, generate an evaluation report, analyze the contribution degree of each test feature to the model output based on SHAP values, identify key features and redundant features, adjust the model architecture according to the evaluation results, and retrain the model until the performance converges (the test set accuracy is increased to 94.1%), and finally generate a test vector AI optimization model with high generalization ability, and synchronously output the model version number, training log, and deployment interface document.

[0010] A further improvement of the technical solution of the present invention lies in that: the test vector generation module specifically includes: Receive the test requirement document of the current chip, including chip model, functional characteristics, performance indicators, and specific test objectives, parse the test requirement document of the current chip, extract key test objectives and constraint conditions, and based on the test feature sequence table, extract the test features of the current chip from the chip design document, process parameter library, and historical test data, and map the test requirements and the test features of the chip into a structured input vector to ensure that the input data is compatible with the trained test vector AI optimization model; Input the constructed input vector into the trained test vector AI optimization model to generate an initial test vector set. Based on the feature importance ranking (SHAP value analysis result) output by the model, customize and optimize the initial vector, including coverage enhancement, redundancy elimination, and resource balancing, and then output a customized test vector set, which includes vector sequences, target coverage nodes, and expected resource consumption, to form a preliminary test plan.

[0011] A further improvement of the technical solution of the present invention lies in that: the test vector evaluation module specifically includes: Deploy the test vector set to the simulation platform (Synopsys VCS), execute the full-process test and collect metric data, including logic coverage rate, fault detection rate, total test time, and resource occupancy, and identify redundant test patterns with duplicate stimuli or redundant timing constraints through vector similarity calculation (cosine similarity) and execution path comparison, quantify the redundancy ratio, and then compare the collected metrics with the constraint conditions in the test requirements document, generate a compliance report, mark the non-compliant items, output an evaluation result list, and clarify the performance shortcoming and requirement deviation of the current test vector; Based on the evaluation results, locate the key problem module and the root cause of redundancy, analyze the performance of the test vector in reducing test time, improving test coverage, and reducing test cost, and formulate optimization strategies for the deficiencies, including coverage improvement, time compression, resource optimization, and vector dynamic adjustment. Generate an optimized test vector set according to the optimization strategy, update the vector sequence, delete redundant items, and reallocate resources to generate an iterative version vector file, and then output an optimization strategy document and the adjusted test vector set to clarify the optimization direction and expected improvement goals; Put the adjusted test vector set back into the simulation environment, re-collect the metric data of logic coverage rate, fault detection rate, total test time, and resource occupancy, compare the performance changes before and after optimization, and check whether the optimization introduces new problems. If so, trace back and adjust the optimization strategy, and set the condition that the performance improvement rate in two consecutive iterations is <1% and there are no new problems as the convergence condition. If it is satisfied, terminate the optimization; otherwise, continue to iterate until the test vector reaches the optimal balance in terms of time, coverage, and cost, and then output the final optimized test vector set, evaluation report, and deployment guide to ensure that the test vector is efficient, accurate, and compliant with the constraint conditions in actual applications.

[0012] A further improvement of the technical solution of the present invention lies in that: the test execution feedback module includes a test execution unit and a feedback update unit; Among them, the test execution unit is used to apply the optimized test vector to the actual integrated circuit chip test process, execute the test task, and record the test results. By using the optimized test vector, the test efficiency is improved, the test time is shortened, and the test cost is reduced; The feedback update unit is used to collect feedback information according to the results of test execution, and further optimize the test vector AI optimization model and test vectors to adapt to the changes in chip production processes and new test requirements.

[0013] A further improvement of the technical solution of the present invention lies in that: the test execution unit specifically includes: According to the chip test requirement document and deployment guide, configure the parameters of the automated test equipment, including clock frequency, power supply voltage, and signal level, to ensure consistency with the test vector generation environment. Load the optimized test vector set (iterative version vector file) into the test equipment, parse the vector sequence, target coverage nodes, and resource allocation parameters, generate an executable test instruction stream, and verify the integrity of vector loading through the equipment self-check function, check the test resource status, and ensure no hardware faults; Start the test task according to the optimized vector execution order, monitor the test progress in real time, record the execution time and resource occupancy of each vector, capture the chip output response signal, compare it bit by bit with the expected result (the target value generated based on the test vector), record the pass / fail test results and fault location information. If a test interruption is detected, trigger the rollback mechanism, save the current test status, and restart the failed vector to ensure test continuity. Synchronously record the timestamp and error code of the abnormal event; Compare the test data before and after optimization, calculate the test time compression rate and the improvement amplitude of resource utilization rate, verify whether the optimization effect meets the expected goal, integrate the test results including the pass rate and fault distribution map with the log file including execution time and resource consumption into a standardized report, classify and store it in the database according to chip batches and test types, and then generate a test efficiency analysis report, mark the unqualified test items, and feedback them to the test vector generation module to drive the next round of optimization iteration, forming a continuous improvement closed loop.

[0014] A further improvement of the technical solution of the present invention lies in that: the feedback update unit specifically includes: Collect various types of feedback information generated during the test execution process, including test results, fault location information, test time, resource occupancy, and abnormal event records, and organize and classify them. At the same time, record the new features and potential defects of the chip found during the test process, as well as the changes in the test environment. Store the feedback information in the database by category and establish a field index; Based on the collected feedback information, analyze the test vector AI optimization model, analyze the adaptability and accuracy of the model in the current test environment, combine the test results, identify the deficiencies of the model in predicting the effectiveness of test vectors, and at the same time, analyze the performance of test vectors in actual tests to find the optimization directions; According to the results of the optimization analysis, update the test vector AI optimization model, adjust the model parameters or improve the model architecture to adapt to the changes in the chip production process and new test requirements. At the same time, adjust the test vectors according to the optimization strategy to generate a new set of test vectors. Apply the updated model and vectors to new test tasks, continuously collect feedback information, compare the performance metrics before and after iteration, and verify the optimization effect. If the standard is not met, trace back and adjust to form a closed-loop mechanism of "collection - analysis - optimization - verification".

[0015] Due to the adoption of the above technical solution, the technical progress achieved by the present invention compared with the prior art is as follows: The present invention provides an integrated circuit chip testing system based on an AI algorithm. By analyzing historical test data, it automatically generates optimized test vectors, avoiding the redundant item-by-item test process in traditional testing. It accurately locates key test nodes through the test vector AI optimization model, reduces unnecessary test steps, thereby significantly shortening the test time and improving the test efficiency.

[0016] The present invention provides an integrated circuit chip testing system based on an AI algorithm. By optimizing the test vectors, it reduces the resource consumption during the testing process, including test time, labor costs, and the wear and tear of test equipment. At the same time, by reducing redundant tests, it avoids unnecessary consumption of test materials, further reducing the test cost. And by being able to learn the relationship between chip performance and test vectors, continuously optimizing the test vectors, improving the comprehensiveness and accuracy of testing, being able to identify and cover potential defects in the chip, reducing the risks of missed tests and mismeasurements, and helping to ensure the quality of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic diagram of the working process of the present invention; Figure 2 It is a schematic diagram of the system function modules of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0020] Embodiment 1, as Figure 1 , Figure 2 shown, the present invention provides an integrated circuit chip testing system based on an AI algorithm, including a chip testing platform, which is communicatively connected to the following modules, where: A data acquisition module, which is used to collect historical test data from existing integrated circuit chip testing equipment, preprocess it, integrate it to obtain a chip test data set, establish a connection with the existing integrated circuit chip testing equipment through a standard communication interface (TCP / IP, GPIB, USB, etc.), automatically scan the historical test data files stored in the equipment, covering electrical parameters, functional test results, test vector execution conditions of the integrated circuit chip, as well as information such as the batch and process parameters of the chip, and encapsulate the original data of the collected historical test data files in a unified format and temporarily store it in a temporary buffer. Preprocess the raw data in the buffer, identify and remove missing values, outliers, and duplicate records. Through data standardization processing, unify the parameter units and precisions output by different devices, eliminate the dimension difference. For unstructured data, use natural language processing technology to extract key features and convert them into structured fields, and correct or mark logically contradictory data. Then, convert the preprocessed data into a unified JSON format to generate an intermediate data set to ensure data standardization and consistency. Classify and integrate the intermediate data set according to the dimensions of the integrated circuit chip model and test batch, establish a data association index, and use a distributed storage architecture to store the integrated data in partitions according to feature dimensions, record the data source, processing process, and version information, and form a chip test data set containing a complete test context; A model training and optimization module, which is used to analyze the chip test data set, learn the relationship between chip performance and test vectors, and train a test vector AI optimization model. The model training and optimization module includes a feature analysis unit and a model training and optimization unit; Among them, the feature analysis unit is used to analyze the historical test data in the chip test dataset, extract test features related to test vector optimization, obtain a test feature sequence list, perform a structured analysis on the chip test dataset, identify potential feature domains contained in the data, and divide out the core feature categories directly related to test vector optimization by parsing the semantic tags, data types, and association relationships of data fields, including electrical performance parameters, functional test results, process parameters, and test environment variables. Combining with the domain knowledge base of integrated circuit chip testing, establish a mapping relationship between features and test vector optimization objectives, clarify the potential roles of each feature in test efficiency, coverage, and cost optimization, form a list of features to be extracted, and extract specific test feature categories from the historical test data according to the list of features to be extracted, including test vector coverage rate, fault detection rate, test time, test vector length, fault coverage rate improvement efficiency, and test redundancy, and conduct multi-dimensional correlation analysis to quantify the correlation strength between test features and test vector effectiveness, generating a structured test feature sequence list containing feature names and definitions. Among them, the test vector coverage rate is the ratio of the number of chip logic nodes actually covered by the test vector to the total number of logic nodes. A high coverage rate indicates that the test vector can detect potential defects in the chip more comprehensively. The fault detection rate is the ratio of the number of faults detected by the test vector to the total number of actual faults in the chip, directly reflecting the sensitivity of the test vector to defects. The test time is the time required for a single test vector to be executed on the chip. Shortening the test time can reduce the test cost. The test vector length is the number of binary digits contained in the test vector. The vector length directly affects the test data storage and transmission costs. The fault coverage rate improvement efficiency is the percentage of the fault coverage rate increased per unit increase in the test vector length, quantifying the relationship between the test vector length and the fault coverage rate. The test redundancy is the ratio of the repeated detection of the same fault in the test vector. A high redundancy indicates low efficiency of the test vector; The model training optimization unit is used to combine the test feature sequence list and historical test data, take the support vector machine model as the basic architecture, learn the relationship between chip performance and test vectors, train the test vector AI optimization model, integrate the test feature sequence list and historical test data to ensure data consistency and integrity, and match the extracted test features with the corresponding records in the historical data through the feature name and the unique identifier (chip batch number) of the data record to form a unified training dataset. The training dataset is divided into a training set, a validation set, and a test set. Taking the support vector machine (SVM) as the core architecture, a test vector AI optimization model is constructed. The radial basis function (RBF) is selected to process the non-linear feature relationship. The search range of the regularization parameter C and the candidate values of the kernel function parameter γ are set. The training set is input into the support vector machine model, and 5-fold cross-validation is used to evaluate the generalization ability of the model. The average accuracy and standard deviation are calculated. Based on grid search, C and γ are iteratively adjusted on the validation set, and the parameter combination that minimizes the cross-validation error is selected. The trained support vector machine model is output, the optimal hyperparameters and the performance metrics during the training process are recorded. Model prediction is performed on the test set, the deviation between the prediction result of the support vector machine model and the actual label is calculated, and an evaluation report is generated. Based on the SHAP value, the contribution degree of each test feature to the model output is analyzed, key features and redundant features are identified, the model architecture is adjusted according to the evaluation results, and the model is retrained until the performance converges (the test set accuracy is increased to 94.1%). Finally, a test vector AI optimization model with high generalization ability is generated, and the model version number, training log, and deployment interface document are output synchronously; The test vector generation module is used to automatically generate initial test vectors according to the trained test vector AI optimization model and combine the test requirements of the current chip, customize the test vectors according to the test features of the chip, avoid repeated tests, and ensure the comprehensiveness of the tests; The test vector evaluation module is used to evaluate the generated test vectors, analyze their effects in chip testing, and optimize the initial test vectors. The optimization objectives are to reduce the test time, improve the test coverage rate, and reduce the test cost. By continuously iterating and adjusting the test vectors, the optimal result is achieved under the premise of meeting the test requirements; The test execution feedback module is used to apply the optimized test vectors to test the integrated circuit chip, and further optimize the test vector AI optimization model and test vectors according to the test execution results.

[0021] Example 2, as Figure 1 、 Figure 2 shown, based on Example 1, the present invention provides a technical solution: Preferably, the test vector generation module specifically includes: Receive the test requirement document of the current chip, including chip model, functional characteristics, performance indicators, and specific test objectives. Analyze the test requirement document of the current chip, extract the key test objectives (functional coverage threshold, defect detection priority) and constraints (upper limit of test time, resource occupancy limit). Based on the test feature sequence list, extract the test features of the current chip from the chip design document, process parameter library, and historical test data. Map the test requirements and the test features of the chip into a structured input vector to ensure compatibility between the input data and the trained test vector AI optimization model. Input the constructed input vector into the trained test vector AI optimization model to generate an initial test vector set. Based on the feature importance ranking (SHAP value analysis result) output by the model, perform customized optimization on the initial vector, including coverage enhancement, redundancy elimination, and resource balance. Among them, coverage enhancement is to preferentially allocate test resources to high-fault-sensitivity modules to improve the critical path coverage rate. Redundancy elimination is to identify and eliminate test patterns that are repeated with historical test vectors through a feature matching algorithm to avoid redundant detection. Resource balance is to dynamically adjust the vector length and complexity according to the resource constraint parameters to ensure the balance of test efficiency and cost, and then output a customized test vector set, including vector sequence, target coverage nodes, and expected resource consumption, forming a preliminary test plan; The test vector evaluation module specifically includes: Deploy the test vector set to the simulation platform (Synopsys VCS), execute the full - process test and collect metric data, including logic coverage, fault detection rate, total test time, and resource occupancy. Compare with the execution path through vector similarity calculation (cosine similarity) to identify redundant test patterns with duplicate stimuli or redundant timing constraints, quantify the redundancy ratio. Then, compare the collected metrics with the constraint conditions in the test requirements document, generate a compliance report, mark the non - compliant items, output a list of evaluation results, clarify the performance short - comings and requirement deviations of the current test vectors. Based on the evaluation results, locate the key problem modules and the root causes of redundancy, analyze the performance of the test vectors in reducing test time, improving test coverage, and reducing test costs. For the deficiencies, formulate optimization strategies, including coverage improvement, time compression, resource optimization, and vector dynamic adjustment. Among them, for uncovered nodes, add high - priority test items or adjust the vector excitation intensity, shorten the length of redundant vectors, merge low - priority test sequences or optimize the vector execution order, adjust the resource allocation parameters or switch to low - resource - consumption test modes. Generate an optimized test vector set according to the optimization strategy, update the vector sequence, delete redundant items, and re - allocate resources to generate an iterative version of the vector file. Then, output an optimization strategy document and the adjusted test vector set, clarify the optimization direction and expected improvement goals. Put the adjusted test vector set back into the simulation environment, re - collect the metric data of logic coverage, fault detection rate, total test time, and resource occupancy, compare the performance changes before and after optimization, and check whether the optimization introduces new problems. If so, backtrack and adjust the optimization strategy. Set the condition that the performance improvement rate in two consecutive iterations is <1% and there are no new problems as the convergence condition. If satisfied, terminate the optimization; otherwise, continue the iteration until the test vectors achieve an optimal balance in terms of time, coverage, and cost. Then, output the final optimized test vector set, evaluation report, and deployment guide to ensure that the test vectors are efficient, accurate, and compliant with the constraints in actual applications; The test execution feedback module includes a test execution unit and a feedback update unit; Among them, the test execution unit is used to apply the optimized test vectors to the actual integrated circuit chip testing process, execute the test tasks, and record the test results. By using the optimized test vectors, the test efficiency can be improved, the test time can be shortened, and the test cost can be reduced. According to the chip test requirement document and deployment guide, configure the parameters of the automated test equipment, including the clock frequency, power supply voltage, and signal level, to ensure consistency with the test vector generation environment. Load the optimized test vector set (iterative version vector file) into the test equipment, parse the vector sequence, target coverage nodes, and resource allocation parameters, generate an executable test instruction stream, and verify the integrity of vector loading through the device self-check function. Check the test resource status to ensure no hardware failures. Start the test tasks according to the execution order of the optimized vectors, monitor the test progress in real time, record the execution time of each vector and resource occupancy, capture the chip output response signal, compare it bit by bit with the expected result (the target value generated based on the test vectors), record the pass / fail test results and fault location information. If a test interruption is detected, trigger the rollback mechanism, save the current test status, and restart the failed vectors to ensure test continuity. Synchronously record the timestamps and error codes of abnormal events, compare the test data before and after optimization, calculate the test time compression rate and the improvement amplitude of resource utilization, and verify whether the optimization effect meets the expected goals. Integrate the test results containing the pass rate and fault distribution map with the log file containing the execution time and resource consumption into a standardized report, classify and store it in the database according to the chip batch and test type, and then generate a test efficiency analysis report, mark the unqualified test items, and feedback them to the test vector generation module to drive the next round of optimization iteration, forming a continuous improvement closed loop; A feedback update unit, which is used to collect feedback information according to the results of test execution, further optimize the test vector AI optimization model and test vectors to adapt to the changes in chip production processes and new test requirements, collect various types of feedback information generated during the test execution process, including test results, fault location information, test time, resource occupancy, and abnormal event records, and organize and classify them. At the same time, record the new features and potential defects of the chip discovered during the test process, as well as the changes in the test environment. Store the feedback information in categories in the database, establish field indexes, analyze the test vector AI optimization model based on the collected feedback information, analyze the adaptability and accuracy of the model in the current test environment, combine the test results, identify the deficiencies of the model in predicting the effectiveness of test vectors, and at the same time, analyze the performance of test vectors in actual tests to find the directions that need to be optimized. According to the results of the optimization analysis, update the test vector AI optimization model, adjust the model parameters or improve the model architecture to adapt to the changes in chip production processes and new test requirements. At the same time, adjust the test vectors according to the optimization strategy to generate a new test vector set, apply the updated model and vectors to new test tasks, continuously collect feedback information, compare the performance indicators before and after iteration, and verify the optimization effect. If the standard is not met, backtrack and adjust to form a "collection - analysis - optimization - verification" closed-loop mechanism to ensure that the test vectors and the model continuously adapt to the changes in chip production processes and the upgrade of test requirements.

[0022] As described above, it is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. An integrated circuit chip testing system based on AI algorithms, including a chip testing platform, characterized in that: The chip test platform is communicatively connected to the following modules, where: The data acquisition module is used to collect historical test data from existing integrated circuit chip test equipment, preprocess it, and integrate it to obtain a chip test data set; The model training and optimization module is used to analyze the chip test data set, learn the relationship between chip performance and test vectors, and train a test vector AI optimization model; The test vector generation module is used to automatically generate initial test vectors according to the trained test vector AI optimization model and in combination with the test requirements of the current chip; The test vector evaluation module is used to evaluate the generated test vectors, analyze their effects in chip testing, and optimize the initial test vectors; The test execution and feedback module is used to apply the optimized test vectors to test the integrated circuit chips, and further optimize the test vector AI optimization model and test vectors according to the test execution results.

2. The integrated circuit chip testing system based on the AI algorithm according to claim 1, wherein: The data acquisition module specifically includes: Establish a connection with existing integrated circuit chip test equipment through a standard communication interface, automatically scan the historical test data files stored in the equipment, and encapsulate the original data of the collected historical test data files in a unified format and temporarily store it in a temporary buffer; Preprocess the original data in the buffer, identify and remove missing values, outliers, and duplicate records, and then convert the preprocessed data into a unified JSON format to generate an intermediate data set; Classify and integrate the intermediate data set according to the dimensions of integrated circuit chip models and test batches, establish a data association index, and use a distributed storage architecture to store the integrated data in partitions according to feature dimensions, record the data sources, processing processes, and version information, and form a chip test data set containing complete test contexts.

3. The integrated circuit chip testing system based on the AI algorithm according to claim 1, characterized in that: The model training and optimization module includes a feature analysis unit and a model training and optimization unit; Among them, the feature analysis unit is used to analyze the historical test data in the chip test data set, extract test features related to test vector optimization, and obtain a test feature sequence list; The model training and optimization unit is used to combine the test feature sequence list and historical test data, and based on the support vector machine model, learn the relationship between chip performance and test vectors, and train a test vector AI optimization model.

4. An integrated circuit chip testing system based on an AI algorithm according to claim 3, characterized in that: The feature analysis unit specifically includes: Perform a structured analysis of the chip test data set, identify potential feature domains contained in the data, and divide the core feature categories directly related to test vector optimization by analyzing the semantic labels, data types, and association relationships of the data fields, including electrical performance parameters, functional test results, process parameters, and test environment variables. Combine the domain knowledge base of integrated circuit chip testing to establish a mapping relationship between features and test vector optimization objectives, clarify the potential roles of each feature in test efficiency, coverage, and cost optimization, and form a list of features to be extracted; According to the list of features to be extracted, specific test feature categories are extracted from historical test data, including test vector coverage rate, fault detection rate, test time, test vector length, fault coverage improvement efficiency, and test redundancy, and multi-dimensional correlation analysis is carried out to quantify the correlation strength between test features and the effectiveness of test vectors, generating a structured test feature sequence list containing feature names and definitions.

5. An integrated circuit chip testing system based on an AI algorithm according to claim 4, characterized in that: The model training and optimization unit specifically includes: Integrate the test feature sequence list with historical test data, and match the extracted test features with the corresponding records in the historical data through the feature name and the unique identifier of the data record to form a unified training data set, and divide the training data set into a training set, a validation set, and a test set; With the support vector machine as the core architecture, build a test vector AI optimization model, select the radial basis function to handle non-linear feature relationships, set the search range of the regularization parameter C and the candidate values of the kernel function parameter γ, input the training set into the support vector machine model, use 5-fold cross-validation to evaluate the generalization ability of the model, iteratively adjust C and γ on the validation set based on grid search, select the parameter combination that minimizes the cross-validation error, output the trained support vector machine model, and record the optimal hyperparameters and performance indicators during the training process; Execute model prediction on the test set, calculate the deviation between the prediction result of the support vector machine model and the actual label, generate an evaluation report, analyze the contribution degree of each test feature to the model output based on SHAP values, identify key features and redundant features, adjust the model architecture according to the evaluation results, and retrain the model until the performance converges, finally generating a test vector AI optimization model with high generalization ability, and synchronously outputting the model version number, training log, and deployment interface document.

6. The integrated circuit chip testing system based on the AI algorithm according to claim 3, wherein: The test vector generation module specifically includes: Receive the test requirement document of the current chip, including chip model, functional characteristics, performance indicators, and specific test objectives, parse the test requirement document of the current chip, extract key test objectives and constraint conditions, and based on the test feature sequence list, extract the test features of the current chip from the chip design document, process parameter library, and historical test data, and map the test requirements and the test features of the chip into a structured input vector; Input the constructed input vector into the trained test vector AI optimization model to generate an initial test vector set, and based on the feature importance ranking output by the model, perform customized optimization on the initial vector, including coverage enhancement, redundancy elimination, and resource balance, and then output a customized test vector set, including vector sequence, target coverage nodes, and expected resource consumption, forming a preliminary test plan.

7. An integrated circuit chip testing system based on an AI algorithm according to claim 6, characterized in that: The test vector evaluation module specifically includes: Deploy the test vector set to the simulation platform, execute the full - process test and collect metric data, including logic coverage rate, fault detection rate, total test time consumption, and resource occupancy. Identify redundant test patterns with duplicate incentives or redundant timing constraints through vector similarity calculation and execution path comparison, quantify the redundancy ratio, and then compare the collected metrics with the constraint conditions in the test requirements document to generate a compliance report, mark non - compliant items, output a list of evaluation results, and clarify the performance short - comings and requirement deviations of the current test vectors; Based on the evaluation results, locate the key problem modules and the root causes of redundancy, analyze the performance of the test vectors in reducing test time, improving test coverage, and reducing test costs. For deficiencies, formulate optimization strategies, including coverage improvement, time compression, resource optimization, and vector dynamic adjustment. Generate an optimized test vector set according to the optimization strategies, update the vector sequence, delete redundant items, and re - allocate resources to generate an iterative version of the vector file. Then output an optimization strategy document and the adjusted test vector set, clarifying the optimization direction and expected improvement goals; Put the adjusted test vector set back into the simulation environment, re - collect the metric data of logic coverage rate, fault detection rate, total test time consumption, and resource occupancy, compare the performance changes before and after optimization, and check whether the optimization introduces new problems. If so, trace back and adjust the optimization strategy. Set the condition that the performance improvement rate in two consecutive iterations is <1% and there are no new problems as the convergence condition. If satisfied, terminate the optimization; otherwise, continue the iteration until the test vectors achieve the optimal balance in terms of time, coverage, and cost. Then output the final optimized test vector set, evaluation report, and deployment guide.

8. An integrated circuit chip testing system based on an AI algorithm according to claim 7, characterized in that: The test execution feedback module includes a test execution unit and a feedback update unit; Among them, the test execution unit is used to apply the optimized test vectors to the actual integrated circuit chip test process, execute the test tasks, and record the test results; The feedback update unit is used to collect feedback information according to the test execution results, and further optimize the test vector AI optimization model and test vectors to adapt to the changes in chip production processes and new test requirements.

9. The integrated circuit chip testing system based on the AI algorithm according to claim 8, wherein: The test execution unit specifically includes: According to the chip test requirements document and deployment guide, configure the parameters of the automated test equipment, including clock frequency, power supply voltage, and signal level. Load the optimized test vector set into the test equipment, parse the vector sequence, target coverage nodes, and resource allocation parameters to generate an executable test instruction stream, and verify the integrity of vector loading through the equipment self - check function and check the test resource status; Start the test tasks according to the execution order of the optimized vectors, monitor the test progress in real - time, record the execution time and resource occupancy of each vector, capture the chip output response signals, compare them bit - by - bit with the expected results, record the pass / fail test results and fault location information. If a test interruption is detected, trigger the rollback mechanism, save the current test status, restart the failed vectors, and synchronously record the timestamps and error codes of abnormal events; Compare the test data before and after optimization, calculate the compression rate of the test time and the improvement rate of the resource utilization rate, verify whether the optimization effect meets the expected goal, integrate the test results including the pass rate and the fault distribution diagram with the log file containing the execution time and resource consumption into a standardized report, classify and store it in the database according to the chip batch and test type, and then generate a test efficiency analysis report, mark the unqualified test items, feedback them to the test vector generation module, drive the next round of optimization iteration, and form a continuous improvement closed loop.

10. An integrated circuit chip testing system based on an AI algorithm according to claim 9, characterized in that: The feedback and update unit specifically includes: Collect various feedback information generated during the test execution process, including test results, fault location information, test time, resource occupancy, and abnormal event records, and organize and classify them. At the same time, record the new chip features and potential defects found during the test, as well as the changes in the test environment, store the feedback information in the database by category, and establish field indexes; Based on the collected feedback information, analyze the test vector AI optimization model, analyze the adaptability and accuracy of the model in the current test environment, combine the test results, identify the deficiencies of the model in predicting the effectiveness of the test vector, and at the same time, analyze the performance of the test vector in the actual test to find the direction that needs to be optimized; According to the results of the optimization analysis, update the test vector AI optimization model. At the same time, adjust the test vector according to the optimization strategy, generate a new test vector set, apply the updated model and vector to the new test task, continuously collect feedback information, compare the performance indicators before and after iteration, verify the optimization effect, and if not up to standard, backtrack and adjust to form a closed-loop mechanism of "collection - analysis - optimization - verification".

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