Electronic component quality control method and system

Abstract

The invention discloses an electronic component quality control method and system, and relates to the technical field of transistor performance quality control. The quality control method for the electronic component comprises the following steps: evaluating transistor switch abnormity; switching speed delay regulation and control; and evaluating the input signal response control accuracy. Transistor switching abnormality evaluation is carried out in the transistor switching process, then whether switching speed delay optimization is carried out or not is judged based on a quantization result, if switching speed delay optimization is carried out, switching speed delay regulation and control are carried out, and if switching speed delay optimization is not carried out, input signal response control accuracy evaluation is carried out. And finally, judging whether to carry out input signal response control optimization or not based on a quantification result of the input signal response control accuracy evaluation, thereby achieving the effect of improving the response control sufficiency of the transistor on the input signal in the switching process. The problem that the switch response difference is not fully considered in the response control process of a transistor to an input signal in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor performance quality control, and particularly relates to a method and system for quality control of electronic components. Background Art

[0002] With the rapid development of modern electronic technology, the quality control of electronic components has become a key factor determining the competitiveness of products. High-quality electronic components can improve the reliability and performance of products; the electrical performance quality of electronic components is the basis for the normal operation of electronic devices. In electronic devices, electrical performance is an important indicator for measuring the operating conditions, safety performance, and working efficiency of the devices, and it includes basic electrical parameters such as voltage, current, resistance, capacitance, and inductance. In a power adapter, as a switching element, the performance of a transistor directly affects the stability and efficiency of the power supply. If the switching speed of the transistor decreases, it will lead to inaccurate response control of the input signal, thereby affecting the output stability of the power adapter.

[0003] Existing methods mainly adopt a multi-phase parallel topology structure to distribute the load to multiple transistors, thereby reducing the load on each transistor.

[0004] For example, the transistor power switching device and the method for measuring its characteristics announced in the invention patent announcement with the publication number of CN102473724B include: an array of vertical transistor elements for conducting current between the first and second surfaces of a semiconductor body. The device also includes a semiconductor monitoring element, which includes first and second semiconductor monitoring regions located in the semiconductor body and a monitoring conductive layer different from the current-carrying conductive layer of the transistor array. The semiconductor monitoring element provides a representation of the semiconductor properties of the transistor array. The characteristics of the semiconductor monitoring element are measured as a representation of the characteristics of the transistor array. By measuring and recording the parameters when the transistor power switching device is new and comparing them with the values after the device operates, the source metal aging of the transistor power switching device is monitored, where the parameter is a function of the sheet resistance of the monitoring conductive layer. The measured current is applied between a first position on an elongated strip element of the monitoring conductive layer and a first position on one of a pair of laterally extending portions of the strip, and the corresponding voltage generated between a second position on the elongated strip element and the other of the pair of laterally extending portions is measured.

[0005] For example, an IGZO transistor and an inverter unit with a fully surrounded source-drain-gate disclosed in the invention patent application with the publication number of CN118738129A include: a fully surrounded source, a fully surrounded drain, a fully surrounded gate, a gate dielectric layer, an IGZO channel layer, and a protective layer. The fully surrounded source-drain-gate means that the source, drain, and gate completely surround the IGZO channel layer. Among them, the source and drain surrounding the channel layer can increase the current transmission path, reduce the parasitic capacitance and contact resistance, improve the switching speed and on-current of the device, and reduce the signal delay, noise, and power consumption.

[0006] However, in the process of implementing the technical solution of the present invention in the embodiments of the present application, it is found that the above technology has at least the following technical problems: In the prior art, the electrical performance quality of electronic components is the basic requirement for the normal operation of the components. In a power adapter, as a switching element, the transistor controls the on and off of the current, and its electrical performance quality is the key to ensuring a stable voltage output. When an input voltage signal arrives, the transistor can quickly respond to conduct or cut off the current, thereby achieving a stable voltage output.

[0007] Since the switching speed of the transistor directly affects the efficiency and output stability of the power adapter, high-frequency switching operations may cause the transistor to generate a thermal effect, thereby reducing its performance (such as a decrease in the switching speed), resulting in the problem that the response control process of the transistor to the input signal does not fully consider the switching response difference. Summary of the Invention

[0008] By providing a method and system for controlling the quality of electronic components, the embodiments of the present application solve the problem that the response control process of the transistor to the input signal in the prior art does not fully consider the switching response difference, and achieve an improvement in the adequacy of the response control of the transistor to the input signal during the switching process.

[0009] The embodiments of the present application provide a method for controlling the quality of electronic components, including the following steps: During the switching process of the transistor, conduct an abnormal assessment of the transistor switching to quantitatively describe the abnormal situation of the transistor switching, and based on the quantitative result, judge whether to perform switching speed delay optimization, where the switching speed delay optimization is used to reduce the switching speed delay of the transistor; if the switching speed delay optimization is performed, then perform switching speed delay regulation based on the obtained switching speed delay regulation parameters to improve the accuracy of the switching speed delay control of the transistor; if the switching speed delay optimization is not performed, then conduct an assessment of the accuracy of the input signal response control to quantitatively describe the response of the transistor to the input signal, and based on the quantitative result of the assessment of the accuracy of the input signal response control, judge whether to perform input signal response control optimization, where the input signal response control optimization is used to improve the response control ability of the transistor to the input signal.

[0010] An embodiment of the present application provides an electronic component quality control system, including a transistor switch abnormality evaluation module, a switching speed delay regulation module, and an input signal response control accuracy evaluation module: Among them, the transistor switch abnormality evaluation module is used to evaluate the transistor switch abnormality during the transistor switching process to quantitatively describe the abnormality of the transistor switch, and judge whether to optimize the switching speed delay based on the quantitative result. The switching speed delay optimization is used to reduce the switching speed delay of the transistor; the switching speed delay regulation module is used to, if the switching speed delay is optimized, perform switching speed delay regulation based on the obtained switching speed delay regulation parameters to improve the accuracy of the switching speed delay control of the transistor; the input signal response control accuracy evaluation module is used to, if the switching speed delay is not optimized, perform an input signal response control accuracy evaluation to quantitatively describe the response of the transistor to the input signal, and judge whether to optimize the input signal response control based on the quantitative result of the input signal response control accuracy evaluation. The input signal response control optimization is used to improve the response control ability of the transistor to the input signal.

[0011] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: 1. By evaluating the transistor switch abnormality during the transistor switching process, then judging whether to optimize the switching speed delay based on the quantitative result. If the switching speed delay is optimized, the switching speed delay is regulated. If the switching speed delay is not optimized, the input signal response control accuracy is evaluated. Finally, it is judged whether to optimize the input signal response control based on the quantitative result of the input signal response control accuracy evaluation, thereby improving the accuracy of the input signal response control optimization, and further improving the sufficiency of the response control of the transistor to the input signal during the switching process, effectively solving the problem that the existing technology does not fully consider the switching response difference in the response control process of the transistor to the input signal.

[0012] 2. By comparing the difference between the monitored transistor switching speed response time and the preset transistor switching speed response time to obtain the transistor switching speed response difference value. When the transistor switching speed response difference value does not meet the switching speed qualification condition, the switching speed delay is optimized. When the transistor switching speed response difference value meets the switching speed qualification condition, the input signal response control accuracy is evaluated, thereby improving the reliability of the switching speed delay optimization and the input signal response control accuracy evaluation, and further improving the effectiveness of the switching speed delay optimization and the input signal response control accuracy evaluation.

[0013] 3. After performing a weighted operation on the results of quantifying the degree of approximation between the preset input signal response control factor and the total input signal response control factor and the corresponding input signal response control data, a coupling process is carried out to obtain an optimized score for the input signal response control, thereby realizing the accurate evaluation of the accuracy of the transistor input signal response control, and further realizing the improvement of the effectiveness of the transistor input signal response control. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. is a flowchart of a method for controlling the quality of electronic components provided by an embodiment of the present application; Figure 2 FIG. is a specific flowchart provided by an embodiment of the present application; Figure 3 FIG. is a schematic structural diagram of a system for controlling the quality of electronic components provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] In an embodiment of the present application, by providing a method and a system for controlling the quality of electronic components, the problem in the prior art that the response control process of a transistor to an input signal does not fully consider the switching response difference is solved. By performing an abnormal evaluation of the transistor switch during the transistor switching process, a difference value reflecting the transistor switch speed is obtained to quantitatively describe the abnormal situation of the transistor switch. Then, based on the quantization result, it is judged whether to perform switch speed delay optimization. When the difference value reflecting the transistor switch speed monitored does not meet the switch speed qualification condition, switch speed delay optimization is performed, and switch speed delay regulation is carried out based on the obtained switch speed delay regulation parameters to improve the accuracy of the transistor switch speed delay control. When the difference value reflecting the transistor switch speed monitored meets the switch speed qualification condition, an evaluation of the accuracy of the input signal response control is performed to quantitatively describe the response situation of the transistor to the input signal. Finally, based on the quantization result of the evaluation of the accuracy of the input signal response control, it is judged whether to perform input signal response control optimization, realizing the improvement of the sufficiency of the response control of the transistor to the input signal during the switching process.

[0016] The technical solution in the embodiment of the present application is to solve the problem that the response control process of the transistor to the input signal does not fully consider the switching response difference, and the general idea is as follows: By performing an abnormal evaluation of the transistor switch during the transistor switching process, and then judging whether to perform switch speed delay optimization based on the quantization result. If switch speed delay optimization is performed, switch speed delay regulation is carried out. If switch speed delay optimization is not performed, an evaluation of the accuracy of the input signal response control is performed. Finally, based on the quantization result of the evaluation of the accuracy of the input signal response control, it is judged whether to perform input signal response control optimization, achieving the effect of improving the sufficiency of the response control of the transistor to the input signal during the switching process.

[0017] To better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings of the specification and specific implementation manners.

[0018] As Figure 1 shown, it is a flowchart of a method for quality control of electronic components provided by an embodiment of the present application. The method includes the following steps: Transistor switch anomaly evaluation: During the transistor switching process, transistor switch anomaly evaluation is performed to quantitatively describe the anomaly of the transistor switch. Based on the quantitative result, it is judged whether to perform switch speed delay optimization, and the switch speed delay optimization is used to reduce the switch speed delay of the transistor; Switch speed delay regulation: If switch speed delay optimization is performed, switch speed delay regulation is performed based on the obtained switch speed delay regulation parameters to improve the accuracy of the switch speed delay control of the transistor; Input signal response control accuracy evaluation: If switch speed delay optimization is not performed, input signal response control accuracy evaluation is performed to quantitatively describe the response of the transistor to the input signal. Based on the quantitative result of the input signal response control accuracy evaluation, it is judged whether to perform input signal response control optimization, and the input signal response control optimization is used to improve the response control ability of the transistor to the input signal.

[0019] In this embodiment, as Figure 2 shown, it is a specific flowchart provided by an embodiment of the present application; by performing transistor switch anomaly evaluation, the difference value of the transistor switch speed reflection is obtained. When the monitored difference value of the transistor switch speed reflection does not meet the switch speed qualification condition, switch speed delay optimization is performed; if switch speed delay optimization is performed, the drive resistance reduction process is performed based on the obtained switch speed delay reflection score and switch speed delay regulation factor; if switch speed delay optimization is not performed, input signal response control accuracy evaluation is further performed to obtain the input signal response control optimization score and input signal response control factor, and input signal response control is performed according to the input signal response control factor; through switch speed delay optimization and input signal response control optimization, it helps to reduce switch losses, ensure the integrity and accuracy of the signal during transmission, and thus improve the adequacy of the response control of the transistor to the input signal during the switching process.

[0020] As a switching element, a transistor controls the on and off of current, and the quality of its electrical performance is the key to ensuring a stable voltage output. The current loop is the path through which current flows in a power adapter, including the power input terminal, transistor, transformer, load capacitor, and load resistor, etc. To ensure the stable operation of the transistor, an abnormal evaluation of the transistor switch is carried out to quantitatively describe the abnormal situation of the transistor switch, and then based on the quantitative result, it is judged whether to optimize the switching speed delay. By optimizing the switching speed delay, the energy loss of the transistor during the switching process can be reduced, the overall efficiency of the power adapter can be improved, and it helps to achieve a more stable voltage output. If the switching speed delay is optimized, further adjustment of the switching speed delay is carried out to improve the accuracy of the switching speed delay control of the transistor. If the switching speed delay is not optimized, an evaluation of the accuracy of the input signal response control is carried out and it is further judged whether to optimize the input signal response control. By optimizing the response control of the input signal (optimizing the switching speed delay and the input signal response control), it helps to reduce the switching loss, ensure that the transistor can quickly respond to the input signal, and achieve a stable voltage output.

[0021] Furthermore, the transistor switching speed response time includes the transistor average turn-on time and the transistor average turn-off time; the preset transistor switching speed response time includes the preset average turn-on time and the preset average turn-off time; the transistor switching speed response difference value includes the turn-on time response difference value and the turn-off time response difference value, which is used to reflect the delay situation of the transistor switching speed; the turn-on time response difference value is represented by the difference between the transistor average turn-on time and the preset transistor average turn-on time; the turn-off time response difference value is represented by the difference between the transistor average turn-off time and the preset transistor average turn-off time. Among them, the average value of the time required for the transistor to change from the cut-off state to the fully conducting state from the arrival of the input signal is monitored by an oscilloscope within a preset time period as the transistor average turn-on time; the average value of the time required for the transistor to change from the conducting state to the fully cut-off state from the removal of the input signal is monitored by an oscilloscope within a preset time period as the transistor average turn-off time.

[0022] It should be added that during the transistor switching process, an abnormal evaluation of the transistor switch is carried out to quantitatively describe the abnormal situation of the transistor switch, and based on the quantitative result, it is judged whether to optimize the switching speed delay. The specific process is as follows: A difference comparison (i.e., a subtraction operation) is carried out based on the monitored transistor switching speed response time and the preset transistor switching speed response time obtained from the database to obtain the transistor switching speed response difference value, where the preset transistor switching speed response time is represented by the average value of the transistor switching speed response time corresponding to the historical time period.

[0023] When the difference value reflected by the monitored transistor switching speed does not meet the switching speed qualification condition, a switching speed delay prompt is sent, and switching speed delay optimization is performed.

[0024] Conversely, when the difference value reflected by the monitored transistor switching speed meets the switching speed qualification condition, a switching speed qualification prompt is sent, and the accuracy evaluation of the input signal response control is performed; the switching speed qualification condition means that the difference values reflected by the transistor switching speeds are all not greater than 0.

[0025] It should be added that the switching speed delay optimization includes heat dissipation and topology regulation and switching speed delay regulation; the specific process of heat dissipation and topology regulation is as follows: after the transistor heat dissipation setting is performed, the difference value reflected by the transistor switching speed is re-obtained. When the re-obtained difference value reflected by the transistor switching speed meets the switching speed qualification condition, the execution is stopped. Otherwise, the multi-phase parallel topology setting is performed; after the multi-phase parallel topology setting is performed, the difference value reflected by the transistor switching speed is re-obtained. When the re-obtained difference value reflected by the transistor switching speed meets the switching speed qualification condition, the execution is stopped. Otherwise, the switching speed delay regulation is performed; the steps for performing the multi-phase parallel topology setting are: monitoring the average value of the current in the current loop. If the monitored average value of the current in the current loop is not within the preset current balance range, a prompt is sent to the preset personnel to adjust the driving signal timing, where the preset current balance range is set by the preset personnel; if the monitored average value of the current in the current loop is within the preset current balance range, the monitoring of the average value of the current in the current loop is stopped. If the average value of the current in the current loop corresponding to the adjusted driving signal timing is still not within the preset current balance range, an alarm prompt is sent; the average value of the current in the current loop is represented by the average value of the currents at the preset position points in the current loop; performing the transistor heat dissipation setting means sending a prompt to the preset personnel to gradually increase the startup duration of the corresponding preset heat dissipation device to reduce the working temperature of the transistor, thereby reducing the channel resistance and the carrier dynamic resistance to increase the switching speed; performing the multi-phase parallel topology setting means sending a prompt to the preset personnel to use a multi-phase parallel topology structure to distribute the load to the preset transistors to reduce the load of the transistors to increase the switching speed.

[0026] In this embodiment, heat dissipation and topology regulation are performed by monitoring the transistor switching speed to reflect the proportional relationship between the difference value and the preset transistor switching speed reflection difference value set by the preset personnel, and gradually increasing the startup duration of the preset heat dissipation device (such as a heat sink) in corresponding preset proportions. By gradually increasing the startup duration of the preset heat dissipation device, it helps to reduce the transistor operating temperature, reduce the channel resistance and carrier dynamic resistance, thereby improving the switching speed; sharing the load through a multi-phase parallel topology structure reduces the load on a single transistor, thereby improving the switching speed; while performing the multi-phase parallel topology setting, it is also necessary to monitor the average value of the current in the current loop. When the average value of the current in the current loop is not within the preset current balance range, a prompt is sent to the preset personnel to adjust the driving signal timing, which is beneficial to ensuring current balance, further improving the switching speed and stability, and thus enhancing the adequacy of the transistor's response control to the input signal during the switching process.

[0027] Further, the regulation of the switching speed delay includes: A1, obtaining the switching speed delay reflection score, which is used to regulate the transistor switching speed delay; A2, setting the driving resistance, which is used to reduce the gate capacitance charging time, thereby reducing the transistor turn-on time.

[0028] Specifically, the specific process of obtaining the switching speed delay reflection score is as follows: A11, quantifying the approximation degree between the average transistor power consumption and the preset average transistor power consumption to obtain the first switching speed delay reflection index, which is used to reflect the influence of the average transistor power consumption on the transistor switching speed delay. Specifically, the expression of the first switching speed delay reflection index is , , D represents the number of the preset time period, Q represents the total number of the preset time periods, represents the first switching speed delay reflection index of the Dth preset time period, represents the average transistor power consumption of the Dth preset time period, represents the preset average transistor power consumption. Among them, the transistor power consumption is obtained by monitoring the average current and average voltage within the transistor switching period during the preset time period through an oscilloscope and then performing numerical integration through a simulation software (such as SPICE), and its average value is used as the average transistor power consumption. The units of the average transistor power consumption and the preset average transistor power consumption are both watts.

[0029] A12, quantifying the approximation degree between the difference value of the turn-on time to be optimized and the preset difference value of the turn-on time to be optimized to obtain the second switching speed delay reflection index, which is used to reflect the influence of the difference value of the turn-on time to be optimized on the transistor switching speed delay. Specifically, the expression of the second switching speed delay reflection index is , The second switching speed delay reflection index representing the D-th preset time period The to-be-optimized turn-on time reflection difference value representing the D-th preset time period The to-be-optimized turn-on time reflection difference value is represented by a turn-on time reflection difference value greater than 0; the unit of both the to-be-optimized turn-on time reflection difference value and the preset to-be-optimized turn-on time reflection difference value is microsecond.

[0030] A13. The third switching speed delay reflection index is obtained by quantifying the approximation degree between the to-be-optimized turn-off time reflection difference value and the preset to-be-optimized turn-off time reflection difference value, and is used to reflect the influence of the to-be-optimized turn-off time reflection difference value on the transistor switching speed delay situation. Specifically, the expression of the third switching speed delay reflection index is , The third switching speed delay reflection index representing the D-th preset time period The to-be-optimized turn-off time reflection difference value representing the D-th preset time period The to-be-optimized turn-off time reflection difference value is represented by a turn-off time reflection difference value greater than 0; the unit of both the to-be-optimized turn-off time reflection difference value and the preset to-be-optimized turn-off time reflection difference value is microsecond.

[0031] A14. The fourth switching speed delay reflection index is obtained by quantifying the approximation degree between the average switching frequency and the preset average switching frequency, and is used to reflect the influence of the average switching frequency on the transistor switching speed delay situation. Specifically, the expression of the fourth switching speed delay reflection index is , The fourth switching speed delay reflection index representing the D-th preset time period The average switching frequency representing the D-th preset time period The preset average switching frequency. The average value of the number of transistor switchings within the preset time period is monitored by a spectrum analyzer and an oscilloscope as the average switching frequency. The unit of both the average switching frequency and the preset average switching frequency is times.

[0032] A15. After weighting operations on the switching speed delay reflection data and the corresponding preset switching speed delay reflection factors, and then performing coupling processing, the switching speed delay reflection score is obtained; the switching speed delay reflection score is used to reflect the comprehensive influence of the switching speed delay regulation parameters and the preset switching speed delay reflection parameters on the transistor switching speed delay situation; the switching speed delay reflection score is obtained by quantifying the transistor switching speed delay situation by combining the switching speed delay regulation parameters and the preset switching speed delay regulation parameters obtained from the database.

[0033] Among them, the switching speed delay reflection fraction is obtained by the following method: ; In the formula, represents the switching speed delay reflection fraction of the D-th preset time period, represents the preset first switching speed delay reflection factor, represents the preset second switching speed delay reflection factor, represents the preset third switching speed delay reflection factor, represents the preset fourth switching speed delay reflection factor.

[0034] It should be explained that the switching speed delay regulation parameters include the average transistor power consumption, the difference value of the on-time to be optimized, the difference value of the off-time to be optimized, and the average switching frequency; the preset switching speed delay regulation parameters include the preset switching speed delay reflection parameters and the preset switching speed delay reflection factors; the preset switching speed delay reflection parameters include the preset average transistor power consumption, the preset difference value of the on-time to be optimized, the preset difference value of the off-time to be optimized, and the preset average switching frequency; the preset switching speed delay reflection factors include the preset first switching speed delay reflection factor, the preset second switching speed delay reflection factor, the preset third switching speed delay reflection factor, and the preset fourth switching speed delay reflection factor, which are used to reflect the influence of the switching speed delay reflection data on the switching speed delay reflection fraction; the switching speed delay reflection data includes the first switching speed delay reflection index, the second switching speed delay reflection index, the third switching speed delay reflection index, and the fourth switching speed delay reflection index, and the switching speed delay reflection data are all greater than 0.

[0035] It should be added that the preset switching speed delay regulation parameters are represented by the average value of the switching speed delay regulation parameters in the historical time period; a set of mapping groups containing mapping sets is obtained from the database to reflect the mapping relationship between the switching speed delay reflection data and the corresponding preset switching speed delay reflection factors; the preset switching speed delay reflection factors can be obtained by inputting the real-time switching speed delay reflection data into the corresponding mapping group; the mapping relationship in the mapping set can be a one-to-one or many-to-one relationship; for example, the value range of the preset switching speed delay reflection factor is 0-1.

[0036] In this embodiment, the switching speed delay reflection score is further obtained by analyzing the switching speed delay reflection data. The larger the first switching speed delay reflection index, the stronger the influence of the average transistor power consumption on the transistor switching speed delay, resulting in a larger switching speed delay reflection score; the larger the second switching speed delay reflection index, the stronger the influence of the turn-on time reflection difference value to be optimized on the transistor switching speed delay, resulting in a larger switching speed delay reflection score; the third switching speed delay reflection index means that the influence of the turn-off time reflection difference value to be optimized on the transistor switching speed delay is stronger, resulting in a larger switching speed delay reflection score; the larger the fourth switching speed delay reflection index, the stronger the influence of the average switching frequency on the transistor switching speed delay, resulting in a larger switching speed delay reflection score; in summary, in this embodiment, the switching speed delay reflection data and the switching speed delay reflection score are positively correlated.

[0037] The switch speed delay control parameters monitored in this embodiment do not exist in isolation, but have interrelated characteristics, and require correlation analysis to describe their joint effects. The increase in average transistor power consumption may lead to an enhanced thermal effect of the transistor during the turn-on process. The thermal effect will change the electrical characteristics of the transistor, causing the time required for the transistor to reach a fully turned-on state to change, resulting in a longer turn-on time and a longer turn-off time, which in turn leads to a larger difference in the turn-on time reflection to be optimized and a larger difference in the turn-off time reflection to be optimized; the larger the difference in the turn-on time reflection to be optimized, the greater the energy loss distribution of the transistor during the switching process, which in turn affects the turn-off time, resulting in a larger difference in the turn-off time reflection to be optimized; the greater the average switching frequency, the more times the transistor switches, which may lead to an increase in transistor power consumption, which in turn leads to a greater average transistor power consumption. By analyzing the comprehensive impact of the parameters, an accurate evaluation of the transistor switching speed delay is achieved, thereby achieving the effect of improving the adequacy of the transistor's response control to the input signal during the switching process.

[0038] Furthermore, the specific process of setting the driving resistance is as follows: A21, compare the switching speed delay reflection score with the preset switching speed delay reflection score obtained from the database (i.e., perform a difference operation) to obtain a switching speed delay difference value, wherein the preset switching speed delay reflection score is represented by the average value of the switching speed delay reflection scores in the historical time period.

[0039] A22, performing a ratio analysis (i.e., performing a ratio operation) on the switch speed delay difference value and the preset switch speed delay difference value obtained from the database to obtain a switch speed delay control factor, wherein the preset switch speed delay difference value is represented by an average value of the switch speed delay difference values in a historical time period.

[0040] For A23, perform the processing of reducing the drive resistance. The processing of reducing the drive resistance means sending a prompt to a preset person to gradually reduce the drive resistance. When the drive resistance is reduced to the minimum value of the preset drive resistance obtained from the database, if the difference value reflected by the transistor switching speed still does not meet the switching speed qualification condition, an alarm prompt is sent. Among them, the minimum value of the preset drive resistance is represented by the minimum value of the drive resistance in the historical time period; the switching speed delay difference value is represented by the absolute value corresponding to the difference between the switching speed delay reflection score and the preset switching speed delay reflection score; the switching speed delay regulation factor is represented by the ratio of the switching speed delay difference value to the preset switching speed delay difference value.

[0041] In this embodiment, when receiving the prompt for processing of reducing the drive resistance, the drive resistance is gradually reduced in corresponding amplitudes by the percentage corresponding to the switching speed delay regulation factor. The purpose of gradually reducing the drive resistance is to accelerate the switching speed of the transistor by reducing the drive resistance, thereby reducing the switching speed delay. When the drive resistance is reduced to the minimum value of the preset drive resistance, if the difference value reflected by the transistor switching speed still does not meet the switching speed qualification condition, it indicates that the current adjustment of the drive resistance cannot further optimize the switching speed, and an alarm prompt is sent; by performing the processing of reducing the drive resistance, it helps to reduce the switching speed delay of the transistor, ensure the stable operation of the transistor, and further achieve the effect of improving the adequacy of the response control of the transistor to the input signal during the switching process.

[0042] Furthermore, perform the evaluation of the accuracy of the input signal response control to quantitatively describe the response of the transistor to the input signal, and judge whether to optimize the input signal response control based on the quantitative result of the evaluation of the accuracy of the input signal response control. The specific process is as follows: Compare the difference between the monitored transistor response control time and the preset transistor response control time obtained from the database to obtain the response control difference value; when the monitored response control difference value does not meet the input signal response control qualification condition, send an unqualified prompt for the input signal response control and perform the optimization of the input signal response control; when the monitored response control difference value meets the input signal response control qualification condition, send a qualified prompt for the input signal response control; the input signal response control qualification condition means that the response control difference values are all not greater than 0.

[0043] The transistor response control time includes the transistor average rise time and the transistor average fall time; the preset transistor response control time includes the preset transistor average rise time and the preset transistor average fall time; the response control difference value includes the transistor rise time difference value and the transistor fall time difference value; the transistor rise time difference value is represented by the difference between the transistor average rise time and the preset transistor average rise time; the transistor fall time difference value is represented by the difference between the transistor average fall time and the preset transistor average fall time.

[0044] Among them, when monitoring the transistor from the cut-off state to the saturation state within the preset input response time period through an oscilloscope, the time when the collector current rises from 10% to 90% of its saturation current is statistically averaged as the average rise time of the transistor; when monitoring the transistor from the saturation state to the cut-off state within the preset input response time period through an oscilloscope, the time when the collector current drops from 90% to 10% of its saturation current is statistically averaged as the average fall time of the transistor; the preset transistor response control time is represented by the average value of the transistor response control time in the historical time period.

[0045] Specifically, optimizing the input signal response control includes obtaining the input signal response control factor and performing the input signal response control; obtaining the input signal response control factor is used to regulate the input signal response of the transistor; performing the input signal response control is used to improve the accuracy of the input signal response control of the transistor; the specific process of obtaining the input signal response control factor is as follows: S1. Quantify the degree of approximation between the preset signal transmission delay duration and the signal transmission delay duration to obtain the first input signal response control value, which is used to reflect the influence of the signal transmission delay duration on the accuracy of the input signal response control of the transistor. Specifically, the expression of the first input signal response control value is , represents the first input signal response control value of the Bth preset input response time period, represents the signal transmission delay duration of the Bth preset input response time period, represents the preset signal transmission delay duration, , B represents the number of the preset input response time period, M represents the total number of the preset input response time periods, the time interval from the start of the change of the input signal to the start of the change of the output signal within the preset input response time period is monitored through an oscilloscope as the transmission delay duration, and the units of the signal transmission delay duration and the preset signal transmission delay duration are both microseconds.

[0046] S2. Quantify the degree of approximation between the average transistor gain-bandwidth product and the preset average transistor gain-bandwidth product to obtain the second input signal response control value, which is used to reflect the influence of the average transistor gain-bandwidth product on the accuracy of the input signal response control of the transistor. Specifically, the expression of the second input signal response control value is , represents the second input signal response control value of the Bth preset input response time period, represents the average transistor gain-bandwidth product of the Bth preset input response time period, Denote the preset average transistor gain-bandwidth product. Monitor the gain and frequency response of the transistor at preset time points within the preset input response time period through a network analyzer, and take the average value of their product as the average transistor gain-bandwidth product. The units of both the average transistor gain-bandwidth product and the preset average transistor gain-bandwidth product are hertz.

[0047] S3. Quantify the degree of approximation between the preset average transistor temperature and the average transistor temperature to obtain the third input signal response control value, which is used to reflect the influence of the average transistor temperature on the accuracy of the transistor input signal response control. Specifically, the expression of the third input signal response control value is , Denote the third input signal response control value of the Bth preset input response time period, Denote the average transistor temperature of the Bth preset input response time period, Denote the preset average transistor temperature. Monitor the temperature of the preset point on the surface of the transistor at the end state within the preset input response time period through a thermocouple, and take its average value as the average transistor temperature. The units of both the average transistor temperature and the preset average transistor temperature are degrees Celsius.

[0048] S4. After performing a weighted operation on the result of quantifying the degree of approximation between the preset input signal response control factor and the total input signal response control factor and the corresponding input signal response control data, perform a coupling process to obtain the input signal response control optimization score; the input signal response control optimization score is used to reflect the comprehensive influence of the input signal response control parameters and the preset input signal response control parameters on the accuracy of the transistor input signal response control.

[0049] Among them, the input signal response control optimization score is obtained through the following method: ; In the formula, Denote the input signal response control optimization score of the Bth preset input response time period, Denote the preset first input signal response control factor, Denote the preset second input signal response control factor, Denote the preset third input signal response control factor, and Z denotes the total input signal response control factor.

[0050] Specifically, the expression of the total input signal response control factor is .

[0051] In summary, the input signal response control data includes the first input signal response control value, the second input signal response control value, and the third input signal response control value, and all the input signal response control data is greater than 0; the input signal response control parameters include the signal transmission delay duration, the average transistor gain-bandwidth product, and the average transistor temperature; the preset input signal response control parameters include the preset signal transmission delay duration, the preset average transistor gain-bandwidth product, and the preset average transistor temperature; the preset input signal response control factors include the preset first input signal response control factor, the preset second input signal response control factor, and the preset third input signal response control factor, which are used to reflect the influence degree of the input signal response control data on the input signal response control optimization score.

[0052] Specifically, the preset input signal response control parameters are represented by the average value of the input signal response control parameters in the historical time period; a set of mapping groups containing mapping sets is obtained from the database to reflect the mapping relationship between the input signal response control data and the corresponding preset input signal response control factors; the preset input signal response control factors can be obtained by inputting the real-time input signal response control data into the corresponding mapping group; the mapping relationship in the mapping set can be a one-to-one or many-to-one relationship; for example, the value range of the preset input signal response control factor is 0-1.

[0053] The input signal response control optimization score and the preset input signal response control score obtained from the database are compared for differences to obtain the input signal response control difference value, where the preset input signal response control score is represented by the average value of the input signal response control scores in the historical time period; the input signal response control difference value and the preset input signal response control difference value are analyzed for the proportion degree (i.e., ratio operation) to obtain the input signal response control factor, where the preset input signal response control difference value is represented by the average value of the input signal response control difference values in the historical time period; the input signal response control difference value is represented by the absolute value corresponding to the difference between the input signal response control optimization score and the preset input signal response control score obtained from the database.

[0054] In this embodiment, by monitoring the response control difference value to quantitatively describe the deviation degree of the transistor's response to the input signal, through input signal response control optimization, it helps to reduce the response delay of the transistor to the input signal, thereby improving the electrical performance quality of the transistor; by analyzing the proportion degree of the input signal response control difference value and the preset input signal response control difference value to obtain the input signal response control factor, it helps to achieve dynamic regulation of the transistor's response delay to the input signal.

[0055] By analyzing the input signal response control data, the input signal response control optimization score is further obtained. The larger the first input signal response control value, the stronger the influence of the signal transmission delay duration on the accuracy of the transistor input signal response control, resulting in a larger input signal response control optimization score; the larger the second input signal response control value, the stronger the influence of the average transistor gain-bandwidth product on the accuracy of the transistor input signal response control, resulting in a larger input signal response control optimization score; the larger the third input signal response control value, the stronger the influence of the average transistor temperature on the accuracy of the transistor input signal response control, resulting in a larger input signal response control optimization score; in summary, in this embodiment, there is a positive correlation between the input signal response control data and the input signal response control optimization score.

[0056] In this embodiment, the monitored input signal response control parameters do not exist in isolation and have interrelated characteristics, and correlation analysis is required to describe their combined effects. The larger the average transistor gain-bandwidth product, the stronger the amplification ability of the transistor, the faster the response speed to the signal, which means that the transistor can follow the change of the input signal faster, thus helping to reduce the signal transmission delay duration, and further resulting in a smaller signal transmission delay duration; the higher the average transistor temperature, the lower the carrier mobility inside the transistor, resulting in a decrease in the switching speed and amplification ability of the transistor, and further resulting in a larger signal transmission delay duration; the higher the average transistor temperature, the more intense the thermal motion of the carriers inside the transistor may be, increasing the scattering of the carriers, thereby reducing the carrier mobility, and further resulting in a smaller average transistor gain-bandwidth product. By analyzing the comprehensive influence between the parameters, the accurate evaluation of the accuracy of the transistor input signal response control is realized, and further the effect of improving the adequacy of the transistor's response control to the input signal during the switching process is achieved.

[0057] Further, the specific process of performing input signal response control is as follows: The first step is to set the input signal frequency. When the response control difference value corresponding to the input signal frequency increasing to the maximum value of the input signal frequency meets the input signal response control qualification condition, a transistor electrical performance quality qualified prompt is sent; otherwise, the second step is executed, and setting the input signal frequency means sending a prompt to a preset person to gradually increase the input signal frequency; the second step is to judge the load characteristics. When the monitored load is capacitive, the load capacitance is set, and when the monitored load is resistive, the load resistance is set.

[0058] Performing load capacitance setting means sending a prompt to a preset person to gradually decrease the load capacitance. When the response control difference value corresponding to the minimum preset load capacitance meets the qualified condition for input signal response control, a qualified prompt for the electrical performance quality of the transistor is sent; otherwise, an alarm prompt is sent. Herein, the minimum preset load capacitance is set by the preset person. Performing load resistance setting means sending a prompt to a preset person to gradually decrease the load resistance. When the response control difference value corresponding to the minimum preset load resistance meets the qualified condition for input signal response control, a qualified prompt for the electrical performance quality of the transistor is sent; otherwise, an alarm prompt is sent. Herein, the minimum preset load resistance is set by the preset person.

[0059] In this embodiment, when a prompt for input signal frequency setting is detected, the input signal frequency is gradually increased in corresponding amplitudes according to the percentage corresponding to the input signal response control factor. By judging the load characteristics, it helps to accurately identify the type of the current load, avoid performance degradation or faults caused by mismatching, and thus achieve targeted regulation of the transistor's response control ability to the input signal. If load capacitance setting is to be performed, then according to the characteristics of the capacitive load, based on the percentage corresponding to the input signal response control factor, the load capacitance is gradually decreased, which helps to reduce the phase lag or lead caused by the capacitive load. If load resistance setting is to be performed, then according to the characteristics of the resistive load, based on the percentage corresponding to the input signal response control factor, the load resistance is gradually decreased, which helps to maintain stable power output and impedance matching under different load resistances. By performing input signal response control, it helps to ensure the electrical performance quality of the transistor, and thus improves the sufficiency of the transistor's response control to the input signal during the switching process.

[0060] Such as Figure 3As shown in the figure, it is a schematic structural diagram of an electronic component quality control system provided by an embodiment of the present application. An electronic component quality control system provided by an embodiment of the present application includes a transistor switch anomaly evaluation module, a switching speed delay regulation module, and an input signal response control accuracy evaluation module: Among them, the transistor switch anomaly evaluation module is used to evaluate the transistor switch anomaly during the transistor switching process to quantitatively describe the anomaly of the transistor switch, and based on the quantitative result, determine whether to optimize the switching speed delay. The switching speed delay optimization is used to reduce the switching speed delay of the transistor; the switching speed delay regulation module is used to, if the switching speed delay optimization is performed, perform switching speed delay regulation based on the obtained switching speed delay regulation parameters to improve the accuracy of the switching speed delay control of the transistor; the input signal response control accuracy evaluation module is used to, if the switching speed delay optimization is not performed, evaluate the input signal response control accuracy to quantitatively describe the response of the transistor to the input signal, and based on the quantitative result of the input signal response control accuracy evaluation, determine whether to optimize the input signal response control. The input signal response control optimization is used to improve the response control ability of the transistor to the input signal.

[0061] In summary, by evaluating the transistor switch anomaly during the transistor switching process, then determining whether to optimize the switching speed delay based on the quantitative result, if the switching speed delay optimization is performed, then performing the switching speed delay regulation, if the switching speed delay optimization is not performed, then evaluating the input signal response control accuracy, and finally determining whether to optimize the input signal response control based on the quantitative result of the input signal response control accuracy evaluation, the accuracy of the input signal response control optimization is improved, and further the sufficiency of the response control of the transistor to the input signal during the switching process is improved, effectively solving the problem that the response control process of the transistor to the input signal in the prior art does not fully consider the switching response difference.

[0062] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0063] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0064] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0065] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operational steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0066] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0067] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A method for quality control of electronic components, characterized in that, It includes the following steps: During the transistor switching process, perform transistor switching anomaly evaluation to quantitatively describe the anomaly of transistor switching, and based on the quantitative result, determine whether to perform switching speed delay optimization, where the switching speed delay optimization is used to reduce the switching speed delay of the transistor; If switching speed delay optimization is to be performed, then perform switching speed delay regulation based on the obtained switching speed delay regulation parameters to improve the accuracy of the switching speed delay control of the transistor; If switching speed delay optimization is not to be performed, then perform input signal response control accuracy evaluation to quantitatively describe the response of the transistor to the input signal, and based on the quantitative result of the input signal response control accuracy evaluation, determine whether to perform input signal response control optimization, where the input signal response control optimization is used to improve the response control ability of the transistor to the input signal.

2. The method for quality control of electronic components according to claim 1, wherein, The process of performing transistor switching anomaly evaluation during the transistor switching process to quantitatively describe the anomaly of transistor switching and determining whether to perform switching speed delay optimization based on the quantitative result is as follows: Obtain the transistor switching speed reflection difference value by comparing the monitored transistor switching speed reflection time with the preset transistor switching speed reflection time obtained from the database; When the monitored transistor switching speed reflection difference value does not meet the switching speed qualification condition, send a switching speed delay prompt and perform switching speed delay optimization; When the monitored transistor switching speed reflection difference value meets the switching speed qualification condition, send a switching speed qualification prompt and perform input signal response control accuracy evaluation; The switching speed qualification condition means that the transistor switching speed reflection difference values are all not greater than 0; The transistor switching speed reflection time includes the transistor average turn-on time and the transistor average turn-off time; The transistor switching speed reflection difference value includes the turn-on time reflection difference value and the turn-off time reflection difference value, which are used to reflect the delay situation of the transistor switching speed.

3. The method for quality control of electronic components according to claim 2, wherein, Performing the switching speed delay optimization includes performing heat dissipation and topology regulation and performing switching speed delay regulation; The specific process of the heat dissipation and topology regulation is as follows: After setting the transistor heat dissipation, re-obtain the transistor switching speed reflection difference value. When the re-obtained transistor switching speed reflection difference value meets the switching speed qualification condition, stop execution; otherwise, perform the multi-phase parallel topology setting; After performing the multi-phase parallel topology setting, re-obtain the transistor switching speed reflection difference value. When the re-obtained transistor switching speed reflection difference value meets the switching speed qualification condition, stop execution; otherwise, perform the switching speed delay regulation; The steps of performing the multi-phase parallel topology setting are: monitor the average value of the current in the current loop. If the monitored average value of the current in the current loop is not within the preset current balance range, send a prompt to the preset personnel to adjust the driving signal timing; if the monitored average value of the current in the current loop is within the preset current balance range, stop monitoring the average value of the current in the current loop. If the average value of the current in the current loop corresponding to the adjusted driving signal timing is still not within the preset current balance range, then send an alarm prompt; The transistor heat dissipation setting means sending a prompt to a preset person to gradually increase the startup duration of the corresponding preset heat dissipation device to reduce the operating temperature of the transistor; The polyphase parallel topology setting means sending a prompt to a preset person to use a polyphase parallel topology structure to distribute the load to the preset transistor, which is used to reduce the load of the transistor to improve the switching speed.

4. The method for quality control of electronic components according to claim 3, characterized in that, The switching speed delay regulation includes obtaining a switching speed delay reflection score and setting a drive resistance; The obtaining of the switching speed delay reflection score is used to regulate the transistor switching speed delay; The setting of the drive resistance is used to reduce the gate capacitance charging time, thereby reducing the turn-on time of the transistor; The switching speed delay reflection score is obtained by quantifying the transistor switching speed delay situation after combining the switching speed delay regulation parameters and the preset switching speed delay regulation parameters obtained from the database; The switching speed delay regulation parameters include the average transistor power consumption, the difference value reflecting the to-be-optimized turn-on time, the difference value reflecting the to-be-optimized turn-off time, and the average switching frequency; The difference value reflecting the to-be-optimized turn-on time is represented by a turn-on time reflection difference value greater than 0; The difference value reflecting the to-be-optimized turn-off time is represented by a turn-off time reflection difference value greater than 0.

5. The method for quality control of electronic components according to claim 4, characterized in that, The specific process of obtaining the switching speed delay reflection score is as follows: Quantifying the degree of approximation between the average transistor power consumption and the preset average transistor power consumption to obtain a first switching speed delay reflection index, which is used to reflect the influence of the average transistor power consumption on the transistor switching speed delay situation; Quantifying the degree of approximation between the difference value reflecting the to-be-optimized turn-on time and the preset difference value reflecting the to-be-optimized turn-on time to obtain a second switching speed delay reflection index, which is used to reflect the influence of the difference value reflecting the to-be-optimized turn-on time on the transistor switching speed delay situation; Quantifying the degree of approximation between the difference value reflecting the to-be-optimized turn-off time and the preset difference value reflecting the to-be-optimized turn-off time to obtain a third switching speed delay reflection index, which is used to reflect the influence of the difference value reflecting the to-be-optimized turn-off time on the transistor switching speed delay situation; Quantifying the degree of approximation between the average switching frequency and the preset average switching frequency to obtain a fourth switching speed delay reflection index, which is used to reflect the influence of the average switching frequency on the transistor switching speed delay situation; After performing a weighted operation on the switching speed delay reflection data and the corresponding preset switching speed delay reflection factors, and then performing a coupling process to obtain the switching speed delay reflection score; The switching speed delay reflection score is used to reflect the combined influence of the switching speed delay regulation parameters and the preset switching speed delay reflection parameters on the transistor switching speed delay situation.

6. The method for controlling the quality of electronic components according to claim 4, wherein The specific process of setting the drive resistance is as follows: Comparing the difference between the switching speed delay reflection score and the preset switching speed delay reflection score obtained from the database to obtain a switching speed delay difference value; Performing a proportion analysis on the switching speed delay difference value and the preset switching speed delay difference value obtained from the database to obtain a switching speed delay regulation factor; Perform the processing of reducing the drive resistance. When the drive resistance is reduced to the minimum preset drive resistance obtained from the database, if the difference value of the transistor switching speed still does not meet the switching speed qualification condition, send an alarm prompt.

7. The method for quality control of electronic components according to claim 1, characterized in that, Perform the evaluation of the accuracy of the input signal response control to quantitatively describe the response of the transistor to the input signal, and judge whether to optimize the input signal response control based on the quantitative result of the evaluation of the accuracy of the input signal response control. The specific process is as follows: Perform a difference comparison based on the monitored transistor response control time and the preset transistor response control time obtained from the database to obtain the response control difference value; When the monitored response control difference value does not meet the input signal response control qualification condition, send a prompt indicating that the input signal response control is unqualified and perform optimization of the input signal response control; When the monitored response control difference value meets the input signal response control qualification condition, send a prompt indicating that the input signal response control is qualified; The input signal response control qualification condition means that the response control difference values are all not greater than 0; The transistor response control time includes the transistor average rise time and the transistor average fall time; The response control difference value includes the transistor rise time difference value and the transistor fall time difference value.

8. The method for quality control of electronic components according to claim 7, characterized in that, The optimization of the input signal response control includes obtaining the input signal response control factor and performing the input signal response control; The obtained input signal response control factor is used to regulate the response of the transistor to the input signal; Performing the input signal response control is used to improve the accuracy of the transistor input signal response control; The specific process of obtaining the input signal response control factor is as follows: Quantify the degree of approximation between the preset signal transmission delay duration and the signal transmission delay duration to obtain the first input signal response control value, which is used to reflect the influence of the signal transmission delay duration on the accuracy of the transistor input signal response control; Quantify the degree of approximation between the average transistor gain bandwidth product and the preset average transistor gain bandwidth product to obtain the second input signal response control value, which is used to reflect the influence of the average transistor gain bandwidth product on the accuracy of the transistor input signal response control; Quantify the degree of approximation between the preset average transistor temperature and the average transistor temperature to obtain the third input signal response control value, which is used to reflect the influence of the average transistor temperature on the accuracy of the transistor input signal response control; After performing a weighted operation on the result of quantifying the degree of approximation between the preset input signal response control factor and the total input signal response control factor and the corresponding input signal response control data, perform a coupling process to obtain the input signal response control optimization score; The input signal response control optimization score is used to reflect the combined influence of the input signal response control parameters and the preset input signal response control parameters on the accuracy of the transistor input signal response control; The input signal response control data includes the first input signal response control value, the second input signal response control value, and the third input signal response control value; The input signal response control parameters include the signal transmission delay duration, the average transistor gain bandwidth product, and the average transistor temperature; Compare the optimized score of the input signal response control with the preset input signal response control score obtained from the database to obtain the input signal response control difference value; Analyze the proportion degree of the input signal response control difference value and the preset input signal response control difference value to obtain the input signal response control factor.

9. The method for quality control of electronic components according to claim 1, wherein The specific process of performing the input signal response control is as follows: In the first step, set the input signal frequency. When the response control difference value corresponding to the input signal frequency increasing to the maximum value of the input signal frequency meets the input signal response control qualification condition, send a qualified prompt for the electrical performance quality of the transistor. Otherwise, execute the second step. Setting the input signal frequency means sending a prompt to the preset personnel to gradually increase the input signal frequency; In the second step, judge the load characteristics. When the monitored load is capacitive, set the load capacitance. When the monitored load is resistive, set the load resistance; Setting the load capacitance means sending a prompt to the preset personnel to gradually decrease the load capacitance. When the response control difference value corresponding to the load capacitance decreasing to the minimum value of the preset load capacitance meets the input signal response control qualification condition, send a qualified prompt for the electrical performance quality of the transistor. Otherwise, send an alarm prompt; Setting the load resistance means sending a prompt to the preset personnel to gradually decrease the load resistance. When the response control difference value corresponding to the load resistance decreasing to the minimum value of the preset load resistance meets the input signal response control qualification condition, send a qualified prompt for the electrical performance quality of the transistor. Otherwise, send an alarm prompt.

10. An electronic component quality control system, characterized in that, It includes a transistor switch anomaly evaluation module, a switch speed delay regulation module, and an input signal response control accuracy evaluation module: Among them, the transistor switch anomaly evaluation module is used to evaluate the transistor switch anomaly during the transistor switch process to quantitatively describe the anomaly situation of the transistor switch. Based on the quantitative result, judge whether to perform switch speed delay optimization, and the switch speed delay optimization is used to reduce the switch speed delay of the transistor; The switch speed delay regulation module is used to, if switch speed delay optimization is performed, perform switch speed delay regulation based on the obtained switch speed delay regulation parameters to improve the accuracy of the switch speed delay control of the transistor; The input signal response control accuracy evaluation module is used to, if switch speed delay optimization is not performed, evaluate the input signal response control accuracy to quantitatively describe the response situation of the transistor to the input signal. Based on the quantitative result of the input signal response control accuracy evaluation, judge whether to perform input signal response control optimization, and the input signal response control optimization is used to improve the response control ability of the transistor to the input signal.

Images