Low-power-consumption control method and system of controller

Abstract

The invention relates to the field of energy-saving computing, and discloses a low-power-consumption control method and system of a controller, which are used for realizing prediction-sleep-wake-up-response full-link hardware in the controller. Time sequence state data of a controlled object is collected in real time, and a predictive sleep window value is dynamically generated by utilizing a predictive cooperative computing unit, so that intelligent scheduling of sleep and awakening is realized, and the power consumption of a controller is effectively reduced. Meanwhile, in combination with the technologies of threshold comparison, DMA data transmission optimization and the like, the data processing efficiency is improved, and invalid data transmission is reduced. And on the awakening mechanism, an asynchronous awakening circuit and an interrupt request mechanism are adopted to ensure that power supply is quickly recovered and control response is executed when an effective instruction is received, so that the real-time performance of the system is guaranteed. According to the invention, a prediction algorithm, hardware acceleration and an intelligent scheduling technology are fused, the performance of the controller is ensured, the power consumption is obviously reduced, and the endurance time of equipment is prolonged.

Description

Technical Field

[0001] The present invention relates to the field of energy-saving computing, and particularly to a low-power control method and system for a controller. Background Art

[0002] With the explosive growth of Internet of Things devices, the energy consumption problem of controllers has become the core bottleneck restricting their development. Such devices usually rely on button batteries for power supply and need to maintain a working life of 5 - 10 years, which poses harsh requirements on the daily power consumption. The existing technologies mainly reduce power consumption through the following means: Hardware circuit optimization: Using depletion-type MOSFETs to construct an active start-up circuit and reducing the start-up loss to the micro-watt level; Software strategy optimization: Turning off unused peripherals, enabling the chip DC / DC converter to replace the LDO, and using the RTC to replace the timer; Low-power protocols: Multi-protocol chips such as Zigbee and Thread reduce the radio frequency energy consumption through the sleep mode; Communication timing optimization: Such as the "half asleep and half awake" mechanism (100ms working / 100ms sleep) of Difu Company, reducing the receiving power consumption by 50%.

[0003] However, these solutions still have significant deficiencies in predictive control, hardware-level power management, and dynamic response accuracy: The existing solutions rely on fixed-time window sleep or simple threshold judgment and cannot dynamically adjust the sleep window according to the state of the controlled object; Although the existing low-power protocols support sleep, the duty cycle of the receiving window is fixed; The traditional solutions rely on software interrupt response and clock gating: The interrupt response delay > 500μs; The standby leakage current of clock gating still reaches 3 - 5μA; Multi-sensor data requires the MCU to participate in synchronization / screening, resulting in frequent wake-up: The Fanteng switch needs to initialize unused GPIO ports to prevent leakage, increasing the software complexity.

[0004] Therefore, we propose a low-power control method and system for a controller to solve the above problems. Summary of the Invention

[0005] The present invention provides a low-power control method and system for a controller, which is used to implement a full-link hardware of prediction - sleep - wake-up - response in the controller.

[0006] A first aspect of the present invention provides a low-power control method for a controller, the low-power control method for the controller comprising: real-time acquisition of timing state data of a controlled object, and storage in a hardware queue register group; inputting the data in the hardware queue register group into a prediction collaborative calculation unit, the unit being composed of a digital logic circuit solidified in an integrated circuit, and outputting a predicted sleep window value; executing a PREDSLP instruction in a processor instruction set, and writing the predicted sleep window value into a sleep configuration register; according to the value of the sleep configuration register, generating a gated pipeline state signal through a dynamic instruction gating unit; based on the value of the sleep configuration register, generating a control signal of a receiving module through a programmable timing generator, including: extracting the lower 8 bits of the sleep configuration register value through a shift register group, and generating a sleep coefficient value; The system clock is divided into a 100ms period signal by a clock division circuit as a reference timing signal; the sleep coefficient value and the reference timing signal are input into a programmable counter to generate an extended sleep timing signal to meet the following requirements: ; When the value of the sleep configuration register is less than the safety threshold, the hardware timestamp aligner performs the following operations: reading the predicted event occurrence time in the event queue; activating the wake-up circuit 10ms before the event occurs to generate a 10ms precise wake-up pulse; selecting the extended sleep timing signal or the precise wake-up pulse through the multiplexer circuit to generate the final receiving control signal; when the receiving module captures a valid instruction, sending an interrupt request to the CPU through the asynchronous wake-up circuit, restoring the power supply of the instruction fetch circuit and the decoding circuit, and executing the control response.

[0007] Optionally, in a first implementation method of the first aspect of the present invention, it includes: collecting temperature, pressure, and displacement sensor data to generate a sub-channel data packet; inputting the sub-channel data packet into a threshold comparator circuit, eliminating data that exceeds the physical range, and outputting a valid data queue; synchronizing the valid data queue from the sensor clock domain to the system clock domain to generate a synchronization data packet; based on the real-time computing requirements of the predicted collaborative computing unit, the DMA controller writes the synchronization data packet to a specified storage partition of the hardware queue register group to generate a timing state data matrix.

[0008] Optionally, in a second implementation method of the first aspect of the present invention, it includes: extracting timing state data from a hardware queue register group through a parallel multiplexer and converting it into a fixed-point data stream; inputting the fixed-point data stream into a shift-accumulator array, performing a differential operation of a preset fractional order α, and outputting a fractional-order differential value; inputting the fractional-order differential value into a hysteresis loop parameter lookup table, and outputting a hysteresis response flag; and fusing the fractional-order differential value and the hysteresis response flag through a window generation state machine to generate a predicted sleep window value.

[0009] Optionally, in the third implementation manner of the first aspect of the present invention, it includes: identifying the PREDSLP opcode through an instruction decoder circuit to generate a register operation enable signal; converting it into the physical storage address of the sleep configuration register through an address mapping table circuit according to the register number field; loading the predicted sleep window value onto the data bus channel and writing it to the target physical storage address under the control of the register operation enable signal to generate a register write completion flag; and switching the system from the running state to the predicted sleep state through a power consumption state controller according to the register write completion flag.

[0010] Optionally, in the fourth implementation manner of the first aspect of the present invention, it includes: comparing the value of the sleep configuration register with a preset threshold voltage in real time through a voltage comparator circuit to generate a power supply control signal; when the power supply control signal is at a high level, controlling the first MOS transistor array to physically disconnect the power supply path of the instruction fetch circuit to generate a sleep state of the instruction fetch circuit; when the power supply control signal is at a high level, controlling the second MOS transistor array to physically disconnect the power supply path of the decoding circuit to generate a sleep state of the decoding circuit; and fusing the sleep state of the instruction fetch circuit and the sleep state of the decoding circuit through a hardware state encoder to output a 2-bit gated pipeline status signal.

[0011] Optionally, in the fifth implementation manner of the first aspect of the present invention, it includes: the baseband processor of the receiving module performs cyclic redundancy check circuit verification on the received data packet to generate a valid instruction flag signal; inputting the valid instruction flag signal to an edge detection circuit to generate a wake-up trigger pulse; the wake-up trigger pulse driving a power gating driver to output an instruction fetch circuit power supply enable signal and a decoding circuit power supply enable signal; simultaneously when the power supply is restored, generating a non-maskable interrupt vector number through an interrupt controller hardware and writing it to an interrupt vector register; transferring the valid instruction from the receiving buffer to an executor control register through a direct memory access channel to generate a copy of the instruction to be executed; after the power supply of the instruction fetch circuit is restored, the CPU reads the vector number from the interrupt vector register, jumps to a hard-coded interrupt service program, reads the copy of the instruction to be executed in the executor control register, and outputs a control response signal.

[0012] The second aspect of the present invention provides a low-power control system for a controller, including: an acquisition module, configured to collect the timing state data of a controlled object in real time and store it in a hardware queue register group; a sleep module, configured to input the data in the hardware queue register group into a prediction collaborative computing unit, which is composed of digital logic circuits solidified in an integrated circuit, and output a predicted sleep window value; a writing module, configured to execute the PREDSLP instruction in the processor instruction set and write the predicted sleep window value into a sleep configuration register; a gating module, configured to execute and generate a gating pipeline state signal through a dynamic instruction gating unit according to the value of the sleep configuration register; a recovery module, configured to generate a control signal for a receiving module through a programmable timing generator based on the value of the sleep configuration register, including: extracting the lower 8 bits of the sleep configuration register value through a shift register group to generate a sleep coefficient value; Dividing the system clock into a 100 ms periodic signal through a clock frequency division circuit as a reference timing signal; inputting the sleep coefficient value and the reference timing signal into a programmable counter to generate an extended sleep timing signal, satisfying: ; When the value of the sleep configuration register is less than a safety threshold, execute through a hardware timestamp aligner: read the occurrence time of an event in a prediction event queue; activate a wake-up circuit 10 ms before the occurrence time of the event to generate a 10 ms precise wake-up pulse; select an extended sleep timing signal or a precise wake-up pulse through a multiplexer circuit to generate a final receiving control signal; an allocation module, configured to send an interrupt request to the CPU through an asynchronous wake-up circuit when the receiving module captures a valid instruction, restore the power supply of an instruction fetch circuit and a decoding circuit, and execute a control response.

[0013] The mechanism of the present invention is as follows: through the three-layer collaboration of algorithm hardening (fractional-order differential prediction), instruction customization (PREDSLP), and physical isolation (MOS transistor power gating), the entire process of decision-making, execution, and response of predictive sleep is sunk to digital logic circuits, completely avoiding the energy consumption of the software stack, and realizing the unity of nanoampere-level standby current and millisecond-level response. Its core is to deeply couple control theory (modeling the lag characteristics of fractional-order differential) with the hardware architecture to form a self-closed-loop low-power control path.

[0014] Beneficial effects: The sleep window is completely driven by the real-time state of the controlled object, completely avoiding the energy waste caused by a fixed cycle; the dual-mode dynamic complementarity reduces more than 70% of invalid wake-ups and ensures a low event response delay;

[0015] The static power consumption is reduced from the microampere level to the nanoampere level, and the energy efficiency is improved by two orders of magnitude; the interrupt response speed is increased by 10 times, meeting the stringent requirements of industrial control for timing certainty; The entire process of sensor data processing is without MCU intervention, reducing the software wake-up frequency; the control response skips the operating system recovery process to achieve millisecond-level real-time control of "wake up and execute". Dual-mode redundancy guarantee ensures 100% effective capture of instructions, especially suitable for complex working condition scenarios such as industrial vibration and temperature change.

[0016] In summary, the present invention does not require processor scheduling from data acquisition, state prediction to power management, subverting the operation mode dominated by the software stack in traditional low-power solutions, and realizing the coexistence of nanoampere-level standby current and millisecond-level event response in the controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of an embodiment of the low-power control method of the controller in the embodiment of the present invention; Figure 2 It is a schematic diagram of an embodiment of the low-power control system of the controller in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The embodiments of the present invention provide a low-power control method and system for a controller to implement a full-link hardware of prediction-sleep-wake-up-response in the controller. Terms such as "first", "second", "third", "fourth", etc. (if any) in the specification, claims and above-mentioned drawings of the present invention are used to distinguish similar objects and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order different from that shown or described here. In addition, the terms "include" or "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0019] For easy understanding, the specific process of the embodiments of the present invention is described below. Please refer to Figure 1 , an embodiment of the low-power control method of the controller in the embodiments of the present invention includes: 101. Hardware cache construction: Real-time collect the timing state data of the controlled object through the sensor interface circuit and store it in the hardware queue register group; It can be understood that the execution subject of the present invention can be the low-power control system of the controller, or a terminal or a server, and specific limitations are not made here. The embodiments of the present invention are described by taking the server as the execution subject as an example.

[0020] It should be noted that based on the industrial motor temperature control scenario: for the hardware structure design, the sensor interface circuit: a 4-channel differential input interface is constructed using TI's ADS1118 16-bit ADC chip, supporting a range of ±2.048V (corresponding to the -50°C to 150°C range of the PT100 temperature sensor). The interface circuit integrates an instrumentation amplifier (INA128) and an RC low-pass filter (cutoff frequency 50Hz) to eliminate motor electromagnetic interference.

[0021] Queue register group: Using the built-in Block RAM resources of the Xilinx Artix-7 FPGA, it is configured as a circular buffer with a depth of 128×32bit. Each group of registers contains: Timestamp register: 32-bit system clock count (precision 10μs); Temperature value register: 16-bit fixed-point number (the high 12 bits are integers, and the low 4 bits are decimals); Status flag register: 8-bit fault code (such as over-temperature / vibration anomaly, etc.); Data acquisition process, timing trigger: A sampling pulse is generated every 10ms (synchronized by the hardware timer) to start the ADC conversion (conversion time 128μs).

[0022] Data preprocessing: The ADC raw value (0~32768) is converted to °C value by the hardware multiplier ×0.015625 (implemented by shifting right 6 bits), and the status flag is set when out of range.

[0023] Circular write mechanism: The write pointer automatically increments, and when the pointer reaches 0x7F, it wraps around to 0x00, and the old data is overwritten (retaining the most recent 1.28s of data).

[0024] Low-power optimization feature, dynamic power gating: When idle, the ADC reference voltage source is turned off (saving 3.5mA of current), and only the register group is powered (leakage current <1μA).

[0025] Clock gating technology: The sensor interface clock is automatically turned off after data storage is completed (reducing dynamic power consumption by 42%).

[0026] Abnormal data compression: When the temperature change is ≤0.5°C for 5 consecutive times, the incremental storage mode is enabled (only the change amount + time difference is recorded).

[0027] 102. Predictive collaborative hardware calculation: The data in the hardware queue register group is input into the predictive collaborative calculation unit (PCCU). This unit is composed of dedicated digital logic circuits solidified in the integrated circuit, executes the physical prediction algorithm of the non-machine learning model, and outputs the predicted sleep window value; It should be noted that based on the industrial motor temperature control scenario, the PCCU hardware architecture: Core computing unit: dual-channel arithmetic logic unit (ALU) parallel computing, the main channel performs temperature change rate calculation (ΔT / Δt), the auxiliary channel calculates the second-order derivative (d 2 T / dt 2 ). The hardware is implemented by a 55nm custom ASIC, including: Differential calculation circuit: read the latest temperature value (16-bit fixed-point number) from the register group every 10ms and subtract it from the previous data (delay 3ns); Proportional multiplier: multiplies ΔT by the preset coefficient K (K=0.12, corresponding to the motor heat capacity of 125J / ℃), and outputs the accumulated power; Threshold comparator: When the calculation result is ≥ the safety threshold (85°C), the over-temperature flag is triggered; Prediction algorithm solidification: Implementing physical thermodynamic models: ; in, =100℃ (motor insulation limit), Take the sliding average of the last five sampling points (to suppress noise); Real-time calculation process, data input: extract 10 consecutive temperature values (time span 100ms) from the hardware queue register group with a depth of 128; Automatically filter abnormal points: If the deviation of a certain point is greater than ±3°C (vibration interference), the previous value replacement mechanism is activated; Physics Predictive Execution: Step 1: Calculate the instantaneous rate of change ( is the data 100ms ago); Step 2: Match the preset coefficients through the hardware look-up table (LUT): like >5℃ / s→coefficient α=0.8 (forced cooling mode); If 0.5< ≤5℃ / s→α=1.2 (linear prediction); Step 3: Output the predicted value, ; Output constraints: The minimum value is limited to 10ms (to prevent false triggering); The maximum value is limited to 600s (compatible with the device in standby mode); The high 8 bits of the 16-bit output register are integer seconds, and the low 8 bits are 0.1 second precision; Low power optimization features: Event-driven computing: the operation is started only when the register group update flag is set (static power consumption < 5μW); Data stream compression: When 5 consecutive When the temperature is <0.2°C, it automatically switches to the incremental calculation mode (power consumption reduced by 63%); Adaptive clock gating: Immediately turn off the clock tree after the computing unit completes the operation (reducing dynamic power consumption by 42%).

[0028] Through dedicated hardware that solidifies the thermodynamic model, physical prediction is completed in the microsecond level, eliminating the energy consumption of frequent wake-ups in traditional MCU solutions. The key innovation lies in the combination of moving average filtering and coefficient adaptive mechanism, achieving sub-milliwatt power consumption while ensuring prediction accuracy, providing high-reliability input for subsequent sleep decisions.

[0029] 103. Extended instruction set control: Execute the PREDSLP special instruction in the processor instruction set, and write the predicted sleep window value into the sleep configuration register; It should be noted that the hardware architecture design: Definition of special instruction: The PREDSLP instruction is a 32-bit RISC-V extended instruction (Opcode is customized as 0x7B), belonging to the "privileged instruction set" extension. Its function is to write the predicted sleep window value (16-bit fixed-point number, unit 10ms) from the general-purpose register a0 to the sleep configuration register (SCR). Instruction format: PREDSLPa0; Among them, the high 16 bits are reserved, and the low 16 bits store the sleep window value (for example, 0x00C8 represents 2 seconds of sleep).

[0030] Sleep configuration register (SCR): Mapped to the memory address 0x4000_8000, 32-bit wide, the low 16 bits store the sleep window value, and the high 16 bits reserve the status flag (wake-up interrupt trigger bit).

[0031] Operation process (taking the predicted sleep window = 2 seconds as an example): Preparation of predicted value: The PCCU calculates that the sleep window is 2000ms (corresponding to the hexadecimal value 0x00C8) and stores it in the general-purpose register a0.

[0032] Instruction execution: The processor executes the PREDSLPa0 instruction: Decoding stage: Identify the 0x7B opcode and activate the SCR write path.

[0033] Execution stage: Latch the low 16 bits of a0 (0x00C8) to the low 16 bits of the SCR.

[0034] Register update: The SCR value is updated to 0x0000_00C8, triggering subsequent operations: If the value > the threshold (1 second), the DIG unit turns off the power supply of the CPU instruction fetch / decode circuit; The programmable timing generator synchronously receives the SCR value and dynamically adjusts the duty cycle of the receiving window.

[0035] Low-power optimization feature, single-cycle completion: The SCR is directly connected to the register bus in hardware, and the instruction execution takes only 1 clock cycle (20 ns at 50 MHz), saving 87% latency compared to traditional memory-mapped I / O.

[0036] Static power consumption control: The SCR is designed with high-threshold voltage (HVT) cells, and the static current is as low as 0.5 μA.

[0037] Security check: Automatically checks the value range (10 ms to 600 s) before writing, and triggers an exception interrupt when the limit is exceeded.

[0038] Implement hardware-level sleep parameter injection through custom instructions, eliminating the multi-instruction overhead of traditional store-load-write. The key innovation is to use the SCR as an extension of the processor register space, combined with the characteristics of the RISC-V modular instruction set, to reduce the control power consumption to the microjoule level while ensuring real-time performance.

[0039] 104. Pipeline circuit gating: According to the value of the sleep configuration register, perform the following operations through the dynamic instruction gating unit (DIG): When the value is greater than the threshold, turn off the power supply of the CPU's instruction fetch circuit and decoding circuit; when the value is less than the threshold, keep the instruction fetch circuit and decoding circuit in the active state; generate the gating pipeline state signal; It should be noted that the DIG hardware architecture design: Gating unit structure: Adopt a latch-based gating cell, which consists of a level-sensitive latch and an enable signal control circuit. When the value of the sleep configuration register (SCR) > 1 second (threshold), trigger the clock AND gate to turn off the clock signal of the instruction fetch / decoding circuit; at the same time, cut off the power supply (3.3 V → 0 V) through the PMOS power switch, and the static leakage current < 0.8 μA.

[0040] Status signal generator: Integrate a comparator circuit to monitor the SCR value in real time and output two signals: GATE_STAT1: Instruction fetch circuit gating status (high level = active); GATE_STAT2: Decoding circuit gating status (high level = active); Dynamic gating process (taking the sleep window = 2 seconds as an example): Threshold judgment: The SCR value 0x00C8 (2 seconds) > the threshold 0x0064 (1 second), and the DIG unit enables the gating operation.

[0041] Clock and power synchronous shutdown: Clock gating: The latch captures the low-level enable signal to block the clock tree from transmitting to the fetch / decode circuit; Power gating: The PMOS switch cuts off the power supply, and the power consumption of the fetch circuit drops suddenly from 15 mW to 0.2 mW.

[0042] Status signal update: Generate GATE_STAT1 = 0, GATE_STAT2 = 0, indicating that the pipeline enters the sleep mode.

[0043] Energy efficiency optimization design, hierarchical shutdown strategy: Fetch circuit: Shut down after 50 ns delay (to avoid instruction prefetch conflicts); Decode circuit: Shut down immediately (no dynamic tasks); Wake-up pre-synchronization mechanism: Maintain the power supply of the latch state refresh circuit during sleep to ensure that the clock phase synchronization is restored within 5 μs when waking up.

[0044] The performance data is as shown in Table 1 below: Table 1

[0045] Through hardware-level clock / power dual gating, non-essential circuits are completely shut down during the steady operation of the motor. The key innovation lies in combining the latch-type gating unit with the hierarchical shutdown strategy, which controls the standby power consumption of the pipeline at the micro-watt level while ensuring the wake-up real-time performance (<5 μs), saving more than 98% energy compared with the traditional scheme.

[0046] 105. Dynamically generate communication timing: Based on the value of the sleep configuration register, generate the control signal of the receiving module through the programmable timing generator, including: when the value is greater than the safety threshold, output the extended sleep timing signal (the duty cycle of the receiving window ≤ 5%); when the value is less than the safety threshold, output the precise wake-up timing signal (activate the receiving circuit 10 ms before the predicted event occurs); It should be noted that the programmable timing generator adopts a dual-clock domain architecture, integrating a 32 kHz low-power clock (running during sleep) and a 50 MHz system clock (running during activation). Dynamically switch the working mode through the 16-bit value (unit: 10 ms) of the sleep configuration register (SCR), and the safety threshold is set to 2000 ms (corresponding to the SCR value 0x00C8).

[0047] Control signal logic: When the SCR value > 2000 ms (temperature stable state), trigger the extended sleep timing: Generate a square wave with a period of 400 ms and a receiving window of 20 ms (duty cycle = 5%), and the receiving module is only activated within the 20 ms window.

[0048] When the SCR value ≤ 2000 ms (temperature mutation risk), trigger the precise wake-up timing: Based on the overheat time point predicted by PCCU, generate a 50ms activation window 10ms in advance (if the predicted overheat moment t = 5000ms, start the receiving circuit at t - 10ms = 4990ms).

[0049] Dynamic timing generation process, threshold judgment: The timing generator reads the SCR value every 10ms (example: SCR = 0x012C → sleep window = 3000ms > 2000ms).

[0050] Mode switching: Extended sleep mode: Output an RX_EN signal with a period of 400ms and a pulse width of 20ms. The receiving module only works for 20ms every 400ms.

[0051] Precise wake-up mode: Calculate the activation moment in real time = predicted event timestamp - 10ms (if it is predicted that the motor will overheat at 6050ms, output a high-level RX_EN at 6040ms for 50ms).

[0052] Power consumption optimization: Turn off the 50MHz clock tree during sleep, and only keep the 32kHz clock powered (static current 1.2μA).

[0053] By dynamically switching the receiving timing strategy, achieve ultra-low duty cycle (5%) listening when the motor is in a steady state, and ensure 10ms-level precise wake-up under mutation risks. The key innovation lies in combining the real-time calculation of the predicted event timestamp, reducing the communication power consumption to less than 17% of the traditional polling scheme.

[0054] 106. Hardware interrupt recovery: When the receiving module captures a valid instruction, send an interrupt request to the CPU through the asynchronous wake-up circuit, restore the power supply of the instruction fetch circuit and the decoding circuit, and execute the control response.

[0055] It should be noted that for the design of the asynchronous wake-up circuit and the interrupt trigger mechanism: When the receiving module (NRF52840) captures the "emergency stop" instruction (instruction code 0xAA55), trigger a high-level pulse (width ≥ 5μs) through the GPIO13 pin. The asynchronous wake-up circuit uses a level-sensitive latch, which immediately activates the interrupt request line (IRQ) when detecting the high level, regardless of the CPU sleep state.

[0056] Power supply recovery logic: The wake-up circuit outputs two control signals: Clock enable signal: Directly connect to the dynamic instruction gating unit (DIG) to restore the clock supply (50MHz) of the instruction fetch / decoding circuit; Power enable signal: Control the PMOS switch (SI2312 chip) to restore the 3.3V power supply to the CPU pipeline circuit within 200ns; Interrupt handling process, interrupt capture: When the motor overheats, the cloud sends a shutdown command (command code 0xAA55). The receiving module captures the command within the precise wake-up window (10ms activation period) and triggers an asynchronous wake-up signal.

[0057] Status recovery: Power supply recovery: After the PMOS switch conducts, the power supply to the instruction fetch circuit and decoding circuit rises from 0.15mW to 15mW (takes 1.5μs); Pipeline activation: The DIG unit releases the gated state and generates GATE_STAT = 0x3 (the high 2 bits indicate the activation of the instruction fetch / decoding circuit); Interrupt response: The CPU resumes execution from the sleep address 0x8000F000, jumps to the interrupt vector table (address 0x00000000), and calls the emergency shutdown service program: turns off the motor drive power supply (sets the IO pin to low level); starts the cooling fan (PWM duty cycle 100%); sends the status code 0xE0 to the cloud (through the SPI interface); The performance indicators are as shown in Table 2 below: Table 2

[0058] Scenario: When the motor is stalled and overheats, the total time from instruction capture to shutdown execution is ≤54μs, which is faster than the traditional polling scheme. The static current of the asynchronous wake-up circuit is only 0.8μA, avoiding additional energy consumption during the sleep period.

[0059] This embodiment completes the full response chain from sleep to execution within 5μs through a hardware-level asynchronous wake-up circuit and state machine control. The core innovation lies in the collaborative design of level-sensitive latches and power gating, which controls the standby power consumption at the microamp level while ensuring μs-level interrupt response.

[0060] Please refer to Figure 1 , another embodiment of the low-power control method for the controller in the embodiment of the present invention includes: 101. Hardware cache construction: Real-time collect the timing status data of the controlled object through the sensor interface circuit and store it in the hardware queue register group; Specifically, the temperature, pressure, and displacement sensor data are collected simultaneously through a parallel ADC interface to generate per-channel data packets. The per-channel data packets are input into a threshold comparator circuit to eliminate data beyond the physical range, and an effective data queue is output. The effective data queue is synchronized from the sensor clock domain to the system clock domain through a dual-port asynchronous FIFO memory to generate synchronized data packets. According to the real-time calculation requirements of the Prediction and Cooperative Computing Unit (PCCU), the synchronized data packets are written into the specified storage partition of the hardware queue register group by the DMA controller to generate a timing status data matrix (the timing status data matrix is used as the input of 102).

[0061] It should be noted that for the sensor interface configuration and parallel ADC acquisition: Three independent ADC modules (ADC1 / 2 / 3) are used for synchronous sampling: ADC1 channel 5 (PA0) is connected to a temperature sensor (PT100, range -40~125°C); ADC2 channel 6 (PA1) is connected to a pressure sensor (0 - 10MPa); ADC3 channel 7 (PA2) is connected to a displacement sensor (0 - 100mm); The TIM3 timer is configured to trigger (sampling rate 100kHz) with 12-bit resolution; Output format of per-channel data packets: [Temperature ADC value (16-bit) | Pressure ADC value (16-bit) | Displacement ADC value (16-bit)]; Threshold screening circuit and range protection design: Threshold comparator parameters (based on LM393): Temperature threshold: 0.88V (-40°C) ~ 3.0V (125°C); Pressure threshold: 0.5V (0MPa) ~ 2.5V (10MPa); Displacement threshold: 0.3V (0mm) ~ 3.0V (100mm); Hardware implementation scheme: A hysteresis comparator circuit is adopted; Resistance configuration: R1 = 20kΩ, R2 = 4.3kΩ, R3 = 11.2kΩ, R4 = 46kΩ; Data beyond the range is marked as 0xFFFF and is eliminated in real time by the FPGA logic circuit; Clock domain synchronization and asynchronous FIFO design: Dual-port FIFO parameters: Depth 1024 words (18-bit width); Write clock: Sensor clock domain (100kHz); Read clock: System clock domain (72MHz); Synchronization mechanism: Gray code pointer conversion to avoid metastability; empty / full flag bit cross-clock domain synchronization; the output synchronous data packet format is the same as the input; Data matrix generation, DMA hardware acceleration: Configure DMA2 Stream0: Source address: FIFO read port (0x40026000); Destination address: Hardware queue register group (0x2001FC00); Transfer mode: Burst transfer (4 groups of data packets each time); Register group partitioning: 0x2001FC00 - 0x2001FC7F: Temperature data area (128 words); 0x2001FC80 - 0x2001FCFF: Pressure data area (128 words); 0x2001FD00 - 0x2001FD7F: Displacement data area (128 words); Trigger PCCU calculation condition: When the data volume of a certain partition ≥ 64 groups, set the status register flag bit.

[0062] 102. Predictive collaborative hardware calculation: Input the data in the hardware queue register group into the Predictive Collaborative Computing Unit (PCCU), which is composed of dedicated digital logic circuits solidified in the integrated circuit, executes physical prediction algorithms for non-machine learning models, and outputs predictive sleep window values; Specifically, extract timing status data from the hardware queue register group through a parallel multiplexer and convert it into a fixed-point data stream; input the fixed-point data stream into a shift-accumulator array to perform differential operations with a preset fractional order α and output fractional difference values; input the fractional difference values into a hysteresis loop parameter lookup table and output hysteresis response flag bits based on the Preisach hysteresis model; fuse the fractional difference values and hysteresis response flag bits through a window generation state machine to generate predictive sleep window values (as the input of step 103) and write them into the output register.

[0063] It should be noted that taking an industrial temperature control system as the scenario, the controlled object is the temperature of the heating furnace, and the sensor data includes temperature (range 0 - 100 °C), pressure (0 - 10 kPa), and displacement (0 - 50 mm). The PCCU (Predictive Collaborative Computing Unit) executes physical prediction algorithms through dedicated digital logic circuits and outputs predictive sleep window values. The specific implementation is as follows: Data extraction and fixed-point conversion, input data source: The hardware queue register group stores a timing status data matrix, including the most recent 64 groups of sampling data (sampled once every 100 ms): Temperature data: 32 sets of fixed-point numbers (Q16 format, 16 bits for integer part and 16 bits for decimal part), the range corresponds to 0-100℃ (25.5℃ is converted to 0x19800000).

[0064] The parallel multiplexer extracts data from the register group: selects the temperature channel data stream (highest priority) and outputs the fixed-point data stream through a 4:1 multiplexer. The conversion takes ≤50ns.

[0065] Fractional differentiation operation, shift-accumulator array configuration: The preset fractional order α=0.7 (for slow dynamic characteristics of temperature changes).

[0066] The array consists of 8 shift-accumulate units in parallel, each performing fractional differentiation: ; The weight coefficient Solidified in ROM ( =0.7, =0.2, =0.08, =0.02).

[0067] Output example: Input temperature data stream [25.5, 26.0, 26.2]℃, after calculation, the output fractional-order difference value is 0.15 (fixed-point number 0x00018000), and the operation delay is 200ns.

[0068] Generation of hysteresis response flag, hysteresis loop parameter lookup table: Based on the Preisach hysteresis model, the lookup table stores 256 entries corresponding to hysteresis responses of different differential value ranges.

[0069] Parameter definition: temperature rising threshold = 0.1℃ / ms, falling threshold = 0.08℃ / ms.

[0070] Logical judgment: If the fractional-order differential value ≥ the rising threshold (0.15 > 0.1), the output hysteresis response flag bit 1 (indicating that the temperature rises rapidly); otherwise, the output is 0.

[0071] Hardware implementation: The lookup table is implemented using a combinational logic circuit (AND gate array) with an access time of 20ns.

[0072] Dormant window value generation, window generation state machine: The state machine contains 3 states (IDLE, CALC, OUTPUT), and the dormant window is calculated based on the differential value and the flag bit fusion.

[0073] Fusion rule: If the flag bit = 1 (accelerated rise), the sleep window = basic window × (1 - difference value) × safety factor.

[0074] If the flag bit = 0 (stable), the sleep window = the base window × 1.2 (extended sleep).

[0075] Specific calculation: The base window = 100 ms, the input differential value is 0.15, the flag bit is 1, and the output sleep window value is 85 ms (fixed-point number 0x55).

[0076] Write to the output register: Store the value through a 32-bit output register (address 0x4000F000), and the write time is 10 ns.

[0077] 103. Extended instruction set control: Execute the PREDSLP special instruction in the processor instruction set, and write the predicted sleep window value to the sleep configuration register; Specifically, instruction decoding trigger: Identify the PREDSLP opcode through the instruction decoder circuit to generate a register operation enable signal; Address mapping conversion: According to the register number field in the PREDSLP instruction, convert it to the physical storage address of the sleep configuration register through the address mapping table circuit; Data bus transmission: Load the predicted sleep window value to the dedicated data bus channel, and write it to the target physical storage address under the control of the register operation enable signal to generate a register write completion flag; Low-power state switching: According to the register write completion flag, switch the system from the running state to the predicted sleep state (trigger condition of 104) through the power state controller.

[0078] It should be noted that the dedicated instruction integration: PREDSLP instruction encoding: 0xF1A0_000X (the high 16 bits are the opcode, and the low 4 bits X are the target register number); Sleep configuration register address: 0x4000_01F0 (32-bit register, stores the sleep window value); Power state controller: Integrated in the power management unit (PWR), supporting the switch from the running state (4.2 mA) to the predicted sleep state (1.3 μA); Instruction execution flow, instruction decoding trigger: When the CPU executes the PREDSLP R2 instruction (R2 stores the predicted value 85 ms / 0x55): The instruction decoder identifies the opcode 0xF1A0 and generates a register operation enable signal (active high); Clock synchronization delay: ≤3 ns (system clock 72 MHz); Address mapping conversion: Register number field parsing: Extract the low 4 bits 0x2 of the instruction (corresponding to R2); Hardware implementation of address mapping table: Input register number: 0x2 → Mapped table output physical address: 0x4000_01F8; (Offset + 8, because each sleep register occupies 4 bytes); Conversion time: Implemented by combinational logic circuit, with a delay of 2 ns; Data bus transmission, data transmission path: [Register R2] →|Dedicated 32-bit bus| →[Sleep configuration register]; Key timing parameters: Width of register enable signal: 10 clock cycles (about 139 ns); Data setup time: Load the value 0x55 5 ns before the rising edge of the enable signal; Generation of write completion flag: Set at the falling edge of the enable signal (flag address 0x4000_01FF); Low-power state switching, actions of the power consumption state controller: After detecting the write completion flag, start the state switching sequence; Execution order: Turn off the core voltage regulator (VCORE drops from 1.2V to 0.9V); Freeze the system clock (HCLK / PCLK stops); Keep the backup domain powered (RTC continues to run); Switching time: 8 μs (from flag setting to entering Stop mode); Energy consumption comparison (input predicted value 85 ms) is as shown in Table 3 below: Table 3

[0079] 104. Pipeline circuit gating: According to the value of the sleep configuration register, perform the following operations through the dynamic instruction gating unit (DIG): When the value is greater than the threshold, turn off the power supply of the CPU's instruction fetch circuit and decoding circuit; when the value is less than the threshold, keep the instruction fetch circuit and decoding circuit active; generate the gating pipeline state signal; Specifically, threshold hardware comparison: The value of the sleep configuration register is compared with the preset threshold voltage in real time through a voltage comparator circuit to generate a power supply control signal; Instruction fetch circuit gating: When the power supply control signal is at a high level, control the first MOS transistor array to physically disconnect the power supply path of the instruction fetch circuit to generate a sleep state of the instruction fetch circuit; Decoding circuit gating: When the power supply control signal is at a high level, control the second MOS transistor array to physically disconnect the power supply path of the decoding circuit to generate a sleep state of the decoding circuit; Status signal encoding: The sleep state of the instruction fetch circuit and the sleep state of the decoding circuit are fused through a hardware status encoder, and a 2-bit gated pipeline status signal (used as the basis for interrupt recovery) is output to the pipeline status register.

[0080] It should be noted that the core parameters: Sleep configuration register address: 0x4000_01F0 (32 bits, storing the predicted sleep window value); Threshold voltage: 1.0V (corresponding to the value 0x32, i.e., a 50ms threshold); MOS transistor array: SI2301 MOSFET (on-resistance 0.1Ω, off-state leakage current <1μA); System power supply voltage: 1.2V (CPU core voltage); Gating execution process, threshold hardware comparison: When the value of the sleep configuration register is 0x64 (100ms): The voltage comparator (LM393) converts the register value to 1.8V through DAC (the full scale of 3.3V corresponds to 200ms); Compare with the preset threshold voltage of 1.0V (0x32), and output a high-level power supply control signal (logical 1); Response time: 20ns (typical value); Instruction fetch circuit gating, the power supply control signal drives the first MOS transistor array (Q1-Q4): Physically disconnect the 1.2V power supply path of the instruction fetch circuit; The current drops from 4.2mA in the running state to 0.9mA in the sleep state; The status register marks the instruction fetch circuit as in the sleep state (status bit FETCH_SLP = 1); Decoding circuit gating, synchronously control the second MOS transistor array (Q5-Q8): Disconnect the 1.2V power supply of the decoding circuit; The current drops from 3.8mA to 0.85mA; Status mark DECODE_SLP = 1; Status signal encoding, input of the hardware status encoder (74HC148): FETCH_SLP = 1, DECODE_SLP = 1 → Output encoding "11b"; Write to the pipeline status register (lower 2 bits of address 0x4000_01F4); Encoding delay: ≤5 ns; The test data is as shown in Table 4 below: Table 4

[0081] 105. Communication timing dynamically generated: Based on the value in the sleep configuration register, the control signals for the receiving module are generated by a programmable timing generator, including: when the value is greater than the safety threshold, output an extended sleep timing signal (the duty cycle of the receiving window ≤5%); when the value is less than the safety threshold, output a precise wake-up timing signal (activate the receiving circuit 10 ms before the predicted event occurs); Specifically, sleep coefficient calculation: Extract the lower 8 bits of the value in the sleep configuration register through a shift register group to generate a sleep coefficient value; basic beat generation: Divide the system clock by a clock divider circuit into a 100 ms periodic signal as the reference timing signal; dynamic period extension: Input the sleep coefficient value and the reference timing signal into a programmable counter to generate an extended sleep timing signal, satisfying: ; Precise wake-up alignment: When the value in the sleep configuration register is less than the safety threshold, execute through a hardware timestamp aligner: Read the occurrence time of the event in the predicted event queue; Activate the wake-up circuit 10 ms before the event occurs to generate a 10 ms precise wake-up pulse; Signal synthesis output: Select the extended sleep timing signal or the precise wake-up pulse through a multiplexer circuit to generate the final receiving control signal to the module.

[0082] It should be noted that for sleep coefficient calculation, the input is: the value in the sleep configuration register (e.g., predicted sleep window 85 ms → hexadecimal value 0x55); Operations: Shift register group extracts the lower 8 bits: 0x55 & 0xFF = 0x55 (decimal 85); Sleep coefficient value (Sleep_Coeff) = 0x55 (directly used for subsequent calculations); For basic beat generation, hardware configuration: Clock divider parameters: Input a 72 MHz system clock, division ratio 720 → Output a 100 Hz signal (period 100 ms); Reference timing signal (Base_CLK): 100 ms square wave, duty cycle 50%; Dynamic cycle extension, condition: sleep value 85ms > safety threshold 50ms → trigger extended sleep mode; Programmable counter operation: ; Receive window opening time: fixed 100ms (duty cycle calculation: 100ms / 8500ms × 100% ≈ 1.18%); Output signal: generate a 100ms receive window every 8.5 seconds, and turn off the receive circuit for the rest of the time; Precise wake-up alignment, condition: if the sleep value drops to 30ms (0x1E) < 50ms → trigger precise wake-up mode; Hardware timestamp aligner operation: read the predicted event queue (example: temperature mutation event is expected to occur at t+205ms); activate the wake-up circuit at t+195ms (10ms in advance); generate a 10ms-wide wake-up pulse (high level valid); Signal synthesis output, multiplexer logic: sleep value > 50ms: select extended sleep timing signal (duty cycle 1.18%); Sleep value ≤ 50ms: select precise wake-up pulse (10ms width); Final output: RX_EN pin of the control module (SX1276): turn on reception when at high level; Performance measured data (in 25°C environment) is as shown in Table 5 below: Table 5

[0083] 106. Hardware interrupt recovery: When the receive module captures a valid instruction, it sends an interrupt request to the CPU through the asynchronous wake-up circuit, resumes the power supply of the instruction fetch circuit and the decoding circuit, and executes the control response.

[0084] Specifically, instruction validity verification: The baseband processor of the receiving module performs cyclic redundancy check (CRC) circuit verification on the received data packet to generate a valid instruction flag signal; Asynchronous wake-up trigger: Input the valid instruction flag signal into the edge detection circuit to generate a wake-up trigger pulse; Power recovery control: The wake-up trigger pulse drives the power gating driver to output the power supply enable signal for the instruction fetch circuit and the power supply enable signal for the decoding circuit; Interrupt vector generation: At the same time as the power supply is restored, a non-maskable interrupt vector number is generated by the interrupt controller hardware and written into the interrupt vector register; Control instruction direct pass: The valid instruction is transferred from the receive buffer to the actuator control register through the direct memory access (DMA) channel to generate a copy of the instruction to be executed; Interrupt service jump: After the power supply of the instruction fetch circuit is restored, the CPU reads the vector number from the interrupt vector register, jumps to the hard-coded interrupt service program, reads the copy of the instruction to be executed in the actuator control register, and outputs a control response signal to the actuator.

[0085] It should be noted that the scenario setting: The temperature control system of the heating furnace, the CPU is in the predicted sleep state (the instruction fetch / decoding circuit is powered off), the sleep configuration register value is 85 ms (0x55), and the system clock is 72 MHz. The module is SX1276 (LoRa communication).

[0086] Instruction validity verification, the module receives an instruction: Received data packet: 0x3A 01 25 00 3C (instruction header 0x3A, set temperature 25 °C, target value 60 °C); CRC check: The baseband processor performs CRC-16 check (polynomial 0x1021), calculates the check code 0x4F29, which matches the last two bytes of the data packet → generates a valid instruction flag signal (high level); Response time: < 500 μs (hardware CRC circuit acceleration); Asynchronous wake-up trigger, edge detection circuit (SN74LVC1G17): Input the valid instruction flag signal (rising edge) → output a wake-up trigger pulse with a width of 10 μs; Key parameter: Propagation delay 15 ns, meeting the requirement of fast wake-up; Power recovery control, power gating driver (TPS22918 load switch): The wake-up pulse drives the MOS transistor array: The first path: Turn on the power supply of the instruction fetch circuit (enable signal FETCH_PWR_EN = 1); The second path: Turn on the power supply of the decoding circuit (enable signal DECODE_PWR_EN = 1); Current change: 1.2 μA in the sleep state → 4.2 mA in the restored state (completed within 20 μs); Interrupt vector generation, interrupt controller (NVIC hardware module): Generate a non-maskable interrupt vector number 0x0000_000F (highest priority) simultaneously when power supply resumes; Write to the interrupt vector register (address 0xE000_ED08); Delay: < 100 ns (hardware direct connection path); Control instruction direct pass-through, DMA channel transfer (STM32 DMA2): Source address: receive buffer 0x2000_8000; Destination address: actuator control register 0x4000_2000 (heating power adjustment register); Transferred content: valid instruction 0x25 (25 °C) → generate a copy of the instruction to be executed; Transfer time: 2 μs (burst transfer mode); Interrupt service jump, CPU response process: After the instruction fetch circuit power supply resumes, read the vector number 0x0000_000F from 0xE000_ED08; Jump to the hard-coded ISR entry address 0x0800_1F00; The ISR reads the value 0x25 of the actuator control register and outputs a PWM control signal to the heater (duty cycle 40%); Total response delay: from wake-up to output of the control signal ≤ 50 μs; Performance measured data (25 °C environment) is as shown in Table 6 below: Table 6

[0087] In the embodiments of the present invention, a parallel ADC interface (ADC1 / 2 / 3) is used to synchronously collect temperature, pressure, and displacement data, and a hysteresis comparator circuit is combined to achieve hardware-level outlier rejection; an asynchronous FIFO design (depth 1024 words, Gray code pointer) solves the cross-clock domain transmission problem, triples the data synchronization efficiency, and the FPGA is used to reject out-of-range data (marked as 0xFFFF) in real time to ensure the reliability of subsequent calculations; the fractional-order differential operation (α = 0.7) and the Preisach hysteresis model are solidified in the digital logic circuit, and a 200-ns delay real-time calculation is achieved through an 8-cell shift-accumulator array; the window generation state machine dynamically adjusts the sleep window according to the difference value and the hysteresis flag (shortens to 85 ms when the temperature accelerates upward), enabling the prediction accuracy to reach ±5 ms, significantly better than the traditional fixed-time sleep strategy; a dedicated PREDSLP instruction (encoding 0xF1A0_000X) is developed, and the predicted value is directly written to the sleep configuration register through a hardware address mapping table (register number → physical address conversion delay 2 ns); a dual MOS transistor array (SI2301) physically powers off the instruction fetch / decode circuit, and a 2-bit gating signal is output in combination with a hardware status encoder ("11b" indicates dual-circuit sleep).

[0088] The low-power control method of the controller in the embodiments of the present invention has been described above. Next, the low-power control system of the controller in the embodiments of the present invention will be described. Please refer to Figure 2 An embodiment of the low-power control system of the controller in the embodiments of the present invention includes: an acquisition module 201, configured to collect the timing state data of the controlled object in real time and store it in the hardware queue register group; a sleep module 202, configured to input the data in the hardware queue register group into the prediction collaborative calculation unit, which is composed of a digital logic circuit solidified in an integrated circuit, and output the predicted sleep window value; a writing module 203, configured to execute the PREDSLP instruction in the processor instruction set and write the predicted sleep window value into the sleep configuration register; a gating module 204, configured to generate a gating pipeline state signal through a dynamic instruction gating unit according to the value of the sleep configuration register; a recovery module 205, configured to generate a control signal for the receiving module through a programmable timing generator based on the value of the sleep configuration register; an allocation module 206, configured to send an interrupt request to the CPU through an asynchronous wake-up circuit when the receiving module captures a valid instruction, restore the power supply of the instruction fetch circuit and the decode circuit, and execute a control response.

[0089] In the embodiments of the present invention, by predicting the output of the prediction cooperation calculation unit to obtain the predicted sleep window value, the system sleep time can be accurately predicted based on the sequential state data of the controlled object, avoiding unnecessary continuous operation and effectively reducing the system power consumption; the prediction cooperation calculation unit is composed of digital logic circuits solidified in an integrated circuit, and by executing instructions of a specific processor instruction set (PREDSLP instruction) to write into the sleep configuration register and other means, part of the control logic is hardwareized, reducing complex operations and calculation overhead at the software level; according to the value of the sleep configuration register, a gated pipeline status signal is generated by the dynamic instruction gating unit to implement dynamic gating of the pipeline. This flexible control method can adjust the working state of the pipeline in real time according to the actual running state of the system, and effectively reduce the pipeline power consumption without affecting the system function; a receiving module control signal is generated based on the value of the sleep configuration register. When the receiving module captures a valid instruction, an interrupt request is sent to the CPU through the asynchronous wake-up circuit to restore the power supply of the instruction fetch circuit and the decoding circuit and execute the control response. This not only ensures that the system can respond in time when needed but also avoids the system being in a high-power active state for a long time, achieving a good balance between power consumption and response speed.

[0090] The present invention also provides a low-power control device for a controller. The low-power control device for the controller includes a memory and a processor. Computer-readable instructions are stored in the memory. When the computer-readable instructions are executed by the processor, the processor executes the steps of the low-power control method for the controller in the above-mentioned embodiments.

[0091] The present invention also provides a computer-readable storage medium. The computer-readable storage medium can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When the instructions run on a computer, the computer executes the steps of the low-power control method for the controller.

[0092] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0093] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0094] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of various embodiments of the present invention.

Claims

1. A low-power control method for a controller, characterized in that The low-power control method of the described controller includes: Collecting the timing status data of the controlled object in real time and storing it in the hardware queue register group; Inputting the data in the hardware queue register group into the prediction collaborative computing unit, which is composed of digital logic circuits solidified in the integrated circuit, and outputting the predicted sleep window value; Executing the PREDSLP instruction in the processor instruction set and writing the predicted sleep window value into the sleep configuration register; According to the value of the sleep configuration register, generating a gated pipeline status signal through the dynamic instruction gating unit; Based on the value of the sleep configuration register, generating a control signal for the receiving module through the programmable timing generator, including: Extracting the lower 8 bits of the value of the sleep configuration register through the shift register group to generate a sleep coefficient value; Dividing the system clock into a 100ms periodic signal through the clock frequency division circuit as the reference timing signal; Inputting the sleep coefficient value and the reference timing signal into the programmable counter to generate an extended sleep timing signal, satisfying: ； When the value of the sleep configuration register is less than the safety threshold, execute through the hardware timestamp aligner: Reading the event occurrence time in the prediction event queue; Activating the wake-up circuit 10ms before the event occurrence time to generate a 10ms precise wake-up pulse; Selecting the extended sleep timing signal or the precise wake-up pulse through the multiplexer circuit to generate the final receiving control signal; When the receiving module captures a valid instruction, sending an interrupt request to the CPU through the asynchronous wake-up circuit, restoring the power supply of the instruction fetching circuit and the decoding circuit, and executing the control response.

2. The low-power control method of the controller according to claim 1, wherein Including: Collecting the data of temperature, pressure, and displacement sensors and generating sub-channel data packets; Inputting the sub-channel data packets into the threshold comparator circuit, eliminating the data beyond the physical range, and outputting a valid data queue; Synchronizing the valid data queue from the sensor clock domain to the system clock domain to generate a synchronized data packet; According to the real-time calculation requirements of the prediction collaborative computing unit, the DMA controller writes the synchronized data packet into the specified storage partition of the hardware queue register group to generate a timing status data matrix.

3. The low-power control method of the controller according to claim 2, wherein Including: Extracting the timing status data from the hardware queue register group through the parallel multiplexer and converting it into a fixed-point data stream; Inputting the fixed-point data stream into the shift-accumulator array, performing the differential operation of the preset fractional order α, and outputting the fractional difference value; Inputting the fractional difference value into the hysteresis loop parameter lookup table and outputting the hysteresis response flag bit; Fusing the fractional difference value and the hysteresis response flag bit through the window generation state machine to generate the predicted sleep window value.

4. The low-power control method of the controller according to claim 3, characterized in that Including: Identifying the PREDSLP opcode through the instruction decoder circuit to generate a register operation enable signal; Converting it into the physical storage address of the sleep configuration register according to the register number field through the address mapping table circuit; Loading the predicted sleep window value onto the data bus channel and writing it into the target physical storage address under the control of the register operation enable signal to generate a register write completion flag; According to the register write completion flag, switching the system from the running state to the predicted sleep state through the power consumption status controller.

5. The low-power control method of the controller according to claim 4, characterized in that, Including: The voltage comparator circuit compares the value of the sleep configuration register with the preset threshold voltage in real time to generate a power supply control signal; When the power supply control signal is at a high level, control the first MOS transistor array to physically disconnect the power supply path of the instruction fetch circuit to generate a sleep state of the instruction fetch circuit; When the power supply control signal is at a high level, control the second MOS transistor array to physically disconnect the power supply path of the decoding circuit to generate a sleep state of the decoding circuit; Fuse the sleep state of the instruction fetch circuit and the sleep state of the decoding circuit through a hardware status encoder to output a 2-bit gated pipeline status signal.

6. The low-power control method of the controller according to claim 5, characterized in that, It includes: The baseband processor of the receiving module performs cyclic redundancy check circuit verification on the received data packet to generate a valid instruction flag signal; Input the valid instruction flag signal into the edge detection circuit to generate a wake-up trigger pulse; The wake-up trigger pulse drives the power gating driver to output an instruction fetch circuit power supply enable signal and a decoding circuit power supply enable signal; At the same time when the power supply is restored, generate a non-maskable interrupt vector number through the interrupt controller hardware and write it into the interrupt vector register; Transfer the valid instruction from the receive buffer to the actuator control register through the direct memory access channel to generate a copy of the instruction to be executed; After the power supply of the instruction fetch circuit is restored, the CPU reads the vector number from the interrupt vector register, jumps to the hard-coded interrupt service program, reads the copy of the instruction to be executed in the actuator control register, and outputs a control response signal.

7. A low-power control system for a controller, characterized in that, The low-power control system of the controller includes: An acquisition module for real-time collecting the timing state data of the controlled object and storing it in the hardware queue register group; A sleep module for inputting the data in the hardware queue register group into the prediction collaborative computing unit, which is composed of digital logic circuits solidified in the integrated circuit, and outputting a predicted sleep window value; A writing module for executing the PREDSLP instruction in the processor instruction set and writing the predicted sleep window value into the sleep configuration register; A gating module for generating a gated pipeline status signal through the dynamic instruction gating unit according to the value of the sleep configuration register; A recovery module for generating a control signal for the receiving module through a programmable timing generator based on the value of the sleep configuration register, including: Extracting the lower 8 bits of the value of the sleep configuration register through a shift register group to generate a sleep coefficient value; Dividing the system clock by a clock division circuit into a 100ms periodic signal as a reference timing signal; Inputting the sleep coefficient value and the reference timing signal into a programmable counter to generate an extended sleep timing signal, satisfying: ； When the value of the sleep configuration register is less than the safety threshold, execute through the hardware timestamp aligner: Read the occurrence time of the event in the predicted event queue; Activate the wake-up circuit 10ms before the event occurrence time to generate a 10ms precise wake-up pulse; Select the extended sleep timing signal or the precise wake-up pulse through a multiplexer circuit to generate a final receive control signal; An allocation module for, when the receiving module captures a valid instruction, sending an interrupt request to the CPU through an asynchronous wake-up circuit, restoring the power supply of the instruction fetch circuit and the decoding circuit, and executing a control response.

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