Power-off detection circuit and power-on and power-off indication circuit

Abstract

The invention relates to a power-off detection circuit and a power-on and power-off indication circuit. The power-off detection circuit is used for generating a power-off marking signal when the power supply voltage is in a power-off state, the on resistance of the variable resistance unit is increased along with the reduction of the power supply voltage in the power-off state so as to increase the voltage of the first node, and the current in the mirror image branch can be increased along with the increase of the voltage of the first node so as to increase the voltage of the second node. According to the power-down mark output module, when the voltage of the second node is lower than a set value, an output power-down mark signal is converted from a first level to a second level, that is, a reliable power-down mark signal is formed, and generation of the power-down mark signal is irrelevant to whether the chip is in a low-power-consumption mode or not. Therefore, the chip can be powered off stably and reliably, and related circuits can be controlled or reset by using the power-off marking signal. The power-on and power-off indicating circuit comprises the power-off detection circuit.

Description

Technical Field

[0001] The present invention relates to the field of circuit technologies, and particularly to a power-down detection circuit and a power-up / down indication circuit. Background Art

[0002] In order to ensure that the internal circuit nodes of a chip can be powered on and off stably and reliably, a suitable power-up / down indication circuit needs to be designed during chip design. A relatively simple power-up / down indication circuit includes several PMOS transistors and resistors, etc. Among them, when the power supply voltage (VDD) exceeds the threshold voltage (Vth) of the PMOS transistor to a certain extent, a current flows through the resistor, and a power-on flag signal is generated in the circuit. When the chip is in a certain low-power mode, the switch coupled to the resistor is turned off according to the mode signal to save the current flowing through the resistor and reduce power consumption. However, it is found that the existing power-up / down indication circuit is difficult to generate a reliable power-down flag signal under the control of the mode signal, which affects the control and reset of the circuit through the power-down flag signal, making the power-down of the chip unable to be completed stably and reliably, and is not conducive to the normal operation of the chip. Summary of the Invention

[0003] The present invention provides a power-down detection circuit that can reliably generate a power-down flag signal, regardless of whether the chip is in a low-power mode, facilitating the chip to complete power-down stably and reliably. The present invention further provides a power-up / down indication circuit.

[0004] On the one hand, the present invention provides a power-down detection circuit for generating a power-down flag signal when the power supply voltage is in a power-down state. The power-down detection circuit includes:

[0005] A power-down flag output module configured to output the power-down flag signal according to the voltage of a second node coupled to the power supply voltage, wherein when the voltage of the second node is lower than a set value, the power-down flag signal changes from a first level to a second level;

[0006] A current source module configured to form a current branch between the power supply voltage and the ground. One of the current branches includes a variable resistance unit with one end coupled to the ground, and the other end of the variable resistance unit is coupled to a first node. The on-resistance of the variable resistance unit increases as the power supply voltage decreases in the power-down state to increase the voltage of the first node; and

[0007] A current mirror module coupled to the first node and forming at least one mirror branch between the second node and the ground. The current in the mirror branch is positively correlated with the voltage of the first node.

[0008] Optionally, the power-down detection circuit further includes a second node pull-up module configured to pull up the voltage of the second node to the power supply voltage after the power supply voltage is powered on. Wherein, as the power supply voltage decreases in the power-down state, the current in the mirror branch increases to a certain extent and pulls down the voltage of the second node.

[0009] Optionally, the second node pull-up module includes a PMOS transistor or at least two PMOS transistors connected in series. And, the gate terminal of the PMOS transistor in the second node pull-up module is grounded, the source terminal is coupled to the power supply voltage, and the drain terminal is coupled to the second node.

[0010] Optionally, the current source module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first resistor, and the variable resistor unit; the source terminals of the first PMOS transistor and the second PMOS transistor are both coupled to the power supply voltage, and the drain terminals are respectively coupled to the drain terminals of the first NMOS transistor and the second NMOS transistor. The gate terminals of the first PMOS transistor and the second PMOS transistor and the drain terminal of the first PMOS transistor are coupled together. The two ends of the first resistor are respectively coupled to the source terminal of the first NMOS transistor and the ground. The gate terminals of the first NMOS transistor and the second NMOS transistor and the drain terminal of the second NMOS transistor are coupled to the first node. The variable resistor unit is respectively coupled to the source terminal of the second NMOS transistor and the ground.

[0011] Optionally, the variable resistor unit includes an NMOS transistor or at least two NMOS transistors connected in series. The gate terminal of the NMOS transistor in the variable resistor unit is coupled to the power supply voltage, the drain terminal is coupled to the source terminal of the second NMOS transistor, and the source terminal is coupled to the ground.

[0012] Optionally, the current mirror module includes a first mirror branch having a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and the ground. The gate terminals of the third NMOS transistor and the fourth NMOS transistor are coupled to the first node.

[0013] Optionally, the power-down detection circuit further includes a first capacitor unit coupled between the power supply voltage and the drain terminal of the fourth NMOS transistor.

[0014] Optionally, the current mirror module further includes a second mirror branch having a fifth NMOS transistor coupled between the second node and the ground. The third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor have the same aspect ratio.

[0015] Optionally, the power-down flag output module includes a fourth PMOS transistor and a sixth NMOS transistor connected in series. The source terminal of the fourth PMOS transistor is coupled to the power supply voltage, and the drain terminal is coupled to the drain terminal of the sixth NMOS transistor. The source terminal of the sixth NMOS transistor is grounded. The second node is coupled to the gate terminals of the fourth PMOS transistor and the sixth NMOS transistor. The power-down flag signal is the voltage signal at the connection point of the fourth PMOS transistor and the sixth NMOS transistor.

[0016] Optionally, the power-down flag output module further includes:

[0017] A first native NMOS transistor, with the drain terminal coupled to the gate terminal and to the power supply voltage, and the source terminal coupled to the source terminal of the fourth PMOS transistor; and

[0018] A second capacitor unit, coupled between the source terminal of the fourth PMOS transistor and ground.

[0019] On the one hand, the present invention provides a power-on / off indication circuit, which includes:

[0020] A zero-th PMOS transistor, a second native NMOS transistor, and a second resistor connected in series between the power supply voltage and ground. The connection point of the zero-th PMOS transistor and the second native NMOS transistor is the initialization node. Wherein, the signal at the gate terminal of the second native NMOS transistor follows the change of the power supply voltage when the power supply voltage is powered on, and turns off the second native NMOS transistor after the power supply voltage is powered on;

[0021] A zero-th NMOS transistor, with the drain terminal coupled to the initialization node and the source terminal grounded;

[0022] The above-mentioned power-down detection circuit, and the power-down flag signal formed by the power-down detection circuit is coupled to the gate terminal of the zero-th NMOS transistor;

[0023] An inverter circuit, with the input terminal coupled to the initialization node and the output terminal generating a power-on / off indication signal.

[0024] The power-down detection circuit provided by the present invention is used to generate a power-down flag signal when the power supply voltage is in the power-down state. Among them, the on-resistance of the variable resistance unit in the current source module increases as the power supply voltage decreases in the power-down state, so as to increase the voltage of the first node. The current in the mirror branch of the current mirror module is positively correlated with the voltage of the first node. Therefore, when the power supply voltage is in the power-down state, the current in the mirror branch can increase as the voltage of the first node increases, and the voltage of the second node is reduced. The power-down flag output module makes the power-down flag signal change from the first level to the second level when the voltage of the second node is lower than the set value, that is, a reliable power-down flag signal is formed. The generation of this power-down flag signal has nothing to do with whether the chip is in the low-power mode, which is convenient for the chip to complete power-down stably and reliably. Using the power-down flag signal, relevant circuits can be controlled or reset.

[0025] The power-on and power-off indication circuit provided by the present invention includes the above-mentioned power-down detection circuit, which can trigger the inversion of the power-on and power-off indication signal by using the reliable power-down flag signal generated by the power-down detection circuit, so as to control or reset relevant circuits to ensure the normal operation of the chip. Moreover, after power-on, the second Native NMOS transistor is turned off, and it can be used in the low-power mode of the chip, which can save power. Brief Description of the Drawings

[0026] Figure 1 is a simplified schematic diagram of a power-on and power-off indication circuit.

[0027] Figure 2 is a schematic diagram of the power-down detection circuit according to an embodiment of the present invention.

[0028] Figure 3 is a schematic diagram of the power-down flag output module in the power-down detection circuit according to another embodiment of the present invention.

[0029] Figure 4 is a schematic diagram of the power-on and power-off indication circuit according to an embodiment of the present invention. Detailed Description of the Invention

[0030] The power-down detection circuit and the power-on and power-off indication circuit of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0031] Figure 1 shows a schematic diagram of a power-on and power-off indication circuit that does not use the power-down detection circuit of the embodiment of the present invention to generate a power-down flag signal. To more clearly illustrate the power-down detection circuit of the embodiment of the present invention, first Figure 1The power-on and power-off indication circuit shown will be described. In the following text, the PMOS transistor refers to a P-type MOS transistor, and the NMOS transistor refers to an N-type MOS transistor.

[0032] As Figure 1 shown, in this power-on and power-off indication circuit, the zero-th PMOS transistor P0 with a lower threshold, the Native NMOS transistor NT0 (threshold voltage (VTH) close to 0V), and the resistor R0 are connected in series between the power supply voltage VDD and the ground. The connection point of the zero-th PMOS transistor P0 and the Native NMOS transistor NT0 is the initialization node INIT0. This initialization node INIT0 is connected to two series-connected inverters (i.e., the first inverter I0 and the second inverter I1). The second inverter I1 outputs the power-on and power-off indication signal PWON. The working process of this power-on and power-off indication circuit is as follows: When the power supply voltage VDD powers on, the signal STATE_1 at the gate terminal of the Native NMOS transistor NT0 increases as the power supply voltage VDD increases. When the power supply voltage VDD is lower than the threshold voltage of the zero-th PMOS transistor P0, the zero-th PMOS transistor P0 is not conducting, and the Native NMOS transistor NT0 is conducting. The initialization node INIT0 is pulled to the zero potential (GND), and the power-on and power-off indication signal PWON is at a low level; when the power supply voltage VDD is greater than the threshold voltage of the PMOS transistor P0 by a certain value, the voltage of the initialization node INIT0 gradually becomes higher. When it exceeds the switching point of the first inverter I0, the power-on and power-off indication signal PWON switches from a low level to a high level, indicating that the power-on is completed; when the power supply voltage VDD is high enough, the voltage of the initialization node INIT0 is equal to the power supply voltage VDD, and the current flowing through the resistor R0 is basically equal to VDD / R0, that is, it is proportional to the power supply voltage VDD.

[0033] To reduce power consumption, the operating mode of the chip can be set to the low-power mode. Using the mode signal corresponding to the low-power mode, a specified circuit can be controlled to be in low power, ultra-low power, sleep, or standby states, etc. For example, when the chip is in the low-power mode, the gate signal STATE_1 of the power-on Native NMOS transistor NT0 is controlled at zero potential (GND) after power-on, that is, the Native NMOS transistor NT0 is turned off, so that the current does not pass through the resistor R0, thereby reducing power consumption. However, when the power supply voltage VDD transitions from the power-on state to the power-off state, since the Native NMOS transistor NT0 is not conducting, it is difficult for the initialization node INIT0 to be pulled down by the resistor R0. As a result, when the power supply voltage VDD drops to a certain level, the first inverter I0 still cannot be flipped, and thus the power-on / off indication signal PWON is also difficult to transition from a high level to a low level, making it difficult to control or reset related circuits using the power-on / off indication signal PWON during power-off. Although when there is a leakage current at the initialization node INIT0, after a sufficient period of time, the power supply voltage VDD drops to turn off the zero-th PMOS transistor P0. At this time, the initialization node INIT0 can gradually decrease. However, obtaining a low-level power-on / off indication signal PWON in this way is very unreliable. If the power supply voltage VDD powers off and then powers on again in a short period of time, and the initialization node INIT0 fails to be reliably pulled down during power-off, it will cause the power supply voltage VDD not to power off completely. During this process, the power-on / off indication signal PWON remains at a high level all the time, resulting in a lack of a reset process. After power-on again, the chip also fails to return to the initial state, which is not conducive to the normal operation of the chip.

[0034] Embodiments of the present invention relate to a power-off detection circuit and a power-on / off indication circuit. Using the power-off flag signal, a reliable power-off flag signal can be generated. Moreover, the generation of the power-off flag signal is independent of whether the chip is in the low-power mode and can be compatible with low-power designs (such as Figure 1 the power-on / off indication circuit shown), facilitating the chip to complete power-off stably and reliably, avoiding power consumption waste, and ensuring the normal operation of the chip. The specific description is as follows.

[0035] Figure 2 is a schematic diagram of the power-off detection circuit according to an embodiment of the present invention. Referring to Figure 2 , the power-off detection circuit includes a current source module 110, a current mirror module 120, and a power-off flag output module 130.

[0036] The current source module 110 is configured to form a current branch between the power supply voltage VDD and the ground (GND). The current branch includes a variable resistance unit 111 with one end coupled to the ground, and the other end of the variable resistance unit 111 is coupled to the first node NB. The on-resistance of the variable resistance unit 111 increases as the power supply voltage VDD decreases in the power-down state, so as to increase the voltage of the first node NB. Exemplarily, the current source module 110 adopts a PTAT (Proportional To Absolute Temperature) constant current source circuit. As Figure 2 shown, the current source module 110 includes, for example, a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a first resistor R1, and the variable resistance unit 111. Among them, the source terminals of the first PMOS transistor P1 and the second PMOS transistor P2 are both coupled to the power supply voltage VDD, and the drain terminals are respectively coupled to the drain terminals of the first NMOS transistor N1 and the second NMOS transistor N2. The gate terminals of the first PMOS transistor P1 and the second PMOS transistor P2 and the drain terminal of the first PMOS transistor P1 are coupled together. The two ends of the first resistor R1 are respectively coupled to the source terminal of the first NMOS transistor N1 and the ground. The gate terminals of the first NMOS transistor N1 and the second NMOS transistor N2 and the drain terminal of the second NMOS transistor N2 are coupled to the first node NB, and the variable resistance unit 111 is respectively coupled to the source terminal of the second NMOS transistor N2 and the ground. In the current source module 110, the MOS transistors other than the variable resistance unit 111 have a relatively low threshold voltage (Vth), so that the power supply voltage VDD required for the normal operation of the current source module 110 is relatively low. As an example, using Figure 2 the current source module 110 shown, by adopting MOS transistors with appropriate threshold voltages and a 3MΩ first resistor R1, when the power supply voltage VDD is powered on, the currents in the current branch where the first resistor R1 is located and the current branch where the second NMOS transistor N2 is located are only dozens of nA.

[0037] The variable resistance unit 111 may include one NMOS transistor or at least two NMOS transistors connected in series. The gate terminal of the NMOS transistor in the variable resistance unit 111 is coupled to the power supply voltage VDD, the drain terminal is coupled to the source terminal of the second NMOS transistor N2, and the source terminal is coupled to the ground. The NMOS transistor in the variable resistance unit 111 adopts an NMOS transistor with a relatively high threshold voltage (Vth). As an example, as Figure 2 shown, the variable resistance unit 111 adopts an NMOS transistor N7, whose gate terminal is coupled to the power supply voltage VDD. When the power supply voltage VDD changes from the working voltage to the power-down state, the on-resistance of the NMOS transistor N7 increases, which will in turn cause the voltage of the first node NB to increase.

[0038] The current mirror module 120 is coupled to the first node NB, and forms at least one mirror branch between the second node PWU coupled to the power supply voltage VDD and the ground. The current in the mirror branch is positively correlated with the voltage of the first node NB.

[0039] As Figure 2 shown, as an example, the current mirror module 120 includes a first mirror branch 121 and a second mirror branch 122. In the first mirror branch 121, a third NMOS transistor N3 and a fourth NMOS transistor N4 are connected in series between the second node PWU and the ground. In the second mirror branch 122, a fifth NMOS transistor N5 is coupled between the second node PWU and the ground. The gate terminals of the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 are all coupled to the first node NB. The first mirror branch 121 and the second mirror branch 122 can proportionally copy the branch current of the current branch where the first node NB is located. The width-to-length ratios (W / L) of the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 are the same or in a multiple relationship. In this embodiment, two mirror branches, namely the first mirror branch 121 and the second mirror branch 122, are provided. For example, the mirror current of the first mirror branch 121 is less than that of the second mirror branch 122 (the width-to-length ratios of the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 are the same, for example). In this way, when using the currents of these two mirror branches to pull down the voltage of the second node PWU, the current pulling-down ability of the second mirror branch 122 is greater than that of the first mirror branch 121, which is convenient for accelerating the pulling-down process. In another embodiment, the second mirror branch 122 may not be provided, but only the first mirror branch 121 is provided.

[0040] The power-down detection circuit according to an embodiment of the present invention may further include a first capacitor unit 150. The first capacitor unit 150 is coupled between the power supply voltage VDD and the drain terminal of the fourth NMOS transistor N4 (i.e., the node DN). Thus, by using the first capacitor unit 150, the change of the power supply voltage VDD can be quickly coupled to the node DN. As Figure 2 shown, as an example, the first capacitor unit 150 includes a third PMOS transistor P3. The source terminal, drain terminal, and body terminal of the third PMOS transistor P3 are all coupled to the power supply voltage VDD. The gate terminal of the third PMOS transistor P3 is coupled to the node DN. The first capacitor unit 150 can also adopt other capacitor types. The MOS transistors in the current mirror module 120 and the first capacitor unit 150 adopt MOS transistors with a relatively low threshold voltage (Vth), for example.

[0041] The power-down flag output module 130 is configured to output a power-down flag signal PWD according to the voltage of a second node PWU coupled to the power supply voltage VDD, wherein when the voltage of the second node PWU is lower than a set value, the power-down flag signal PWD changes from a first level to a second level. The first level and the second level are a set of opposite levels. In this embodiment, the first level is, for example, a low level, and the second level is a high level. Specifically, when the voltage of the second node PWU is lower than the set value, the power-down flag signal PWD is at a high level, and when the voltage of the second node PWU is higher than another set value, the power-down flag signal PWD is at a low level.

[0042] The power-down flag output module 130 may include a set of inverters, and the set value is, for example, the inversion voltage of the inverter. As Figure 2 shown, as an example, the power-down flag output module 130 includes a fourth PMOS transistor P4 and a sixth NMOS transistor N6 connected in series. The source terminal of the fourth PMOS transistor P4 is coupled to the power supply voltage VDD, and the drain terminal is coupled to the drain terminal of the sixth NMOS transistor N6. The source terminal of the sixth NMOS transistor N6 is grounded. The second node PWU is coupled to the gate terminals of the fourth PMOS transistor P4 and the sixth NMOS transistor N6. The power-down flag signal PWD is the voltage signal at the connection point of the fourth PMOS transistor P4 and the sixth NMOS transistor N6. The fourth PMOS transistor P4 and the sixth NMOS transistor N6 are, for example, MOS transistors with a relatively low threshold voltage.

[0043] As shown in the figure, optionally, the power-down detection circuit may further include a second node pull-up module 140 configured to pull up the voltage of the second node PWU to the power supply voltage VDD after the power supply voltage VDD is powered on. Wherein, as the power supply voltage VDD decreases in the power-down state, the current in the mirror branch of the current mirror module 120 increases to a certain extent and pulls down the voltage of the second node PWU.

[0044] As an example, the second node pull-up module 140 includes one PMOS transistor or at least two PMOS transistors connected in series. And the gate terminal of the PMOS transistor in the second node pull-up module 140 is grounded, the source terminal is coupled to the power supply voltage VDD, and the drain terminal is coupled to the second node PWU. The PMOS transistor in the second node pull-up module 140 is, for example, a PMOS transistor with a relatively high threshold voltage. As Figure 2As shown, the second node pull-up module 140 uses a PMOS transistor P5, whose gate terminal is grounded, the source terminal is coupled to the power supply voltage VDD, and the drain terminal is coupled to the second node PWU. After the power supply voltage VDD is powered on, the absolute value of the gate-source voltage VGS of the PMOS transistor P5 is approximately equal to the power supply voltage VDD, and the PMOS transistor P5 is in a strong conduction state, so that the voltage of the second node PWU is pulled to the power supply voltage VDD.

[0045] The working principle of the power-down detection circuit is as follows.

[0046] When the power supply voltage VDD is powered on to a relatively high normal operating voltage, the gate-source voltage VGS of the NMOS transistor N7 in the current source module 110 is large enough (approximately equal to the power supply voltage VDD after power-on), and its on-resistance is small enough to be negligible. The current (about dozens of nA) in the current branch where the second NMOS transistor N2 is located is copied proportionally to the first mirror branch 121 and the second mirror branch 122. The voltage of the node DN is equal to the source-drain voltage (VDS) of the fourth NMOS transistor N4, and this source-drain voltage (VDS) is, for example, about dozens of millivolts (mV). When the power supply voltage VDD is powered on, the absolute value of the gate-source voltage VGS of the PMOS transistor P5 is very large (approximately equal to the power supply voltage VDD after power-on), and it is in a strong conduction state. The second node PWU is pulled to the normal operating voltage of the power supply voltage VDD. At this time, the voltage of the second node PWU is greater than the threshold voltage and the source voltage of the sixth NMOS transistor N6, and the sixth NMOS transistor N6 conducts, while the fourth PMOS transistor P4 is turned off. The power-down flag signal PWD output by the power-down flag output module 130 is at a low level (Power Down), indicating that the power supply voltage VDD has not entered the power-down state. After the power supply voltage VDD is powered on to the normal operating voltage, there are only four branches in this circuit (the branch where the first NMOS transistor N1 is located, the branch where the second NMOS transistor N2 is located, the branch where the third NMOS transistor N3 is located (i.e., the above-mentioned first mirror branch 121), and the branch where the fifth NMOS transistor N5 is located (i.e., the above-mentioned second mirror branch 122)) with relatively small DC currents, and this DC current is basically independent of the power supply voltage VDD, but is related to the resistance value of the first resistor R0. It can be controlled to make the overall power consumption of the circuit low after power-on.

[0047] When the power supply voltage VDD enters the power-down state from the normal operating voltage and powers down slowly, when the power supply voltage VDD drops low enough to be close to the threshold voltage of the NMOS transistor N7, the on-resistance of the NMOS transistor N7 becomes so large that it cannot be ignored (the current branch where the second NMOS transistor N2 is located gradually approaches or is in the off state), and the voltage of the first node NB gradually rises, that is, the gate voltages of the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 gradually increase, so that the currents in the first mirror branch 121 and the second mirror branch 122 gradually increase. When the current flowing through the on-resistance of the PMOS transistor P5 is less than the sum of the currents in the first mirror branch 121 and the second mirror branch 122, the second node PWU will be pulled down so that the voltage of the second node PWU is lower than the threshold voltage and the source voltage of the fourth PMOS transistor P4, and the fourth PMOS transistor P4 conducts, and the sixth NMOS transistor N6 turns off. The power-down flag signal PWD changes from a low level to a high level, indicating that the power supply voltage VDD is in the power-down state. The power-down flag signal PWD can be used to control or reset related circuits.

[0048] In some cases, the power-down speed of the power supply voltage VDD may be relatively fast. When the power supply voltage VDD powers down rapidly and drops low enough to be close to the threshold voltage of the NMOS transistor N7, due to the limitation of the circuit response speed, the voltage of the first node NB may not have time to rise, resulting in the failure to increase the currents in the first mirror branch 121 and the second mirror branch 122 in time due to the increase in the voltage of the first node NB. Therefore, in this embodiment, a third PMOS transistor P3 is provided between the power supply voltage VDD and the node DN as the first capacitor unit 150. When the power supply voltage VDD powers down rapidly, the gate terminal voltage of the third PMOS transistor P3, that is, the voltage of the node DN, will be coupled and reduced or even become negative, so that the current in the first mirror branch 121 increases rapidly, and thus the voltage of the second node PWU can still be pulled down so that the voltage of the second node PWU is lower than the set value, and further the power-down flag signal PWD changes to a high level, that is, a power-down flag can still be generated.

[0049] As Figure 2 shown, in an embodiment, the source terminal of the fourth PMOS transistor P4 is directly coupled to the power supply voltage VDD. Considering this situation, when the power supply voltage VDD powers down to be lower than the threshold voltage of the fourth PMOS transistor P4, the fourth PMOS transistor P4 turns off. At this time, even if the second node PWU is pulled down, since the fourth PMOS transistor P4 is not conducting, it will be difficult for the power-down flag signal PWD to change from a low level to a high level. In order to facilitate the power-down flag signal PWD to also change from a low level to a high level in this case, refer to Figure 3, which shows the circuit of the power-down flag output module 130 in another embodiment. In another embodiment, the power-down flag output module 130 includes a fourth PMOS transistor P4 and a sixth NMOS transistor N6. The source terminal of the sixth NMOS transistor N6 is grounded. The second node PWU is coupled to the gate terminals of the fourth PMOS transistor P4 and the sixth NMOS transistor N6. The power-down flag signal is the voltage signal at the connection point of the fourth PMOS transistor P4 and the sixth NMOS transistor N6. Moreover, the power-down flag output module 130 further includes a first Native NMOS transistor NT1 and a second capacitor unit 131. The drain terminal of the first Native NMOS transistor NT1 is coupled to the gate terminal and coupled to the power supply voltage VDD. The source terminal of the first Native NMOS transistor NT1 is coupled to the source terminal of the fourth PMOS transistor P4. The second capacitor unit 131 is coupled between the source terminal of the fourth PMOS transistor P4 and the ground. The second capacitor unit 131 can adopt various capacitor types. Here, for example, an NMOS transistor N8 is used. The source terminal, drain terminal, and substrate terminal of the NMOS transistor N8 are grounded while the gate terminal is coupled to the source terminal of the fourth PMOS transistor P4. Using the power-down flag output module 130 as shown in Figure 3 , when the power supply voltage VDD is at a relatively high normal operating voltage, the second capacitor unit 131 stores charge. When the power supply voltage VDD powers down from the normal operating voltage to a lower value, the charge stored in the second capacitor unit 131 enables the fourth PMOS transistor P4 to still conduct, thereby ensuring that the power-down flag signal PWD changes from a low level to a high level.

[0050] Using the power-down detection circuit described in the above embodiments, when the power supply voltage VDD is in the power-down state, the on-resistance of the variable resistance unit 111 in the current source module 110 increases, causing the voltage of the first node NB to rise, and further enabling the current in the mirror branch to increase. When the current in the mirror branch increases to a certain extent, the voltage of the second node PWU is pulled down, and a reliable power-down flag signal PWD is output through the power-down flag output module 130. Using the power-down flag signal PWD, relevant circuits can be controlled or reset. Moreover, the generation of the power-down flag signal PWD is independent of whether the chip is in the low-power mode, and it can also maintain low power consumption after the power supply voltage VDD powers on, avoiding power consumption waste.

[0051] An embodiment of the present invention further includes a power-on / power-down indication circuit, which applies the power-down detection circuit described in the above embodiments to Figure 1 the power-on / power-down indication circuit as shown in to obtain a reliable power-down flag signal.

[0052] Figure 4 is a schematic diagram of the power-on / power-down indication circuit according to an embodiment of the present invention. Referring to Figure 4 , the power-on / power-down indication circuit includes:

[0053] A zero PMOS transistor P0, a second native NMOS transistor NT2, and a second resistor R2 connected in series between a power supply voltage VDD and ground (GND), a connection point of the zero PMOS transistor P0 and the second native NMOS transistor NT2 being an initialization node INIT0, wherein a signal STATE_1 at a gate terminal of the second native NMOS transistor NT2 changes following the power supply voltage VDD when the power supply voltage VDD is powered on, and turns off the second native NMOS transistor NT2 after the power supply voltage VDD is powered on;

[0054] A zero NMOS transistor N0, having a drain terminal coupled to the initialization node INIT0 and a source terminal grounded;

[0055] For the power-down detection circuit described in the above embodiment, a power-down flag signal PWD formed by the power-down detection circuit is coupled to a gate terminal of the zero NMOS transistor N0;

[0056] An inverter circuit 160, having an input terminal coupled to the initialization node INIT0 and an output terminal generating a power-on / off indication signal PWON.

[0057] In this embodiment, the inverter circuit includes, for example, a first inverter I0 and a second inverter I1, an input terminal of the first inverter I0 being coupled to the initialization node INIT0, an input terminal of the second inverter I1 being coupled to an output terminal of the first inverter I0, and an output terminal of the second inverter I1 outputting the power-on / off indication signal PWON.

[0058] Figure 4When the power-on and power-off indication circuit shown is working, when the power supply voltage VDD is powered on, the gate signal STATE_1 of the second Native NMOS transistor NT2 changes following the power supply voltage VDD. When the power supply voltage VDD is lower than the threshold voltage of the zero-th PMOS transistor P0, the zero-th PMOS transistor P0 is not conducting, and the second Native NMOS transistor NT2 is conducting. The initialization node INIT0 is pulled to the zero potential (GND), and the power-on and power-off indication signal PWON is at a low level. When the power supply voltage VDD is greater than the threshold voltage of the zero-th PMOS transistor P0 by a certain value, the voltage of the initialization node INIT0 gradually becomes higher. When it exceeds the switching voltage of the first inverter I0, the power-on and power-off indication signal PWON changes from a low level to a high level, indicating that the power-on is completed. After the power supply voltage VDD is powered on, the gate terminal signal STATE_1, for example, is grounded, causing the second Native NMOS transistor NT2 to turn off, so that the current does not pass through the second resistor R2, which can reduce power consumption. This setting can be used in conjunction with the low-power mode of the chip. When the power supply voltage VDD enters the power-off state from the normal operating voltage after power-on, as known from the power-off detection circuit described in the above embodiments, the power-off flag signal PWD can change from a low level to a high level, so that the zero-th NMOS transistor N0 conducts, causing the initialization node INIT0 to be pulled to a low level, and the power-on and power-off indication signal PWON changes from a high level to a low level to control or reset the relevant circuits on the chip. Subsequently, when the power supply voltage VDD is powered on again, the chip can return to the correct initial state.

[0059] Using the power-on and power-off indication circuit of the embodiment of the present invention, reliable power-on and power-off indication signals can be formed when the power supply voltage VDD is powered on and powered off. These power-on and power-off indication signals can be used to control, reset, or reinitialize relevant circuits. Moreover, after power-on, the second Native NMOS transistor NT2 turns off, and it can be used in the low-power mode of the chip, which can save power.

[0060] The above description is only a description of the preferred embodiments of the present invention, and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes, and decorations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention all fall within the protection scope of the technical solutions of the present invention.

Claims

1. A power-down detection circuit, characterized in that, For generating a power-down flag signal when the power supply voltage is in the power-down state, the power-down detection circuit includes: A power-down flag output module configured to output the power-down flag signal according to the voltage of a second node coupled to the power supply voltage, wherein when the voltage of the second node is lower than a set value, the power-down flag signal changes from a first level to a second level; A current source module configured to form a current branch between the power supply voltage and ground, the current branch including a variable resistance unit with one end coupled to ground and the other end coupled to a first node, the on-resistance of the variable resistance unit increasing as the power supply voltage decreases in the power-down state to increase the voltage of the first node; and A current mirror module coupled to the first node and forming at least one mirror branch between the second node and ground, the current in the mirror branch being positively correlated with the voltage of the first node.

2. The power-down detection circuit according to claim 1, wherein, It further includes: A second node pull-up module configured to pull up the voltage of the second node to the power supply voltage after the power supply voltage is powered on, wherein as the power supply voltage decreases in the power-down state, the current in the mirror branch increases to a certain extent and pulls down the voltage of the second node.

3. The power-off detection circuit according to claim 2, wherein The second node pull-up module includes a PMOS transistor or at least two PMOS transistors connected in series, and the gate terminal of the PMOS transistor in the second node pull-up module is grounded, the source terminal is coupled to the power supply voltage, and the drain terminal is coupled to the second node.

4. The power-down detection circuit according to claim 1, wherein The current source module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first resistor, and the variable resistance unit; the source terminals of the first PMOS transistor and the second PMOS transistor are both coupled to the power supply voltage and the drain terminals are respectively coupled to the drain terminals of the first NMOS transistor and the second NMOS transistor, the gate terminals of the first PMOS transistor and the second PMOS transistor and the drain terminal of the first PMOS transistor are coupled together, the two ends of the first resistor are respectively coupled to the source terminal of the first NMOS transistor and ground, the gate terminals of the first NMOS transistor and the second NMOS transistor and the drain terminal of the second NMOS transistor are coupled to the first node, and the variable resistance unit is respectively coupled to the source terminal of the second NMOS transistor and ground.

5. The power-down detection circuit according to claim 1, wherein The variable resistance unit includes an NMOS transistor or at least two NMOS transistors connected in series, the gate terminal of the NMOS transistor in the variable resistance unit is coupled to the power supply voltage, the drain terminal is coupled to the source terminal of the second NMOS transistor, and the source terminal is coupled to ground.

6. The power-down detection circuit according to claim 1, wherein, The current mirror module includes a first mirror branch having a third NMOS transistor and a fourth NMOS transistor connected in series between the second node and ground, and the gate terminals of the third NMOS transistor and the fourth NMOS transistor are coupled to the first node.

7. The power-down detection circuit according to claim 6, wherein The power-down detection circuit further includes: A first capacitor unit coupled between the power supply voltage and the drain terminal of the fourth NMOS transistor.

8. The power-down detection circuit according to claim 6, wherein, The current mirror module further includes a second mirror branch, and the second mirror branch has a fifth NMOS transistor coupled between the second node and the ground. The third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor have the same aspect ratio.

9. The power-down detection circuit according to claim 1, wherein The power-down flag output module includes a fourth PMOS transistor and a sixth NMOS transistor connected in series. The source terminal of the fourth PMOS transistor is coupled to the power supply voltage, and the drain terminal is coupled to the drain terminal of the sixth NMOS transistor. The source terminal of the sixth NMOS transistor is grounded. The second node is coupled to the gate terminals of the fourth PMOS transistor and the sixth NMOS transistor. The power-down flag signal is the voltage signal at the connection point of the fourth PMOS transistor and the sixth NMOS transistor.

10. The power-down detection circuit according to claim 9, wherein The power-down flag output module further includes: a first Native NMOS transistor, with the drain terminal coupled to the gate terminal and coupled to the power supply voltage, and the source terminal coupled to the source terminal of the fourth PMOS transistor; and a second capacitor unit, coupled between the source terminal of the fourth PMOS transistor and the ground.

11. An up and down power indication circuit, characterized in that, including: a zero-th PMOS transistor, a second Native NMOS transistor, and a second resistor connected in series between the power supply voltage and the ground. The connection point of the zero-th PMOS transistor and the second Native NMOS transistor is the initialization node. Among them, the signal at the gate terminal of the second Native NMOS transistor follows the change of the power supply voltage when the power supply voltage is powered on, and turns off the second Native NMOS transistor after the power supply voltage is powered on; a zero-th NMOS transistor, with the drain terminal coupled to the initialization node and the source terminal grounded; The power-down detection circuit according to any one of claims 1 to 10, wherein the power-down flag signal formed by the power-down detection circuit is coupled to the gate terminal of the zero-th NMOS transistor; and an inverter circuit, with the input terminal coupled to the initialization node and the output terminal generating a power-on / off indication signal.

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