High-precision code Doppler implementation method capable of being used for channel simulation instrument
Through the secondary decimal interpolation algorithm and the ping-pong operation of DDR4 SDRAM memory, the continuous changes in code Doppler effect and mirror signal leakage in satellite communication are solved, and high-precision code Doppler simulation is realized, which simplifies the hardware structure and improves system flexibility.
Patent Information
- Application Number
- CN202510798407.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-16
- Publication Date
- 2025-07-25
AI Technical Summary
In the prior art, when simulating the code Doppler effect in satellite communication, it is difficult to achieve continuous changes and high hardware costs, or the problem of mirror signal leakage will occur without changing the sampling rate.
The secondary decimal interpolation algorithm and DDR4 SDRAM memory are used to generate carriers through FPGA, and the memory read and write synchronization is controlled using ping pong operation, and the secondary decimal interpolation and convolution process are performed to simplify the hardware structure and realize high-precision code Doppler simulation.
It realizes that the system sampling rate is not frequently changed at different motion speeds, simplifies the hardware structure, and greatly suppresses the leakage of mirror signals, and dynamically simulates the continuous code Doppler effect.
Smart Images
Figure CN120378036A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of satellite communication, and in particular to a high-precision code Doppler implementation method applicable to a channel simulator. Background Art
[0002] Satellite communication plays an indispensable role in the modern communication system. It can break through the limitations of the geographical environment and achieve seamless global coverage. The high-speed relative motion between the satellite and the terminal will bring about the code Doppler effect, making the acquisition and synchronization of satellite signals particularly difficult. The wireless channel simulator can simulate various wireless communication propagation environments in the laboratory; it has a wide range of applications, is not affected by geographical and weather conditions, and the parameter indicators are repeatable, effectively shortening the R & D cycle of equipment, making it an essential device for satellite communication testing.
[0003] In the prior art for simulating the code Doppler effect, one is to change the sampling rate of AD / DA to achieve the change of chip bandwidth, which cannot ensure the continuous change simulation of code Doppler, and at the same time has a high hardware cost. The other is to use a farrow filter to resample the code element to achieve the change of chip bandwidth without changing the AD / DA sampling rate. This scheme will have mirror signal leakage at the critical bandwidth. Summary of the Invention
[0004] In order to overcome the above problems existing in the prior art, the present invention proposes a high-precision code Doppler implementation method applicable to a channel simulator.
[0005] The technical solution adopted by the present invention to solve its technical problems is: a high-precision code Doppler implementation method applicable to a channel simulator, including the following steps: Step 1, the user sets the working bandwidth, working frequency point, moving speed and working mode, calculates the code Doppler frequency shift amount and the Doppler frequency shift amount according to the user settings, and converts them into fixed-point numbers and issues them to the FPGA; Step 2, the FPGA generates a carrier according to the issued Doppler frequency shift amount; Step 3, judge the positive and negative code offsets. According to the positive and negative code offsets, use a memory to realize the accumulation of input / output signals, and at the same time, use the misaligned address control technology to control the memory to complete the read and write synchronization through ping-pong operation; Step 4, perform a two-stage fractional interpolation algorithm on the input signal; Step 5, reconstruct the code element, generate a Doppler frequency shift according to the set Doppler control word, convolve it with the reconstructed signal, and output through DA.
[0006] In the above-mentioned high-precision code Doppler implementation method applicable to a channel simulator, in step 1, the code Doppler frequency shift amount is converted into the interpolation and decimation amount for resampling, and the Doppler frequency shift amount is converted into a frequency control word.
[0007] The above-mentioned high-precision code Doppler implementation method applicable to a channel simulator, in step 3, the memory is implemented by DDR4 SDRAM, and the specific read and write processes include: 1) According to the set cache capacity, convert it into an address offset; 2) Concatenate the signal data and start writing data into the write FIFO; 3) Judge the status of the write FIFO. When it reaches the half-full state, enter the DDR4 write operation. If it does not reach the half-full state, enter step 4); 4) Judge whether FIFO0 reaches the half-full state. When it reaches the half-full state, enter step 3). If it does not reach the half-full state, start reading data from the DDR according to the first read address, read 128 memory units, and enter step 3).
[0008] The above-mentioned high-precision code Doppler implementation method applicable to a channel simulator, the second-order fractional interpolation algorithm in step 4 is specifically: use a farrow filter to complete fractional interpolation on a Sinc filter, and use the Sinc filter after fractional interpolation to filter the input signal.
[0009] The above-mentioned high-precision code Doppler implementation method applicable to a channel simulator, the farrow filter is expressed as: Wherein, is the fitting polynomial, m is the delay order, is the fractional step, is the polynomial; The Sinc filter after fractional interpolation is expressed as: Wherein, t is the continuous time, is the fractional step; For the baseband signal, the frequency is between which is equivalent to truncating . To prevent spectrum leakage, windowing is used for truncation, and finally it is expressed as: Wherein, n is the sampling point, and L represents the window function length.
[0010] The beneficial effects of the present invention are that the present invention uses the fractional interpolation method to achieve fractional interpolation compared with changing the AD / DA sampling rate, simplifies the hardware structure, and improves the flexibility of the system. The second-order fractional interpolation algorithm greatly suppresses the mirror signal leakage of the critical bandwidth compared with the fractional interpolation of the farrow filter. The cubic interpolation algorithm is used to segment and quantize the code Doppler quantity to realize the simulation of the dynamic continuous code Doppler effect. Brief Description of the Drawings
[0011] Figure 1 is a schematic diagram of the implementation of the code Doppler of the present invention; Figure 2 is a schematic diagram of the DDR4 state control of the present invention; Figure 3 is a schematic diagram of the farrow structure of the present invention. Detailed Embodiment
[0012] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be described in detail below in conjunction with the drawings and specific embodiments.
[0013] This embodiment discloses a high-precision code Doppler implementation method applicable to a channel simulator. Users can set the working bandwidth, working frequency point, moving speed, and working mode of the channel simulator according to requirements; calculate the code Doppler amount and Doppler frequency shift amount according to the user settings, convert the code Doppler amount into the interpolation and decimation amount of resampling, and convert the Doppler frequency shift amount into a frequency control word. The conversion results are represented in fixed-point numbers and sent to the FPGA. In the FPGA, according to the set decimation and interpolation amounts, calculate whether it is a positive code offset or a negative code offset. According to the positive and negative code offsets, use DDR4 to implement the accumulation of input / output signals. At the same time, with the misaligned address control technology, the DDR4 is controlled through ping-pong operation to complete read and write synchronization to ensure the continuity of the signal; perform a two-stage fractional interpolation algorithm on the input signal, reconstruct the code elements, generate a Doppler frequency shift according to the set Doppler control word, convolve it with the reconstructed signal, and finally output through DA. The overall block diagram is as Figure 1 shown.
[0014] The specific steps are as follows: Step 1, the user sets the working bandwidth, working frequency point, moving speed, and working mode. The PC calculates the code Doppler frequency shift amount and Doppler frequency shift amount, and converts them into fixed-point numbers and sends them to the FPGA; Step 2, in the FPGA, generate a carrier according to the sent Doppler frequency shift amount; Step 3, judge the positive and negative code offsets. If it is a positive code offset, use memory 0 to cache the signals collected by 1GB of AD. If it is a negative code offset, use memory 1 to cache the resampled signals of 1GB; Step 4, read the data in memory 0, perform a two-stage fractional interpolation on it, and cache it into DDR4_1. The working clock is 2 times the system clock; Step 5, read the data in memory 1 and convolve it with the carrier generated in step 2; Step 6, send it out through DA.
[0015] In this embodiment, the memory for data caching is implemented using DDR4 SDRAM. The misaligned address control technology is used to reasonably switch the read / write states, and the ping-pong operation is adopted to enable simultaneous reading and writing of signals. The read / write DDR4 process is as follows Figure 2 , and the specific operations are as follows: 1) According to the set cache capacity, convert it into an address offset. 2) Concatenate the signal data and start writing data into the write FIFO. 3) Judge the status of the write FIFO. When it reaches the half-full state, enter the DDR4 write operation. If it does not reach the half-full state, enter step 4). 4) Judge whether FIFO0 reaches the half-full state. When it reaches the half-full state, enter step 3). If it does not reach the half-full state, start reading data from the DDR according to the first-channel read address, read 128 memory units, and then enter step 3).
[0016] In this embodiment, the second-order fractional interpolation is specifically as follows: For fractional delay, the signal is first interpolated by N times and then decimated by M times to achieve fractional sampling rate conversion. Based on the signal resampling of fractional interpolation, a polynomial approximation low-pass filter is used to achieve fractional interpolation. The farrow filter structure is often adopted. In this method, for the critical Nyquist sampling theorem, the out-of-band image interference cannot be filtered out. This problem is eliminated by the second-order fractional interpolation in this method, that is, the farrow filter is used to complete the fractional interpolation of the Sinc filter, and then the input signal is filtered by the Sinc filter after fractional interpolation.
[0017] For the farrow filter, the idea of this method is to use polynomial fitting, that is, regarding each order h as polynomial fitting: where p is the filter order, m is the filter index, ∆ is the fractional delay, is the fitting polynomial.
[0018] The corresponding filter can be expressed as: Simplify it to: where, is the fitting polynomial, m is the delay order, is the fractional step, and the current architecture is as Figure 3 shown.
[0019] The Sinc function can be expressed as: The Sinc filter after fractional interpolation is expressed as: For the baseband signal, the frequency needs to be restricted to between, which is equivalent to performing frequency truncation on as follows: To prevent spectrum leakage, windowing is used for truncation, and the final expression is: .
[0020] In this embodiment, the chip bandwidth change is achieved through the resampling algorithm. When simulating different motion speeds, there is no need to frequently change the system sampling rate, which simplifies the hardware implementation unit. The second-order fractional interpolation algorithm is adopted to reconstruct the code elements to achieve high-precision code Doppler effect. When simulating different motion speeds, there is no need to frequently change the system sampling rate, which simplifies the hardware implementation unit. At the same time, the cubic interpolation algorithm is used to segment and quantize the code Doppler quantity to achieve the simulation of dynamic continuous code Doppler effect.
[0021] The above embodiments are only exemplary embodiments of the present invention and are not used to limit the present invention. Those skilled in the art can make various modifications or equivalent replacements to the present invention within the essence and protection scope of the present invention, and such modifications or equivalent replacements should also be regarded as falling within the protection scope of the present invention.
Claims
1. A high-precision code Doppler implementation method applicable to a channel simulator, characterized in that It includes the following steps: Step 1: The user sets the working bandwidth, working frequency point, moving speed, and working mode, calculates the code Doppler frequency shift amount and Doppler frequency shift amount according to the user settings, and converts them into fixed-point numbers and sends them to the FPGA; Step 2: The FPGA generates a carrier according to the sent Doppler frequency shift amount; Step 3: Judge the positive and negative code offsets. According to the positive and negative code offsets, use the memory to realize the accumulation of input / output signals. At the same time, with the misaligned address control technology, the ping-pong operation is used to control the memory to complete the read and write synchronously; Step 4: Perform a two-stage fractional interpolation algorithm on the input signal; Step 5: Reconstruct the code element, generate a Doppler frequency shift according to the set Doppler control word, convolve it with the reconstructed signal, and output through the DA; 2. A high-precision code Doppler implementation method for a channel simulator according to claim 1, characterized in that, In the said Step 1, the code Doppler frequency shift amount is converted into the interpolation and decimation amount for resampling, and the Doppler frequency shift amount is converted into a frequency control word; 3. A high-precision code Doppler implementation method for a channel simulator according to claim 1, characterized in that, In the said Step 3, the memory is implemented by using DDR4 SDRAM. The specific read and write process includes: 1) According to the set cache capacity, convert it into an address offset; 2) Concatenate the signal data and start writing data into the write FIFO; 3) Judge the status of the write FIFO. When it reaches the half-full state, enter the DDR4 write operation. If it does not reach the half-full state, enter Step 4); 4) Judge whether FIFO0 reaches the half-full state. When it reaches the half-full state, enter Step 3). If it does not reach the half-full state, start reading data from the DDR according to the first read address, read 128 memory units, and enter Step 3); 4. A high-precision code Doppler implementation method for a channel simulator according to claim 1, characterized in that, In the said Step 4, the two-stage fractional interpolation algorithm is specifically: use the farrow filter to complete the fractional interpolation of the Sinc filter, and use the Sinc filter after fractional interpolation to filter the input signal; 5. A high-precision code Doppler implementation method applicable to a channel simulator according to claim 4, characterized in that The said farrow filter is expressed as: wherein, is a fitting polynomial, m is the delay order, is a decimal step, is a polynomial; The Sinc filter after fractional interpolation is expressed as: where t is continuous time, is a fractional step; For the baseband signal, the frequency is between which is equivalent to truncating To prevent spectral leakage, windowing is used for truncation, and the final expression is: Where n is the sampling point and L represents the window function length.