Switching tube delay method and wave-by-wave current-limiting protection method of NPC type three-level topological structure

Abstract

The invention discloses a switching tube delay method and a wave-by-wave current-limiting protection method of an NPC type three-level topological structure, which are used for controlling the switching time sequence of an inner tube and an outer tube of a switching tube in an NPC type three-level inverter, and a digital signal processing DSP chip comprises a configurable logic module CLB; the switch tube delay control of the NPC type three-level topological structure is realized through the wave-sending turn-on delay logic and the wave-sealing turn-off delay logic of the configurable logic module CLB, the wave-by-wave current-limiting protection logic during the overcurrent of equipment hardware is realized, and the logic control requirements that the inner tube is firstly turned on and then the outer tube is firstly turned on and then the inner tube is firstly turned off are met. The switch tube delay control and wave-by-wave current-limiting protection logic of the NPC type three-level topological structure are realized by adopting a single chip mode, and the hardware structure and the software complexity of the circuit are simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply equipment, and in particular to a time delay method and a wave-by-wave current limiting protection method for a switch tube of an NPC type three-level topology structure. Background Art

[0002] NPC (Neutral Point Clamped) three-level topology is the most widely used multi-level topology, such as Figure 1 As shown in the figure, its main advantages are as follows: 1. The voltage supported by a single device is low, allowing it to be used in higher voltage applications; 2. Compared with a two-level inverter, it generates more levels, and the superposition of multiple levels is more similar to a sine wave, with low harmonic content; 3. Electromagnetic interference problems are alleviated, and the dv / dt (switching transient voltage change rate) of a three-level inverter device is only half of that of a traditional two-level inverter; 4. Switching losses are significantly reduced, improving efficiency.

[0003] NPC three-level has special requirements for opening and closing the tube. It is necessary to follow the principle of "opening the tube first and then the outer tube, and closing the tube first and then the inner tube". Otherwise, it may cause damage to the IGBT module. The traditional method adopts the structure of ARM or DSP + FPGA or CPLD, and uses FPGA or CPLD to capture the edge of PWM to realize the delay of switching tube, such as Figure 2 The dual-chip solution is not only complex in structure but also expensive. ARM and DSP are programmed in C language, while FPGA / CPLD uses Verilog or VHDL hardware description language, which increases the complexity of the software. Summary of the Invention

[0004] In view of this, it is necessary to provide a switch delay method and a wave-by-wave current limiting protection method for an NPC type three-level topology structure implemented by a DSP single chip.

[0005] A method for delaying switching tubes in an NPC-type three-level topology structure is used to control the switching timing of inner and outer switching tubes in an NPC-type three-level inverter. The NPC-type three-level inverter includes a digital signal processing (DSP) chip, which includes a configurable logic module (CLB). The method includes wave-generating on-delay logic and wave-blocking off-delay logic. The wave-generating on-delay logic is used to control the delay of the outer tube when the tube is turned on, and the wave-blocking off-delay logic is used to control the delay of the inner tube when the tube is turned off, so as to avoid damage to the switching tube (IGBT).

[0006] Preferably, the configurable logic module CLB is used to implement digital logic control functions through a hardware structure. The configurable logic module CLB includes a counter Counter, a finite state machine FSM, a lookup table module LUT4, an output lookup table module Output LUT, a high-level controller HLC, a configurable switching block, an input signal selector and a peripheral signal multiplexer.

[0007] Preferably, the specific steps of the wave-generating opening delay logic include: Step 1.1: When the tube is turned on, the PWM module of the digital signal processing DSP chip outputs the inner tube drive signal PWMxB0 and the outer tube drive signal PWMxA0; Step 1.2, set the PWM enable signal PWM_EN to a high level, and the event signal E1 to a high level; Step 1.3: The internal tube wave enable logic signal S2 is valid. The internal tube wave enable logic signal S2 is logically ANDed with the internal tube drive signal PWMxB0. The result of the operation is sent to the internal tube and drives the internal tube to turn on. Step 1.4, invert the event signal E1 and input the inverted signal into the first timer Timer0 to start timing the first timer Timer0; Step 1.5: After the first timer Timer0 reaches a predetermined time length, an event signal E2 is generated; Step 1.6: Perform a logic AND operation on the event signal E1 and the event signal E2. If the operation result is valid, an external tube wave enabling logic signal S1 is generated. Step 1.7: The external tube wave transmission enable logic signal S1 is valid. The external tube wave transmission enable logic signal S1 is logically ANDed with the external tube drive signal PWMxA0. The result of the operation is sent to the external tube and drives the external tube to be delayed and turned on.

[0008] Preferably, the calculation formula of the external tube wave enabling logic signal S1 in step 1.6 is as shown in formula (1): S1 = (S1&E2) |(~S1&E1)(1).

[0009] Preferably, the specific steps of the wave blocking and delay logic include: Step 2.1: When the tube is turned off, the PWM module of the digital signal processing DSP chip outputs the inner tube drive signal PWMxB0 and the outer tube drive signal PWMxA0; Step 2.2, the PWM enable signal PWM_EN is set to low level, and the event signal E3 is set to low level; Step 2.3: The external tube wave enable logic signal S1 is invalid, and the external tube wave enable logic signal S1 is logically ANDed with the external tube drive signal PWMxA0. The result of the operation is sent to the external tube and drives the external tube to shut down. Step 2.4: The wave-encapsulation enable signal E3 triggers the second timer Timer1, so that the second timer Timer1 starts timing; Step 2.5: After the second timer Timer1 reaches a predetermined time, an event signal E4 is generated; Step 2.6, perform a logic AND operation on the wave blocking enable signal E3 and the event signal E4, and generate an inner tube wave blocking enable logic signal S2 when the operation result is valid; Step 2.7: The inner tube wave blocking enable logic signal S2 is valid. The inner tube wave blocking enable logic signal S2 is logically ANDed with the inner tube drive signal PWMxB0. The result of the operation is sent to the inner tube and drives the outer tube to be turned off with a delay.

[0010] Preferably, the calculation formula of the inner tube wave sealing enable logic signal S2 in step 2.6 is as shown in formula (1): S2 = (S2&~E3) |(~S2&E4) (2).

[0011] Preferably, in the wave-generating on-delay logic and the wave-blocking off-delay logic, The logic expression of the external tube PWM output is shown in formula (3): PWMxA = S1&PWMxA0(3); The logic expression of the inner tube PWM output is shown in formula (4): PWMxB = S1&PWMxB0 (4).

[0012] Preferably, the predetermined durations of the first timer Timer0 and the second timer Timer1 are preferably 5 us.

[0013] A wave-by-wave current limiting protection method for an NPC three-level topology structure is provided. The switching timing of the inner and outer switching tubes in the NPC three-level inverter is adjusted by using the switching tube delay method of the NPC three-level topology structure described above. The specific steps include: Step 1: The hardware overcurrent detection signal OC_U / V / W is transmitted to the input port of the hardware fault protection module TZ; Step 2: When an overcurrent signal is detected, the TZ module sets PWMxA to a low level and PWMxB to a high level; Step 3: The outer tube is turned off and the inner tube is in the open state; Step 4: When the PWM counter underflow interrupt occurs, check whether the cycle-by-cycle current limit protection flag is valid; if valid, perform a logical AND operation on the cycle-by-cycle current limit protection flag and the operation signal GPIO25; if the operation result is a low-level signal, the low-level signal is input to the CLB wave generator module to turn off the output of PWMB; Step 5: Shut off the inner tube.

[0014] Preferably, when the hardware overcurrent signal is invalid, the PWM enable signal PWM_EN is set to a high level, starting the PWM start-up delay logic of the fully configurable logic module CLB to turn on the inner and outer switches in the NPC three-level inverter.

[0015] In the aforementioned NPC-type three-level topology switch delay method and wave-by-wave current limiting protection method, the digital signal processing (DSP) chip includes a configurable logic module (CLB). The CLB's wave-on delay logic and wave-off delay logic implement delay control of the NPC-type three-level topology switch, implementing wave-by-wave current limiting protection logic in the event of hardware overcurrent. This achieves the logic control requirements of switching the internal tube first, then the external tube, when opening the tube, and switching the external tube first, then the internal tube, when closing the tube. The present invention uses a single chip to implement delay control and wave-by-wave current limiting protection logic for the NPC-type three-level topology switch, simplifying the circuit's hardware structure and software complexity. The present invention's method is simple, easy to implement, low-cost, and easy to promote. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a circuit diagram of an NPC three-level topology.

[0017] Figure 2 It is a schematic diagram of the structure of a dual-chip structure of ARM or DSP + FPGA or CPLD in the prior art.

[0018] Figure 3 It is a structural diagram of a single-chip structure of a switch tube delay method and a wave-by-wave current limiting protection method of an NPC type three-level topology structure according to an embodiment of the present invention.

[0019] Figure 4 The present invention is a flowchart of the wave-generating turn-on delay logic of the switch tube delay method of the NPC type three-level topology structure according to the embodiment of the present invention.

[0020] Figure 5 This is a flow chart of the blocking and turning-off delay logic of the switch tube delay method of the NPC type three-level topology structure according to an embodiment of the present invention.

[0021] Figure 6 This is a timing diagram of the PWM wave switching tube delay logic of the switching tube delay method of the NPC type three-level topology structure according to an embodiment of the present invention.

[0022] Figure 7 It is a structural diagram of the PWM wave protection structure of the wave-by-wave current limiting protection method of the NPC type three-level topology structure according to an embodiment of the present invention.

[0023] Figure 8This is a timing diagram of the PWM pulse action during startup of the NPC three-level topology structure according to an embodiment of the present invention.

[0024] Figure 9 This is a timing diagram of the PWM pulse action during shutdown of the NPC three-level topology structure according to an embodiment of the present invention.

[0025] Figure 10 This is a timing diagram of the wave-by-wave current limiting PWM pulse action of the NPC type three-level topology structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] This embodiment takes the switch tube delay method and the wave-by-wave current limiting protection method of an NPC three-level topology structure as an example, and the present invention will be described in detail below with reference to specific embodiments and drawings.

[0027] See also Figures 3 to 6 , showing a switching tube delay method for an NPC-type three-level topology structure provided by an embodiment of the present invention, which is used to control the switching timing of the inner and outer switching tubes in an NPC-type three-level inverter. The NPC-type three-level inverter includes a digital signal processing DSP chip, and the digital signal processing DSP chip includes a configurable logic module CLB; the switching tube delay method includes wave-generating turn-on delay logic and wave-blocking turn-off delay logic. The wave-generating turn-on delay logic is used to delay control the outer tube when turning on the tube, and the wave-blocking turn-off delay logic is used to delay control the inner tube when turning off the tube, so as to avoid damage to the switching tube IGBT.

[0028] Preferably, the configurable logic module CLB is used to implement complex digital logic control functions through a flexible hardware structure. The configurable logic module CLB includes a counter Counter, a finite state machine FSM, a lookup table module LUT4, an output lookup table module Output LUT, a high-level controller HLC, a configurable switching block, an input signal selector and a peripheral signal multiplexer.

[0029] Specifically, the configurable logic module CLB includes multiple tiles, that is, independent functional units or core modules on the chip, wherein: Counters: Each submodule contains three counters, configurable as adders, counters, or shifters, capable of addition and subtraction, up and down counting, and left and right shifting. The counter event and reset inputs can be freely routed to other submodules in the same instance.

[0030] Finite State Machine (FSM): There are three FSMs in each submodule, which can be configured as a single four-state finite state machine or as two independent two-state finite state machines. They accept two external inputs and generate two state outputs and one combinational output. They can also work as a 4-input lookup table LUT when not used as a state machine.

[0031] Lookup table module (LUT4): Each submodule has 3 LUT4s, which have 4-input lookup table function and can implement any Boolean equation with up to 4 inputs.

[0032] Output LUT: Each submodule has 8 Output LUTs, which are three-input lookup table submodules that can implement any combination of Boolean equations with up to three inputs. Each block is associated with one of the tile outputs.

[0033] High-level controller (HLC): There is only one HLC in each submodule. It is an event-driven block that can handle up to four concurrent events and execute predefined operations when an event occurs. It also provides data exchange and interrupt mechanisms for the CPU subsystem. There are four working registers (R0, R1, R2 and R3) for basic operations and modify or set the values ​​of three counter blocks.

[0034] Configurable exchange block: Provides dynamic connections between all the above blocks. Users can connect submodules, but cannot form loops within submodules.

[0035] Peripheral signal multiplexer: distributes the 8 outputs of the CLB logic block. These 8 outputs are replicated to create 16 output signals, each with a separate output enable bit in the CLB_OUT_EN register.

[0036] Specifically, the traditional DSP chip does not include a CLB module. In this embodiment, the digital signal processing DSP chip uses a TMS320F28P650DK chip, and its internal configurable logic module CLB can be used to replace the FPGA / CPLD chip to realize the switch tube delay function.

[0037] Compared with the traditional dual-chip solution, the technical solution of the present invention adopts a single chip and uses a unified clock to avoid delays. In addition, the overcurrent protection signal acquisition and special PWM signal processing are mature solutions provided by the chip, without the risks that may exist in self-written code, thereby improving the reliability of the protection function.

[0038] See also Figure 4 , showing the wave-generating activation delay logic, the specific steps of the wave-generating activation delay logic include: Step 1.1: When the tube is turned on, the PWM module of the digital signal processing DSP chip outputs the inner tube drive signal PWMxB0 and the outer tube drive signal PWMxA0; Step 1.2, set the PWM enable signal PWM_EN to a high level, and the event signal E1 to a high level; Step 1.3: The internal tube wave enable logic signal S2 is valid. The internal tube wave enable logic signal S2 is logically ANDed with the internal tube drive signal PWMxB0. The result of the operation is sent to the internal tube and drives the internal tube to turn on. Step 1.4, invert the event signal E1 and input the inverted signal into the first timer Timer0 to start timing the first timer Timer0; Step 1.5: After the first timer Timer0 reaches a predetermined time length, an event signal E2 is generated; Step 1.6: Perform a logic AND operation on the event signal E1 and the event signal E2. If the operation result is valid, an external tube wave enabling logic signal S1 is generated. Step 1.7: The external tube wave transmission enable logic signal S1 is valid. The external tube wave transmission enable logic signal S1 is logically ANDed with the external tube drive signal PWMxA0. The result of the operation is sent to the external tube and drives the external tube to be delayed and turned on.

[0039] The calculation formula of the external tube wave enabling logic signal S1 in step 1.6 is shown in formula (1): S1 = (S1&E2) |(~S1&E1)(1).

[0040] See also Figure 5 , showing the wave blocking shutdown delay logic, the specific steps of the wave blocking shutdown delay logic include: Step 2.1: When the tube is turned off, the PWM module of the digital signal processing DSP chip outputs the inner tube drive signal PWMxB0 and the outer tube drive signal PWMxA0; Step 2.2, the PWM enable signal PWM_EN is set to low level, and the event signal E3 is set to low level; Step 2.3: The external tube wave enable logic signal S1 is invalid, and the external tube wave enable logic signal S1 is logically ANDed with the external tube drive signal PWMxA0. The result of the operation is sent to the external tube and drives the external tube to shut down. Step 2.4: The wave-encapsulation enable signal E3 triggers the second timer Timer1, so that the second timer Timer1 starts timing; Step 2.5: After the second timer Timer1 reaches a predetermined time, an event signal E4 is generated; Step 2.6, perform a logic AND operation on the wave blocking enable signal E3 and the event signal E4, and generate an inner tube wave blocking enable logic signal S2 when the operation result is valid; Step 2.7: The inner tube wave blocking enable logic signal S2 is valid. The inner tube wave blocking enable logic signal S2 is logically ANDed with the inner tube drive signal PWMxB0. The result of the operation is sent to the inner tube and drives the outer tube to be turned off with a delay.

[0041] The calculation formula of the inner tube wave blocking enable logic signal S2 in step 2.6 is shown in formula (1): S2 = (S2&~E3) |(~S2&E4) (2).

[0042] See also Figure 6 , showing the timing diagram of the PWM wave-generating switch tube delay logic of the wave-generating turn-on delay logic and the wave-blocking turn-off delay logic.

[0043] Among them, in the wave-generating on-delay logic and the wave-blocking off-delay logic, The logic expression of the external tube PWM output is shown in formula (3): PWMxA = S1&PWMxA0(3); The logic expression of the inner tube PWM output is shown in formula (4): PWMxB = S1&PWMxB0 (4).

[0044] Preferably, the predetermined durations of the first timer Timer0 and the second timer Timer1 are preferably 5 us.

[0045] Specifically, in this embodiment, when the tube is opened, the opening delay time of the outer tube is Δt1 = 5us; when the tube is closed, the closing delay time of the inner tube is Δt2 = 5us.

[0046] Specifically, the specific experimental process of CLB is as follows: 1. After the module receives the wave enable signal E1 (high level at this time): The steps for generating the wave of the inner tube are as follows: Perform "AND" logic processing on E1 and the signal PWMxB0 output by the DSP's PWM module. That is, if PWMxB0 is low at this time, the "AND" result of the two is low, and the DSP's tube PWMxB pin outputs a low level; otherwise, the PWMxB pin outputs a high level, thus achieving the internal tube opening without delay.

[0047] The steps for generating the wave of the outer tube are as follows: When the input signal of Timer0 is high, the timer is in the reset state. The logic-high E1 is inverted to obtain a logic 0 and input to Timer0, which then starts timing. When the 5µs delay ends, event E2 is generated. E1 and E2 are input to the external controller enable logic expression (1) to obtain the external controller enable signal S1. Finally, a logical AND is performed on S1 and the signal PWMxA0 output by the DSP's PWM module. If the PWMxA pin is low at this time, the PWMxA pin is high, otherwise it is low. This delay in turning on the external controller is achieved through the CLB's Timer0, with a delay duration of Δt1 = 5µs.

[0048] 2. The processing logic of the external tube during blocking is as follows: When the wave is blocked, the external tube is immediately turned off. Therefore, when E3 is low, it is immediately ANDed with the external tube drive signal PWMxA0, making PWMxA0 output a low level, thus completing the step of immediately turning off the external tube.

[0049] The processing logic for delayed shutdown of the internal tube during wave blocking is as follows: When E3 is detected as low, the CLB's timer, Timer1, switches from the reset state to the counting state. When Timer1 reaches 5µs, event E4 is generated. E3 and E4 are input into expression (2) to obtain the internal transistor enable signal, S2, during the blocking phase. Then, a logical AND operation is performed on S2 and the internal transistor, PWMxB0. If PWMxB0 is low, the internal driver output is low; otherwise, it is high. The delay shutdown duration, Δt2, is 5µs.

[0050] Also, see Figure 7 , a wave-by-wave current limiting protection method for an NPC type three-level topology structure is shown, wherein the switching timing of the inner and outer switching tubes of the NPC type three-level inverter is adjusted by using the switching tube delay method of the NPC type three-level topology structure described above, and the specific steps include: Step 1: The hardware overcurrent detection signal OC_U / V / W is transmitted to the input port of the hardware fault protection module TZ; Step 2: When an overcurrent signal is detected, the TZ module (Trip-Zone Module) sets PWMxA to a low level and PWMxB to a high level. Among them, PWMxA is used to drive the outer tube, and PWMxB is used to drive the inner tube (x=1,2,3...6).

[0051] Step 3: Turn off the outer tube; at this time, the inner tube is still in the open state; Step 4: When the PWM counter underflow interrupt occurs, check whether the cycle-by-cycle current limit protection flag is valid; if valid, perform a logical AND operation on the cycle-by-cycle current limit protection flag and the operation signal GPIO25; if the operation result is a low-level signal, the low-level signal is input to the CLB wave generator module to turn off the output of PWMB; Step 5: Shut off the inner tube.

[0052] Specifically, when the signal of the wave-by-wave current limiting module is valid, the corresponding overcurrent signal flag will be set to 1, triggering the PWM interrupt, and the DSP will actively stop generating waves. At the same time, this signal will be sent to the CLB module, triggering the CLB's wave-blocking shutdown delay logic.

[0053] Specifically, when a hardware overcurrent occurs, the fully configurable logic module CLB starts the wave blocking shutdown delay logic to first shut down the external tube and then shut down the internal tube.

[0054] Preferably, when the hardware overcurrent signal is invalid, the PWM enable signal PWM_EN is set to a high level, starting the PWM start-up delay logic of the fully configurable logic module CLB to turn on the inner and outer switches in the NPC three-level inverter.

[0055] Specifically, in this embodiment, in order to achieve wave-by-wave current limiting while taking into account the timing of the I-type three-level switch tube, the following is achieved: Figure 7 The cycle-by-cycle current limiting logic is shown. OC_U / V / W are three-phase hardware overcurrent signals. When any of the three phases overcurrents and initiates cycle-by-cycle current limiting, these three signals are pulled low, triggering the TZ module to manipulate the PWM output levels. The design sets PWMA to a low level and PWMB to a high level when an overcurrent signal occurs. Because PWMxA (x = 1, 2, 3, ..., 6) drives transistors 1 and 4, the outer transistor is checked first when an overcurrent condition occurs. This is consistent with the "outer first, then inner" logic of Type I three-level transistors. Simultaneously, the PWM underflow interrupt checks whether the CBC module bit (cycle-by-cycle current limiting protection flag) is valid. If valid, it is logically ANDed with the run signal GPIO25, resulting in a low signal that is fed into the CLB wave generator module, shutting down the PWMB output. Ultimately, both PWMA and PWMB outputs are checked.

[0056] When the overcurrent signal is invalid, the "first inside, then outside" opening logic is automatically started.

[0057] Specifically, see Figures 8 to 10 , showing the actual test effect diagram of this technical solution.

[0058] Among them, PWN_EN represents the power-on enable signal, G1 is the driving signal of bridge arm 1 tube (outer tube), G2 is the driving signal of tube 2 (inner tube), G3 is the driving signal of tube 3 (inner tube), and G4 is the driving signal of tube 4 (outer tube). G1 and G3 are complementary, and G2 and G4 are complementary.

[0059] Figure 8 The following diagram shows the power-on PWM pulse operation. T1 represents the shutdown state, T2 represents the delayed activation of the external transistors, and T3 represents stable operation. Specifically, when the power-on enable signal PWM_EN transitions from low to high, the CLB module detects the rising edge and simultaneously sets the drive signals G2 and G3 for the two internal transistors high. The external transistors, G1 and G4, are then delayed and set high. Because the external transistor's drive signal G4 is low at the time of activation, the delayed activation of the four transistors is not visible in this diagram, but it actually exists. This ensures that the internal transistors are activated first, followed by the external transistors, during power-on.

[0060] Figure 9 The following is a diagram of the shutdown PWM pulse action, where T4 represents the stable operation phase, T5 represents the external transistor shutdown delay phase, and T6 represents the shutdown state for all G1-G4. Specifically, when the module receives the shutdown command and the power-on enable signal PWM_EN falls, the CLB immediately switches the drive signal G1 for transistor 1 (external transistor) from high to low. G3 for transistor 3 (inner transistor) and G4 for transistor 4 (external transistor) remain low. G2 for transistor 2 (inner transistor) is driven high. After a delay of Δt2, G1 for transistor 1 (external transistor) is turned off, and G2 for transistor 2 (inner transistor) is switched from high to low. This allows the external transistors to be shut down first, followed by the internal transistors, during power on / off.

[0061] Figure 10 The following diagram shows the PWM pulse operation that triggers the wave-by-wave current limiting function when an overcurrent signal occurs. Specifically, when the overcurrent signal occurs, the wave enable signal PWN_EN transitions from high to low. When the overcurrent signal is reset, the PWM_EN signal transitions from low to high. As shown in the diagram, at the start of segment T8, when the CLB detects the falling edge of PWN_EN, the drive signal G1 for transistor 1 immediately transitions from high to low. After a delay of Δt1, the drive signal G2 for transistor 2 transitions from high to low. When the PWM_EN signal returns to high, transistor 2 (the inner transistor) is first set to high. Since transistor 3 (the inner transistor) is currently low, it remains low. After a delay of Δt2, transistor 1 (the outer transistor) transitions to high. This implements the logic of shutting down the outer transistor before the inner transistor during wave-by-wave current limiting.

[0062] In the aforementioned NPC-type three-level topology switch delay method and wave-by-wave current limiting protection method, the digital signal processing (DSP) chip includes a configurable logic module (CLB). The CLB's wave-on delay logic and wave-off delay logic implement delay control of the NPC-type three-level topology switch, implementing wave-by-wave current limiting protection logic in the event of hardware overcurrent. This achieves the logic control requirements of switching the internal tube first, then the external tube, when opening the tube, and switching the external tube first, then the internal tube, when closing the tube. The present invention uses a single chip to implement delay control and wave-by-wave current limiting protection logic for the NPC-type three-level topology switch, simplifying the circuit's hardware structure and software complexity. The present invention's method is simple, easy to implement, low-cost, and easy to promote.

[0063] It should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for delaying a switch tube in an NPC three-level topology structure, used to control the switching timing of the inner and outer switch tubes in an NPC three-level inverter, characterized in that: The NPC-type three-level inverter includes a digital signal processing (DSP) chip, which includes a configurable logic module (CLB). The switching tube delay method includes wave-generating on-delay logic and wave-blocking off-delay logic. The wave-generating on-delay logic is used to control the delay of the external tube when the tube is turned on, and the wave-blocking off-delay logic is used to control the delay of the internal tube when the tube is turned off, so as to avoid damage to the switching tube (IGBT).

2. The method for delaying a switch of an NPC three-level topology structure according to claim 1, wherein: The configurable logic module CLB is used to implement digital logic control functions through hardware structure. The configurable logic module CLB includes a counter Counter, a finite state machine FSM, a lookup table module LUT4, an output lookup table module Output LUT, a high-level controller HLC, a configurable switching block, an input signal selector and a peripheral signal multiplexer.

3. The switch delay method of the NPC type three-level topology structure according to claim 1, characterized in that: The specific steps of the wave-generating opening delay logic include: Step 1.1: When the tube is turned on, the PWM module of the digital signal processing DSP chip outputs the inner tube drive signal PWMxB0 and the outer tube drive signal PWMxA0; Step 1.2, set the PWM enable signal PWM_EN to a high level, and the event signal E1 to a high level; Step 1.3: The internal tube wave enable logic signal S2 is valid. The internal tube wave enable logic signal S2 is logically ANDed with the internal tube drive signal PWMxB0. The result of the operation is sent to the internal tube and drives the internal tube to turn on. Step 1.4, invert the event signal E1 and input the inverted signal into the first timer Timer0 to start timing the first timer Timer0; Step 1.5: After the first timer Timer0 reaches a predetermined time length, an event signal E2 is generated; Step 1.6: Perform a logic AND operation on the event signal E1 and the event signal E2. If the operation result is valid, an external tube wave enabling logic signal S1 is generated. Step 1.7: The external tube wave transmission enable logic signal S1 is valid. The external tube wave transmission enable logic signal S1 is logically ANDed with the external tube drive signal PWMxA0. The result of the operation is sent to the external tube and drives the external tube to be delayed and turned on.

4. The switch delay method of the NPC three-level topology structure according to claim 3, characterized in that: The calculation formula of the external tube wave enabling logic signal S1 in step 1.6 is shown in formula (1): S1 = (S1 & E2) |(~S1 & E1) (1).

5. The switch delay method of the NPC three-level topology structure according to claim 3, characterized in that: The specific steps of the wave blocking and delay logic include: Step 2.1: When the tube is turned off, the PWM module of the digital signal processing DSP chip outputs the inner tube drive signal PWMxB0 and the outer tube drive signal PWMxA0; Step 2.2, the PWM enable signal PWM_EN is set to low level, and the event signal E3 is set to low level; Step 2.3: The external tube wave enable logic signal S1 is invalid, and the external tube wave enable logic signal S1 is logically ANDed with the external tube drive signal PWMxA0. The result of the operation is sent to the external tube and drives the external tube to shut down. Step 2.4: The wave-encapsulation enable signal E3 triggers the second timer Timer1, so that the second timer Timer1 starts timing; Step 2.5: After the second timer Timer1 reaches a predetermined time, an event signal E4 is generated; Step 2.6, perform a logic AND operation on the wave blocking enable signal E3 and the event signal E4, and generate an inner tube wave blocking enable logic signal S2 when the operation result is valid; Step 2.7: The inner tube wave blocking enable logic signal S2 is valid. The inner tube wave blocking enable logic signal S2 is logically ANDed with the inner tube drive signal PWMxB0. The result of the operation is sent to the inner tube and drives the outer tube to be turned off with a delay.

6. The switch delay method of the NPC three-level topology structure according to claim 5, characterized in that: The calculation formula of the inner tube wave sealing enable logic signal S2 in step 2.6 is shown in formula (1): S2 = (S2 & ~E3) |(~S2 & E4) (2).

7. The method for delaying a switch tube in an NPC three-level topology structure according to claim 5, wherein: In the wave-generating on-delay logic and the wave-blocking off-delay logic, The logic expression of the external tube PWM output is shown in formula (3): PWMxA = S1 & PWMxA0 (3); The logic expression of the inner tube PWM output is shown in formula (4): PWMxB = S1 & PWMxB0 (4).

8. The switch delay method of the NPC three-level topology structure according to claim 5, characterized in that: The predetermined durations of the first timer Timer0 and the second timer Timer1 are preferably 5 us.

9. A wave-by-wave current limiting protection method for an NPC type three-level topology structure, characterized in that: The switching timing of the inner and outer switching tubes in the NPC three-level inverter is adjusted by using the switching tube delay method of the NPC three-level topology structure according to any one of claims 1 to 8, and the specific steps include: Step 1: The hardware overcurrent detection signal OC_U / V / W is transmitted to the input port of the hardware fault protection module TZ; Step 2: When an overcurrent signal is detected, the TZ module sets PWMxA to a low level and PWMxB to a high level; Step 3: The outer tube is turned off and the inner tube is in the open state; Step 4: When the PWM counter underflow interrupt occurs, check whether the cycle-by-cycle current limit protection flag is valid; if valid, perform a logical AND operation on the cycle-by-cycle current limit protection flag and the operation signal GPIO25; if the operation result is a low-level signal, the low-level signal is input to the CLB wave generator module to turn off the output of PWMB; Step 5: Shut off the inner tube.

10. The wave-by-wave current limiting protection method for an NPC three-level topology structure according to claim 9, characterized in that: When the hardware overcurrent signal is invalid, the PWM enable signal PWM_EN is set to a high level, starting the PWM start-up delay logic of the fully configurable logic module CLB to turn on the inner and outer tubes of the switch tubes in the NPC type three-level inverter.

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