Miniature light emitting diode chip

Abstract

The invention provides a micro light emitting diode chip, comprising a micro mesa array comprising a plurality of micro mesas; the light emitting diode is characterized in that each micro-mesa comprises a first type semiconductor layer, a light emitting layer and a second type semiconductor layer which are sequentially stacked from bottom to top; the first type is different from the second type; the bottom metal layer is located at the bottom of the micro mesa; the bottom dielectric layer is located at the bottom of the bottom metal layer; the bottom dielectric layer is provided with a groove; the first bottom contact hole is located in the bottom dielectric layer and located at the bottom of the bottom metal layer, and the first bottom contact hole is in contact with the bottom metal layer; the side wall dielectric layer is positioned on the side wall of the micro mesa and the side wall of the bottom metal layer; the top conductive layer continuously covers the top surfaces of the micro mesas, the surfaces of the side wall cut-off layers and the areas between the adjacent micro mesas; and the second bottom contact structure is positioned in the groove, is positioned in the bottom dielectric layer between the adjacent micro mesas, and is not in contact with the bottom metal layer.

Description

Technical Field

[0001] The present invention relates to the technical field of light emitting diodes, and more specifically, to a micro light emitting diode chip. Background Art

[0002] Micro Light Emitting Diode (MLED) technology is a high-pixel density LED flat display technology that uses micron-sized LEDs as pixel elements and is assembled on a control backplane at a micron-sized period. The core structure of a MLED is a PN junction diode, which is composed of direct bandgap semiconductor materials. When the upper and lower electrodes apply a forward bias to the MLED to allow current to flow, electrons and holes recombine in the active region and emit single-color photons at the same time.

[0003] Compared with traditional LEDs, Micro LEDs have better strain relaxation, better light extraction efficiency, uniform current diffusion, and higher output performance. Micro LEDs also have the advantages of improved thermal effects, faster response, wider operating temperature range, higher resolution, wider color gamut, higher contrast, lower power consumption, and higher current density. Micro LEDs are hailed as the next generation of display technology and are receiving more and more attention.

[0004] However, in the future, micro-LED chips will develop towards higher resolution and pixel density, thus presenting clearer and more delicate images. However, when the pitch of the micro-LED array, that is, the minimum center distance between micro-LEDs, is less than 3 microns, the interval between adjacent micro-LEDs will become extremely small, which puts extremely stringent requirements on the processing technology of micro-LED chips.

[0005] For example, when dealing with such a small pitch structure, the photoresist performance, exposure dose control and lithography equipment accuracy must all reach top levels. A slight lithography error may cause adjacent micro-LEDs to short-circuit or the shape of the light-emitting area to deviate, which will seriously affect the display effect. In addition, electrode deposition between adjacent micro-LEDs is another problem. At such a small scale, it is difficult to form an electrode layer of the desired shape.

[0006] Therefore, a new type of micro light emitting diode chip is needed, which can at least partially solve the problems existing in the prior art. Summary of the invention

[0007] In view of some or all of the problems in the prior art, the task of the present invention is to provide a micro light-emitting diode chip, a micro mesa array, including a plurality of micro mesas; characterized in that each micro mesa includes: a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer stacked in sequence from bottom to top; the first type and the second type are different; a bottom metal layer located at the bottom of the micro mesa; a bottom dielectric layer located at the bottom of the bottom metal layer; the bottom dielectric layer has a trench; a first bottom contact hole located in the bottom dielectric layer and at the bottom of the bottom metal layer and the first bottom contact hole is in contact with the bottom metal layer; a sidewall dielectric layer located on the sidewalls of the micro mesa and the sidewalls of the bottom metal layer; a top conductive layer continuously covering the top surface of the micro mesa, the surface of the sidewall cutoff layer, and the area between adjacent micro mesas; a second bottom contact structure located in the trench and in the bottom dielectric layer between adjacent micro mesas and not in contact with the bottom metal layer.

[0008] In some embodiments, the top of the second bottom contact structure is lower than the bottom of the bottom metal layer; and lower than the top of the trench.

[0009] In some embodiments, the lateral width of the second bottom contact structure is smaller than the lateral width of the gap between adjacent bottom metal layers.

[0010] In some embodiments, the top conductive layer also covers the top surface of the second bottom contact structure.

[0011] In some embodiments, a plurality of the second bottom contact structures are integrally connected to each other.

[0012] In some embodiments, the second bottom contact structures are arranged in a transverse and longitudinal cross-interconnection pattern around the first bottom contact holes under each micro mesa, and the trenches are also arranged in a transverse and longitudinal cross-interconnection pattern in the bottom dielectric layer and around the first bottom contact holes under each micro mesa.

[0013] In some embodiments, at the transverse and longitudinal cross-points of the second bottom contact structures, the top conductive layer is in contact with the top surface of the second bottom contact structures.

[0014] In some embodiments, the first bottom contact holes and the second bottom contact structures are arranged alternately.

[0015] In some embodiments, the spacing between the sidewalls of the trench above the second bottom contact structure is greater than the spacing between the sidewalls of the trench in contact with the second bottom contact structure.

[0016] In some embodiments, the material of the first bottom contact hole is metal; the material of the second bottom contact structure is metal.

[0017] In some embodiments, the metal is one or more of copper, gold, tin, platinum, tungsten, and chromium.

[0018] In some embodiments, the sidewall dielectric layer coats the entire sidewall of the micro mesa structure and the entire sidewall of the bottom metal layer, and has an opening at the top of the micro mesa structure; the opening exposes part or all of the top of the micro mesa.

[0019] In some embodiments, a bottom conductive layer is further provided at the bottom of the first-type semiconductor layer; the bottom metal layer is located at the bottom of the bottom conductive layer; the light-emitting layer is a multi-layer stack; the first-type semiconductor layer is an N-type, and the second-type semiconductor layer is a P-type; or, the first-type semiconductor layer is a P-type, and the second-type semiconductor layer is an N-type.

[0020] In some embodiments, a metal island layer is further included at the top of the second-type semiconductor layer; the metal island layer contains multiple mutually isolated metal particles.

[0021] The technical solution provided by the present invention has the following beneficial effects:

[0022] 1. The first bottom contact hole of the micro light-emitting diode structure provided by the present invention is electrically connected to the first-type semiconductor layer of the micro mesa through the bottom metal layer and the bottom conductive layer, and the second bottom contact structure is electrically connected to the second-type semiconductor layer of the micro mesa through the top conductive layer. The first bottom contact hole and the second bottom contact structure, as the positive and negative electrodes of the micro light-emitting diode, are both arranged in the bottom dielectric layer below the micro mesa. The bottom dielectric layer is located on the top surface of the driving backplane. The first bottom contact hole is electrically connected to the driving circuit in the driving backplane, and the second bottom contact structure is led out at the edge of the micro mesa array and electrically connected to the external pad. Burying the second bottom contact structure as the top electrode of the micro light-emitting diode into the bottom dielectric layer of the driving backplane can prevent the second bottom contact structure from blocking the micro mesa, thereby increasing the light extraction rate.

[0023] 2. The structure proposed by the present invention avoids arranging the top electrode on the side of the micro mesa, reduces the light absorption effect of the top electrode on the side, and the beam collimation effect of the microlens is better.

[0024] 3. The micro light-emitting diode structure provided by the present invention improves the microlens. By improving the profile of the microlens, the height of the lower spacer, the radius of curvature, and the lens ball height are adjusted, thereby improving the micro defects of the lens, and further effectively improving the brightness or luminous efficiency of the micro light-emitting diode chip. The specific technical effects are as follows. The advantage of increasing the height of the lower spacer lies especially in that: on the premise of determining the radius of curvature, when the light source emits from the upper bottom of the pixel as the main radiation mode, as the radius of curvature increases and the height of the lower spacer is increased, the radius of the emitted light increases, and the emission angle of the same point light source microlens and the air interface decreases, so that the emission angle can be increased; the smaller the radius of curvature, that is, the wider the ball width of the microlens, is beneficial to light emission. Correspondingly, as the ball height increases, that is, the ball height of the original hemispherical microlens is changed, the escaping light can also be emitted from the microlens. By changing the curvature, the total emission angle of the microlens is increased, making it not easy to form total reflection light, which is beneficial to the light emission effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be further described below with reference to the specific embodiments in conjunction with the accompanying drawings.

[0026] Figure 1 The top view schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention is shown.

[0027] Figure 2 The longitudinal sectional schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention along line AA is shown.

[0028] Figure 3 The schematic top view of the first bottom contact hole 111 and the second bottom contact structure 112 according to an embodiment of the present invention is shown.

[0029] Figure 4 The longitudinal sectional schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention is shown.

[0030] Figure 5 The longitudinal sectional schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] It should be noted that the components in the drawings may be exaggerated for illustration purposes and are not necessarily drawn to scale. In the drawings, the same or functionally identical components are provided with the same reference numerals.

[0032] In the present invention, unless otherwise specified, "disposed on", "disposed above", and "disposed on top of" do not exclude the presence of an intermediate object between the two. In addition, "disposed on or above" only represents the relative positional relationship between the two components, and in certain cases, such as when the product direction is reversed, it can also be converted to "disposed under or below", and vice versa.

[0033] In the present invention, each embodiment is only intended to illustrate the solution of the present invention and should not be construed as restrictive.

[0034] In the present invention, unless otherwise specified, the quantifiers "a" and "one" do not exclude the scenario of multiple elements.

[0035] In the present invention, the term "connection" can refer to both direct connection between two entities and indirect connection between two entities through an intermediate element.

[0036] In the present invention, the term "configured" means setting the shape, structure, material, and / or function of an object to achieve the desired technical effect, where "configured" includes various alternative technical means for achieving this technical effect, and these technical means become obvious under the teaching of the present invention.

[0037] It should also be noted here that in the embodiments of the present invention, for the sake of clarity and simplicity, only a part of the components or assemblies may be shown. However, those of ordinary skill in the art can understand that, under the teaching of the present invention, the required components or assemblies can be added according to the specific scenario requirements. Additionally, unless otherwise stated, the features in different embodiments of the present invention can be combined with each other. For example, a certain feature in the second embodiment can be used to replace the corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the scope of the disclosure or the scope of the record of this application.

[0038] It should also be noted here that within the scope of the present invention, the terms "identical", "equal", "equal to", etc. do not mean that the two values are absolutely equal, but allow for a certain reasonable error. That is to say, the terms also cover "substantially identical", "substantially equal", "substantially equal to". By analogy, in the present invention, the terms indicating direction such as "perpendicular to" and "parallel to" also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0039] In the present invention, the term "located at the bottom of the micro-tabletop" refers to the side of the micro-tabletop facing away from the microlens, the term "located at the top of the micro-tabletop" refers to the side of the micro-tabletop facing the microlens, and the term "side of the micro-tabletop" refers to the two sides between the top and the bottom.

[0040] In the present invention, the term "profile of the metal layer" refers to the maximum dimension, such as length, in the plane (or the plane perpendicular to the thickness) formed by the length and width of the metal layer. Similarly, the bottom profile of the micro-tabletop refers to the maximum dimension, such as length, of the micro-tabletop in the bottom plane (i.e., the plane perpendicular to the thickness at the bottom).

[0041] The following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention.

[0042] Figure 1 The top view schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention is shown. Figure 1 It includes a micro light-emitting diode and a microlens 140. Figure 2 The longitudinal sectional schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention along line AA is shown. As shown in the figure, the micro light-emitting diode chip includes a driving backplane 110, a micro light-emitting diode, a bottom metal layer 130, and a microlens 140. The micro light-emitting diode is arranged on the upper surface of the driving backplane 110. The bottom metal layer 130 is located between the driving backplane and the micro light-emitting diode. The microlens 140 is arranged on the upper surface of the micro light-emitting diode, and adjacent microlenses 140 are spaced apart between the micro light-emitting diodes. In some embodiments of the present invention, the driving module includes the driving backplane 110.

[0043] The micro light-emitting diode includes: a bottom conductive layer 150, a micro mesa 120, a sidewall dielectric layer 160, and a top conductive layer 170. The micro light-emitting diode is arranged on the upper surface of the driving backplane 110. The upper surface of the driving backplane 110 includes a first bottom contact hole 111, a second bottom contact structure 112, and a bottom dielectric layer 113 surrounding the first bottom contact hole 111 and the second bottom contact structure 112. The first bottom contact hole 111 is located at the bottom of the bottom metal layer 130, and the first bottom contact hole 111 is in contact with the bottom metal layer 130 and forms an electrical connection. The bottom metal layer 130 is electrically connected to the bottom conductive layer 150, and the bottom conductive layer 150 is arranged at the bottom of the micro mesa 120. The second bottom contact structure 112 is located in the trench and in the bottom dielectric layer 113 between adjacent micro mesas 120, and is not in contact with the bottom metal layer 130.

[0044] The size of each micro light-emitting diode chip does not exceed 1 cm, preferably does not exceed 5 mm. The micro light-emitting diodes are formed in an array in the micro light-emitting diode chip, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro light-emitting diode structure is at the nanometer level, for example, 20 nm to 100 nm. Each micro light-emitting diode can form at least a part of the pixel element on the micro light-emitting diode chip.

[0045] Introduction to the driving backplane 110:

[0046] For convenience, "upward" is used to indicate away from the driving backplane 110, "downward" indicates toward the driving backplane 110, and other directional terms such as top, bottom, above, below, directly below, underneath, etc. are interpreted accordingly. In some embodiments of the present invention, the driving backplane 110 includes a substrate (not shown in the figure), a driving circuit (not shown in the figure), a first bottom contact hole 111, a second bottom contact structure 112, and a bottom dielectric layer 113 surrounding the first bottom contact hole 111 and the second bottom contact structure 112. The first bottom contact hole 111 may also be referred to as the driving electrode of the driving circuit.

[0047] In some embodiments of the present invention, the substrate is a Si substrate. In other embodiments of the present invention, the substrate is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. In some embodiments, the substrate is about 700 micrometers thick.

[0048] The driving circuit forms individual pixel drivers to control the operation of each single micro-LED pixel. The driving circuit includes, for example, complementary metal oxide semiconductor (CMOS) devices or TFT devices, etc.

[0049] Each first bottom contact hole 111 corresponds to a micro-light emitting diode, and each first bottom contact hole 111 is electrically connected to the bottom metal layer 130. In some embodiments of the present invention, the material of the first bottom contact hole 111 is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Sn, W, Cr, Pt, and Au.

[0050] In some embodiments of the present invention, first, a light-emitting epitaxial layer structure of the micro-light emitting diode is fabricated on the surface of the epitaxial substrate. Then, the light-emitting epitaxial layer structure of the micro-light emitting diode can be bonded to the surface of the driving backplane 110 through the bottom metal layer 130, and the bonding between the driving backplane 110 and the micro-light emitting diode can be achieved by high-temperature and high-pressure bonding methods such as eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding.

[0051] Introduction to the bottom metal layer 130:

[0052] In some embodiments of the present invention, the bottom metal layer 130 may be disposed on the driving backplane 110. In some other embodiments of the present invention, the bottom metal layer 130 grows on the driving backplane 110. In some embodiments of the present invention, the thickness of the bottom metal layer 130 is from 0.1 micrometer to 3 micrometers. In a preferred embodiment, the thickness of the bottom metal layer 130 is 0.6 micrometers. In some embodiments of the present invention, the bottom metal layer 130 includes a first metal layer (not shown in the figure) and a second metal layer (not shown in the figure). The first metal layer is in direct contact with the bottom conductive layer 150 at the bottom of the micro mesa 120, and the second metal layer is located at the bottom layer of the bottom metal layer 130. In some embodiments of the present invention, one or more third metal layers are further disposed between the first metal layer and the second metal layer. By making the bottom metal layer 130 have multiple metal layers, firstly, the total thickness of the bottom metal layer 130 can be flexibly controlled by depositing multiple metal layers multiple times during the manufacturing process; secondly, the material selection of each metal layer is also more flexible. For example, the first metal layer in direct contact with the bottom of the bottom conductive layer 150 can select a metal material that is not likely to diffuse into the bottom conductive layer 150 or will not cause serious consequences even if it diffuses, or a metal material with a small contact resistance with the bottom conductive layer 150. The intermediate layer can select a metal material with good conductivity, and the second metal layer at the bottom layer can select a metal material with good bonding property with the driving backplane 110. In some embodiments of the present invention, the material of the first metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the second metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the third metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn. In some embodiments, the bottom metal layer 130 can also be used as a reflector to reflect the light emitted from the LED structure above.

[0053] In an embodiment of the present invention, after the bonding is completed, the epitaxial substrate can be removed by laser lift-off. The material of the epitaxial substrate can be sapphire or silicon. The corresponding lift-off process can be selected according to the material of the epitaxial substrate. After the epitaxial substrate is removed, the purpose of transferring the epitaxial light-emitting structure to the driving backplane 110 can be achieved. Removing the epitaxial substrate can further thin the epitaxial buffer layer structure, facilitating the subsequent PN step process of the epitaxial structure.

[0054] In an embodiment of the present invention, after the bonding is completed, the light-emitting epitaxial layer is etched to form the micro mesa 120, and by adjusting the lithography topography, the ion etching forms a micro light-emitting diode pixel point with a positive trapezoidal structure.

[0055] As Figure 2As shown, in some embodiments, the driving backplane 110 may employ an integrated circuit (IC) board. The micro light-emitting diodes are electrically connected to the driving backplane 110, and the driving backplane 110 is used to control the lighting and extinguishing of the micro light-emitting diodes. In some embodiments, the integrated circuit board may be electrically connected to each micro light-emitting diode in the micro light-emitting diode array through separate metal interconnections. In some embodiments, each micro light-emitting diode may be individually electrically controlled by the integrated circuit board. In some embodiments, the integrated circuit board may be electrically connected to the first bottom contact hole 111 through a metal interconnection. In some embodiments, a dielectric layer may be formed in the gap between the micro light-emitting diodes. In some embodiments, the dielectric layer may also be formed in the gap between the interconnections.

[0056] In some embodiments, the micro light-emitting diode chip includes a plurality of micro light-emitting diode arrays, and each micro light-emitting diode array includes a plurality of micro light-emitting diodes. The driving method of the micro light-emitting diodes is, for example, passive matrix (PM) driving, in which the cathodes of all the micro light-emitting diodes in each array are commonly connected to the cathode line NL, and the micro light-emitting diodes with the same number in each array are respectively connected to the corresponding anode lines PL. Thus, the on / off and light-emitting brightness of each micro light-emitting diode can be individually controlled by controlling the signals on the corresponding cathode line and anode line.

[0057] In some embodiments, the micro light-emitting diodes may be arranged in a regular or irregular manner on the upper surface of the driving module as the pixel points of the micro light-emitting diode chip. In the micro light-emitting diode, the bottom conductive layer 150 is located at the bottom of the micro mesa 120, and the bottom conductive layer 150 is electrically connected to the bottom metal layer 130. The top conductive layer 170 is located on the side and top surfaces of the micro mesa 120, and the top conductive layer 170 is electrically connected to the second bottom contact structure 112.

[0058] In some embodiments, the sidewall dielectric layer 160 at least partially covers the sidewalls of the micro mesa 120 and the sidewalls of the bottom metal layer 130, and the sidewall dielectric layer 160 is located between the micro mesa 120 and the top conductive layer 170. In some embodiments, the sidewall dielectric layer 160 may cover a portion of the top surface of the micro mesa 120. In some embodiments, materials such as silicon dioxide, silicon nitride, silicon oxide, silicon oxynitride, etc. are deposited as the sidewall dielectric layer using plasma enhanced chemical vapor deposition or atomic layer deposition processes. A photolithography opening process is performed on the top surface of the sidewall dielectric layer 160 on the top surface of the micro mesa 120 through a photolithography process, etching to expose at least a part of the surface of the top surface of the micro mesa 120, and electrical contact between the micro mesa 120 and the top conductive layer 170 is achieved through the opening in the sidewall dielectric layer. In some embodiments of the present invention, adjacent sidewall dielectric layers are connected, and all sidewall dielectric layers are connected into a whole. In some embodiments of the present invention, the material of the sidewall dielectric layer is one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0059] In some embodiments, the electrode polarity of the bottom conductive layer 150 is opposite to the electrode polarity of the top conductive layer 170. The bottom conductive layer 150 can be, for example, a P electrode or an anode electrode, while the top conductive layer 170 is an electrode with a polarity opposite to that of the bottom conductive layer 150, such as an N electrode or a cathode electrode. In some embodiments of the present invention, the bottom conductive layer 150, the top conductive layer 170, and their connecting components can be a combination of one or more of materials such as graphene, indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0060] In some embodiments of the present invention, the top conductive layer 170 can be formed on the top surface of the micro mesa 120 and the top surface of the sidewall dielectric layer 160 using a sputtering process.

[0061] In some embodiments of the present invention, adjacent top conductive layers 170 are connected, and all top conductive layers 170 are connected into a whole. In some embodiments of the present invention, the top conductive layer 170 is a transparent electrode for the entire display area and can be made of the conductive material indium tin oxide. In some embodiments of the present invention, the top conductive layer 170 can be formed using processes such as sputtering or electron beam evaporation.

[0062] In some embodiments, the top conductive layer 170 can be shared by all the micro light-emitting diodes in the micro light-emitting diode array.

[0063] In some embodiments, the top conductive layer 170 is electrically connected to the second bottom contact structure 112. In some embodiments, the plurality of second bottom contact structures 112 are integrally connected to each other. The second bottom contact structure 112 can be used as a common electrode and is connected to each micro mesa in the micro light-emitting diode array. The second bottom contact structure 112 can electrically connect the second type semiconductor layer 122 of the micro mesa 120 to the negative electrode of an external power supply. The second bottom contact structure 112 can also be referred to as the N electrode.

[0064] In some embodiments, the second bottom contact structure 112 is located in the trench of the bottom dielectric layer 113. Figure 3 A schematic top view of the first bottom contact hole 111 and the second bottom contact structure 112 according to an embodiment of the present invention is shown. As Figure 3 shown, the first bottom contact holes 111 and the second bottom contact structures 112 are arranged alternately. The second bottom contact structures 112 are arranged in a horizontally strip-shaped and vertically cross-connected manner around the first bottom contact holes 111 under each micro mesa, and the trenches are also arranged in a horizontally and vertically cross-connected manner in the bottom dielectric layer 113 and around the first bottom contact holes 111 under each micro mesa 120. In some embodiments, the second bottom contact structure 112 extends under the micro mesa and leads out at the edge of the micro mesa array and is electrically connected to an external pad. In some embodiments, the material of the first bottom contact hole 111 is metal, and the material of the second bottom contact structure 112 is metal. For example, the metal is one or more of copper, gold, tin, platinum, tungsten, chromium, rhodium, titanium, silver, germanium, and nickel.

[0065] In some embodiments, the top conductive layer 170 covers at least a part of the top surface of the second bottom contact structure 112. In order to avoid short-circuiting between the first type semiconductor layer 121 and the second type semiconductor layer 122 of the micro mesa 120, the second bottom contact structure 112 cannot contact the bottom metal layer 130. The lateral width of the second bottom contact structure 112 can be made smaller than the lateral width of the gap between adjacent bottom metal layers 130, so as to avoid the bottom surface of the bottom metal layer 130 contacting the top surface of the second bottom contact structure 112.

[0066] From Figure 1It can be seen that along the direction of line BB, the spacing distance between the micro - mesa surfaces is the smallest, while along the direction of line AA, the spacing distance between the micro - mesa surfaces is the largest. In some embodiments, the top conductive layer 170 contacts only above the horizontal and vertical intersection points of the second bottom contact structure 112. The other regions of the second bottom contact structure 112 are covered by the bottom dielectric layer 113 on top. The advantage of this structure is that it can reduce the process difficulty and avoid processes such as etching and top conductive layer deposition in small - sized voids. However, those skilled in the art should understand that in the above - mentioned embodiments, the contact position of the top conductive layer 170 and the second bottom contact structure 112 is shown schematically rather than restrictively. In other embodiments of the present invention, the top conductive layer 170 can contact the top surface of the second bottom contact structure 112 at any appropriate position.

[0067] In some embodiments of the present invention, the micro - mesa 120 can be a trapezoidal platform, and the bottom lateral dimension of the micro - mesa 120 is larger than the top lateral dimension. In some embodiments of the present invention, the inclination angle range of the side wall of the micro - mesa 120 is: 60° - 85°. In some embodiments of the present invention, the bottom lateral dimension of the micro - mesa 120 does not exceed 3 microns. In some embodiments of the present invention, the top lateral dimension of the micro - mesa 120 does not exceed 1.5 microns. In some embodiments of the present invention, the lateral dimensions of the bottom conductive layer 150 and the bottom metal layer 130 are larger than the bottom lateral dimension of the micro - mesa 120.

[0068] As Figure 2As shown, the micro mesa 120 includes a first-type semiconductor layer 121, a second-type semiconductor layer 122, and a light-emitting layer 123 located therebetween. The first-type semiconductor layer 121 is electrically connected to the bottom conductive layer 150. The second-type semiconductor layer 122 is electrically connected to the top conductive layer 170. In some embodiments, the micro mesa 120 of each micro light-emitting diode in the micro light-emitting diode array can be a micrometer-scale micro mesa 120. In some embodiments, the micrometer-scale micro mesa 120 can include, from bottom to top, a first-type semiconductor layer 121, a light-emitting layer 123, and a second-type semiconductor layer 122. That is to say, in the three-layer structure, the first-type semiconductor layer 121 is closest to the driving backplane 110; the light-emitting layer 123 is located above the first-type semiconductor layer 121 and is farther from the driving backplane 110; the second-type semiconductor layer 122 is located above the light-emitting layer 123 and is the farthest from the driving backplane 110. In some embodiments, the light-emitting layer 123 is formed by a plurality of stacked quantum well layers, especially superlattice-stacked quantum well layers. Preferably, the superlattice-stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first-type semiconductor layer 121 is a semiconductor material having a first conductivity type and includes multiple semiconductor layers. The main matrix material of the first-type semiconductor layer 121 can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the first-type semiconductor layer 121 can include, from top to bottom, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, the bottom conductive layer 150 can be formed below the window layer. In some embodiments, the second-type semiconductor layer 122 is a semiconductor material having a second conductivity type and includes multiple semiconductor layers. The main matrix material of the second-type semiconductor layer 122 can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the second-type semiconductor layer 122 can include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, the top conductive layer 170 can be formed on the confinement layer. In some embodiments of the present invention, the first conductivity type is different from the second conductivity type.

[0069] In some embodiments, the first-type semiconductor layer 121 is an N-type GaN layer or an N-type AlGaN layer, and the second-type semiconductor layer 122 is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second-type semiconductor layer 122 can be a material layer of the second conductivity type composed of at least two or more elements including Ga, N, As, Al, In, and P, and the first-type semiconductor layer 121 can be a material layer of the first conductivity type composed of at least two or more elements including Ga, N, As, Al, In, and P. In some embodiments, the light-emitting layer 123 includes a multi-quantum well layer and an electron blocking layer, and the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In some embodiments, the light-emitting layer 123 further includes an electron blocking layer, and the electron blocking layer is disposed on a first side of the light-emitting layer 123, and the first side refers to the side along which electrons migrate out of the light-emitting layer 123. In other embodiments of the present invention, the first-type semiconductor layer 121 can also be a P-type GaN layer or a P-type AlGaN layer, and the second-type semiconductor layer 122 is an N-type GaN layer or an N-type AlGaN layer.

[0070] In some embodiments, the light-emitting layer 123 includes at least one quantum well layer (not shown in the figure). The thickness of the quantum well layer is between 20 nm and 40 nm, for example, the thickness is 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9, and the range of y is from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y.

[0071] In some embodiments, one of the first-type semiconductor layer 121 and the second-type semiconductor layer 122 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al x In 1-x P, where the range of x is from 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm. For example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17 cm -3 to 1e 18 cm -3。The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e 18 cm -3 to 1e 19 cm -3 。In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is 0.5 to 0.9 and the range of y is 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is 50 nm to 75 nm, for example 65 nm.

[0072] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer 123, and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, where x is 0.3 to 0.5, for example x is 0.5. In such embodiments, the thickness of the P-type cladding layer is not greater than 380 nm. For example, the thickness of the P-type cladding layer is 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is 10 nm to 30 nm, for example 20 nm.

[0073] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is 0.5 to 0.9 and the range of y is 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is 50 nm to 70 nm, for example 65 nm.

[0074] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y In 1-yP, where the range of x is from 0.1 to 0.3, and the range of y is from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times of x. In some embodiments, the thickness of the first doped P-type transition layer is from 20 nm to 40 nm, such as 30 nm.

[0075] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, where the range of x is from 0.5 to 0.9, for example x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, such as 20 nm.

[0076] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second doped P-type transition layer.

[0077] In some embodiments, the doping concentration of the doped P-type contact layer is greater than that of the second doped P-type transition layer. In addition, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times that of the first doped P-type transition layer.

[0078] For example, the doping concentration of the first doped P-type transition layer is greater than 1e 18 cm -3 , the doping density of the second doped P-type transition layer is in the range of 2e 18 cm -3 -4e 18 cm -3 , and the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0079] Figure 2 In, the lateral dimension of the bottom of the microlens 140 is greater than the lateral dimension of the light-emitting region of the micro light-emitting diode. In some embodiments, the lateral dimension of the bottom of the microlens 140 may be equal to the lateral dimension of the light-emitting region of the micro light-emitting diode.

[0080] In some embodiments, a microlens 140 may cover a plurality of lensless micro light-emitting diodes. A plurality of microlenses form a microlens array. The microlens array is disposed above the micro light-emitting diode array, wherein at least one microlens is disposed on the surface of the top conductive layer of the micro light-emitting diode, and the horizontal profile of the microlens is larger than the maximum horizontal profile of the micro light-emitting diode. The microlens is mainly used to converge and / or collimate light. For example, by adjusting parameters such as the thickness and curvature of the microlens, the focal point of the microlens can be located in the micro mesa 120 of the micro light-emitting diode. The microlenses in the microlens array are usually the same. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses, and cylindrical microlenses. As Figure 2 shown, in some embodiments of the present invention, the microlens 140 includes an upper curvature portion and a lower spacer portion. In some embodiments of the present invention, the typical shape of the lower spacer portion of each microlens 140 includes a circle, a square, a rectangle, and a hexagon. Each microlens in the microlens array of the display panel may be the same or different in terms of shape, curvature, optical power, size, base, spacing, etc.

[0081] In some embodiments of the present invention, the centers of curvature at various positions on the side wall of the lower spacer portion do not coincide with the centers of curvature at various positions of the upper curvature portion. The thickness of the lower spacer portion is set such that the focal point of the microlens is located in the micro mesa 120 of the micro light-emitting diode. In some embodiments of the present invention, the height of the lower spacer portion of the microlens is 0.5 to 3 microns, and / or the height of the upper curvature portion of the microlens is 0.5 to 2 microns, and / or the spherical width of the microlens is 3 to 4 microns. In yet another embodiment, the microlens may be, for example, a positive hemisphere.

[0082] In some embodiments, the shape of the microlens 140 may be a curved hemisphere. In some embodiments, the height of the microlens 140 is not greater than 2 microns. In some embodiments, the height of the microlens 140 is not greater than 1 micron. In some embodiments, the height of the microlens 140 is not greater than 0.5 micron. In some embodiments, the width of the microlens 140 is not greater than 4 microns. In some embodiments, the width of the microlens 140 is not greater than 3 microns. In some embodiments, the width of the microlens 140 is not greater than 2 microns. In some embodiments, the width of the microlens 140 is not greater than 1 micron. In some embodiments, the width-to-height ratio of the microlens 140 is greater than 1.5.

[0083] In some embodiments, the microlens 140 may be made of various materials that are transparent to light of various wavelengths emitted by the micro light-emitting diodes. Exemplary transparent materials for the microlens 140 include polymers and dielectric materials. In some embodiments, the dielectric material includes one or more materials such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, the microlens 140 is made of a photoresist.

[0084] In some embodiments, the manufacturing process of the microlens 140 is mainly based on CVD deposition of SiO2 film layer. Since the actual deposited film thickness varies from 2.5 to 4um, the deposition procedure used is generally a high deposition rate film forming method, which will cause deposition defects and micro cracks in the deep groove area. After the deposition is completed, a photoresist with suitable viscosity is selected, such as a positive photoresist, to coat the wafer surface, and then the light shielding area of the exposure photomask is overlapped with the pixel position, and then exposed to form the microlens 140 photolithography pattern, and the photoresist morphology is fully exposed for a second time and the hard film is baked to improve it, so that the photoresist shrinks due to the photosensitivity and thermal characteristics, and the cross-section forms a hemispherical morphology. At this point, the photolithography process is completed, and ICP dry etching is performed subsequently, which is ion etching dominated by chemical etching. Then, based on the photolithography hemispherical morphology, according to the actual deposited SiO2 thickness, a certain SiO2 etching time is set to obtain the remaining etching margin, and a similar etching pattern can be formed at this time. Figure 1 The appearance of the microlens 140 is shown. Since the etching rate of SiO2 is relatively stable and highly controllable, the desired etching depth can be achieved by setting the etching time, wherein the position of the microlens 140 is photoetched to form a hemispherical SiO2 morphology, where the ball height refers to the height of the hemispherical SiO2, which is generally 1.5 to 1.8um, and similarly, the ball width is the width of the arc-shaped hemispherical diameter, and the height from the ball height to the upper bottom of the pixel point is the height of the lower spacer, and the radius of curvature can be considered as the degree of curvature of the SiO2 hemispherical curve, the larger the radius of curvature, the larger the circle it represents, and the flatter the curve, the smaller the radius of curvature, the smaller the circle it represents, the more curved the curve, and the greater the curvature.

[0085] However, through data simulation and multiple experimental verifications, the inventors found that the smaller the radius of curvature, that is, the larger the spherical width of the microlens 140, the better for light emission. Correspondingly, the larger the spherical height, that is, the change of the original hemispherical spherical height of the microlens 140, the escaped light can also be emitted from the microlens 140. By changing the curvature, the total emission angle of the microlens 140 is increased, making it difficult to form total reflection light, which is beneficial to the light emission effect. In addition, in order to achieve a uniform photolithography pattern, the photoresist is generally not too thick, because the photoresist is also consumed as a mask layer during the etching process, and too much or too little etching cannot obtain a more ideal spherical height of the microlens 140. When the spherical width and spherical height can form a positive semicircular shape, that is, twice the spherical height is equal to the spherical width, the effect is best.

[0086] The inventor further studied and found that the remaining amount of the lower spacer also affects the light output effect. For the same ball height and ball width, the lower spacer generally does not exceed the ball height. Under the current process, there are micro-gap defects on both sides of the SiO2 of the lower spacer, and light sources are prone to diffuse reflection here. If the lithography size of the microlens 140 is adjusted, this defect can be eliminated or reduced during the etching of the previous microlens 140, and the defect repair effect can be achieved through subsequent secondary SiO2 deposition.

[0087] In the existing process steps, it is inevitable that the ball width and ball height of the microlens 140 are not in the best conditions after etching. For example, the SiO2 film layer of the microlens 140 is deposited for the first time by PECVD, about 2.5 - 3.5 microns. Subsequently, the lithography morphology of the microlens 140 is adjusted, such as the photoresist thickness, exposure energy, and hardening film temperature, to complete the lithography array morphology at the corresponding pixel positions. The passivation protective layer SIO2 material of the microlens 140 is etched by ions to form a hemispherical SIO2 microlens 140 with a lens-like morphology. After the etching of the microlens 140 SIO2 is completed, due to the lithography size and ion etching of the microlens 140, the overall curvature radius, the height of the lower spacer, as well as the ball height and lens ball width of the microlens 140 are all slightly smaller. Therefore, secondary SIO2 deposition is performed on the microlens 140 to increase the curvature radius, the height of the lower spacer, as well as the ball height and lens ball width of the microlens 140. The film thickness of the secondary SIO2 deposition needs to be based on the SIO2 film thickness deposited on the previous microlens 140 and the etching morphology of the microlens 140. The secondary deposition is generally 0.2 - 1 micron, and it can be a single or multiple deposition operations. The inventor of the present invention found through research that better brightness improvement effects can be obtained through secondary deposition.

[0088] Based on this, the present invention provides a micro light-emitting diode chip and a manufacturing method thereof. The microlens 140 is formed by multiple deposition methods to change the height of the lower spacer, the curvature radius, and the ball height of the microlens 140, improve the micro-defects of the lens, and effectively improve the light efficiency of the micro light-emitting diode chip.

[0089] In an embodiment of the present invention, the first bottom contact hole 111 is electrically connected to the first-type semiconductor layer 121 of the micro mesa 120 through the bottom metal layer 130 and the bottom conductive layer 150, and the second bottom contact structure 112 is electrically connected to the second-type semiconductor layer 122 of the micro mesa 120 through the top conductive layer 170. The first bottom contact hole 111 and the second bottom contact structure 112, as the positive and negative electrodes of the micro light-emitting diode, are both disposed in the bottom dielectric layer 113 below the micro mesa. The bottom dielectric layer 113 is located on the top surface of the driving backplane 110. The first bottom contact hole 111 is electrically connected to the driving circuit in the driving backplane 110, and the second bottom contact structure 112 is led out at the edge of the micro mesa array and electrically connected to an external pad. Burying the second bottom contact structure 112 as the top electrode of the micro light-emitting diode into the bottom dielectric layer 113 of the driving backplane 110 can prevent the second bottom contact structure 112 from blocking the micro mesa, thereby increasing the light extraction rate. In addition, the structure proposed by the present invention avoids arranging the top electrode on the side surface of the micro mesa, and the beam collimation effect of the micro lens is better.

[0090] In some embodiments, the top of the second-type semiconductor layer 122 further includes a metal island layer 180. The metal island layer 180 contains multiple mutually isolated metal particles.

[0091] In some embodiments, the second bottom contact structure 112 is buried as the top electrode of the micro light-emitting diode into the bottom dielectric layer 113 of the driving backplane 110. In order to avoid short-circuiting between the positive and negative electrodes of the micro light-emitting diode caused by the second bottom contact structure 112 contacting the bottom metal layer 130, the top of the second bottom contact structure 112 can be designed to be lower than the bottom of the bottom metal layer 130. Figure 4 The longitudinal cross-sectional schematic diagram of a micro light-emitting diode chip according to an embodiment of the present invention is shown. As Figure 4 shown, the top of the second bottom contact structure 112 is lower than the top of the trench where it is located. Thus, the second bottom contact structure 112 is spaced apart from the bottom metal layer 130 in the vertical direction.

[0092] In some embodiments, the second bottom contact structure 112 can be further separated from the bottom metal layer 130 in the horizontal direction. For example, the top of the trench where the second bottom contact structure 112 is located can be widened, so that the distance between the side walls of the trench above the second bottom contact structure 112 is greater than the distance between the side wall of the trench in contact with the second bottom contact structure 112.

[0093] In some embodiments, there is an upper connection portion (not shown) between the top conductive layer 170 and the top surface of the second-type semiconductor layer 122, and the upper connection portion is electrically connected to the top conductive layer 170 and the second-type semiconductor layer 122. The material of the upper connection portion can be a metal, and the metal can include one or more of the following: aluminum (Al), gold (Au), rhodium (Rh), silver (Ag), chromium (Cr), titanium (Ti), platinum (Pt), tin (Sn), copper (Cu), gold-tin alloy (AuSn), titanium-tungsten alloy (TiW), etc. Alternatively, the material of the upper connection portion can be a conductive transparent electrode, such as indium tin oxide (ITO) or fluorine-doped tin oxide (FTO).

[0094] In some embodiments, the micro mesa 120 may further include a lower connection portion (not shown) between the bottom conductive layer 150 and the bottom surface of the first-type semiconductor layer 121, and the lower connection portion is electrically connected to the bottom conductive layer 150 and the first-type semiconductor layer 121. The material of the lower connection portion is a metal, including one or more of aluminum (Al), gold (Au), rhodium (Rh), silver (Ag), chromium (Cr), titanium (Ti), platinum (Pt), tin (Sn), copper (Cu), gold-tin alloy (AuSn), titanium-tungsten alloy (TiW), etc.

[0095] Figure 5 The longitudinal cross-sectional schematic diagram of a micro light-emitting diode chip according to an embodiment of the present invention is shown. Figure 5 The shown micro light-emitting diode chip is different from Figure 2 the shown micro light-emitting diode chip in that: Figure 5 the shown micro light-emitting diode is bonded to the driving backplane 110 by hybrid bonding technology. As Figure 5As shown, in some embodiments, the bottom dielectric layer 113 is located at the bottom of the micro mesa, and the micro mesa is hybrid bonded to the driving backplane 110 through the bottom dielectric layer 113 and the first bottom contact hole 111. For the driving plate 110 and the light-emitting diode structure on both sides of the bonding interface, the surface of the bottom dielectric layer 113 is flush with the surface of the first bottom contact hole 111. During bonding, the driving plate 110 and the light-emitting diode structure are aligned, the bottom dielectric layer portion of the driving backplane 110 is bonded to the bottom dielectric layer portion of the light-emitting diode structure, and the first bottom contact hole portion of the driving backplane 110 is bonded to the first bottom contact hole of the light-emitting diode structure, thereby achieving hybrid bonding. In some embodiments, the composition of the first bottom contact hole 111 may include gold-gold bonding, gold-tin bonding, gold-indium bonding, titanium-titanium bonding, copper-copper bonding, or a combination thereof. For example, if gold-gold bonding is selected, then two layers of gold respectively require a chromium coating as an adhesion layer and a platinum coating as an anti-diffusion layer. And the platinum coating is located between the gold layer and the chromium layer. The chromium layer and the platinum layer are respectively located on the top and bottom of the two bonded gold layers. In some embodiments, when the thicknesses of the two layers of gold are approximately the same, under high pressure and high temperature conditions, the mutual diffusion between the two layers of gold will bond these two layers together. Eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding are all example techniques that can be used. The composition material of the bottom dielectric layer 113 can be silicon dioxide (SiO2).

[0096] As Figure 5 shown, the second bottom contact structure 112 is located in the bottom dielectric layer 113 between adjacent micro mesas and does not contact the first type semiconductor layer 121.

[0097] In some embodiments, as Figure 5 shown, the micro light-emitting diode structure further includes a reflective layer 190. The reflective layer 190 is respectively located between the bottom conductive layer 150 and the first bottom contact hole 111, and between the second bottom contact structure 112 and the top conductive layer 170. The top area of the reflective layer 190 can be substantially the same as that of the first bottom contact hole 111 and the second bottom contact structure 112. The reflective layer 190 can be a metal layer with a high reflectivity, which contains one or more metals such as platinum (Pt), rhodium (Rh), aluminum (Al), gold (Au), and silver (Ag); it can also be a stacked distributed Bragg reflector (DBR) layer containing a titanium dioxide (TiO2) / silicon dioxide (SiO2) layer; or any other layer with total reflection characteristics, including a multi-layer omnidirectional reflector (ODR); or a combination of the above several cases. The reflective layer 190 can reflect the light emitted from the light-emitting region, thereby improving the brightness and light-emitting efficiency of the micro light-emitting diode panel or display screen. For example, the light emitted from the light-emitting region may reach the reflective layer and be reflected upward by these reflective layers.

[0098] AsFigure 5 As shown, there is a step 126 at the sidewall of the micro mesa. Specifically, the step 126 includes a flat portion located on the sidewall of the second-type epitaxial layer 122. At this flat portion, the lateral dimension of the second-type epitaxial layer 122 decreases by a specific distance from the edge to the center, thereby forming a flat portion on the sidewall of the second-type epitaxial layer 122. By forming the step 126, the top area of the second-type epitaxial layer 122 decreases, and the electron and hole recombination region at the light-emitting layer 123 converges towards the center of the light-emitting mesa. The test results show that the light intensity of the micro light-emitting diode with sidewall steps is significantly improved within a small light-emitting angle range.

[0099] In some embodiments, the micro light-emitting diode chip may include red, blue, and / or green micro light-emitting diodes. In some embodiments, the pitch of the micro light-emitting diode array, i.e., the minimum center-to-center distance between micro light-emitting diodes, may be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the micro light-emitting diode chip may be between several thousand and several million.

[0100] Although the embodiments of the present invention have been described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, deformations, and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the width and scope of the present invention disclosed herein should not be limited by the above-disclosed exemplary embodiments, but should be defined only by the appended claims and their equivalents.

Claims

1. A micro light-emitting diode chip, comprising a micro mesa array including a plurality of micro mesas; characterized in that, Each micro mesa includes: A first type semiconductor layer, a light emitting layer, and a second type semiconductor layer stacked in sequence from bottom to top; the first type and the second type are different; A bottom metal layer located at the bottom of the micro mesa; A bottom dielectric layer located at the bottom of the bottom metal layer; the bottom dielectric layer has grooves; A first bottom contact hole located in the bottom dielectric layer and at the bottom of the bottom metal layer, and the first bottom contact hole is in contact with the bottom metal layer; A sidewall dielectric layer located on the sidewalls of the micro mesa and the sidewalls of the bottom metal layer; A top conductive layer continuously covering the top surface of the micro mesa, the surface of the sidewall cutoff layer, and the area between adjacent micro mesas; A second bottom contact structure located in the grooves and in the bottom dielectric layer between adjacent micro mesas and not in contact with the bottom metal layer.

2. The micro light-emitting diode chip according to claim 1, wherein The top of the second bottom contact structure is lower than the bottom of the bottom metal layer; and lower than the top of the grooves.

3. The micro light-emitting diode chip according to claim 1, characterized in that, The lateral width of the second bottom contact structure is smaller than the lateral width of the gap between adjacent bottom metal layers.

4. The micro light-emitting diode chip according to claim 1, characterized in that, The top conductive layer also covers the top surface of the second bottom contact structure.

5. The micro light-emitting diode chip according to claim 1, characterized in that, A plurality of the second bottom contact structures are integrally connected to each other.

6. The micro light-emitting diode chip according to claim 5, wherein The second bottom contact structures are arranged in a transverse and longitudinal cross-interconnected manner around the first bottom contact holes under each micro mesa, and the grooves are also arranged in a transverse and longitudinal cross-interconnected manner in the bottom dielectric layer and around the first bottom contact holes under each micro mesa.

7. The micro light-emitting diode chip according to claim 6, wherein, At the transverse and longitudinal cross-points of the second bottom contact structures, the top conductive layer is in contact with the top surface of the second bottom contact structures.

8. The micro light-emitting diode chip according to claim 5, wherein The first bottom contact holes and the second bottom contact structures are arranged alternately.

9. The micro light-emitting diode chip according to claim 1, wherein The spacing between the sidewalls of the grooves above the second bottom contact structures is greater than the spacing between the sidewalls of the grooves in contact with the second bottom contact structures.

10. The micro light-emitting diode chip according to claim 1, characterized in that, The material of the first bottom contact holes is metal; the material of the second bottom contact structures is metal.

11. The micro light-emitting diode chip according to claim 10, wherein The metal is one or more of copper, gold, tin, platinum, tungsten, chromium, rhodium, titanium, silver, germanium, and nickel.

12. The micro light-emitting diode chip according to claim 1, wherein The sidewall dielectric layer covers the entire sidewalls of the micro mesa structure and the entire sidewalls of the bottom metal layer, and has an opening at the top of the micro mesa structure; the opening exposes part or all of the top of the micro mesa.

13. The micro light-emitting diode chip according to claim 12, wherein The material of the sidewall dielectric layer is one or more of silicon oxide, silicon oxynitride, and silicon nitride.

14. The micro light-emitting diode chip according to claim 1, characterized in that, The bottom of the first type semiconductor layer also has a bottom conductive layer; the bottom metal layer is located at the bottom of the bottom conductive layer; the light emitting layer is multi-layer stacked; the first type semiconductor layer is N-type and the second type semiconductor layer is P-type; or, the first type semiconductor layer is P-type and the second type semiconductor layer is N-type.

15. The micro light emitting diode chip according to claim 14 further includes a reflective layer, the reflective layer is respectively located between the bottom conduction and the first bottom contact holes, and between the second bottom contact structures and the top conductive layer, and the top area of the reflective layer is substantially the same as that of the first bottom contact holes and the second bottom contact structures.

16. The micro light-emitting diode chip according to claim 14, wherein, The bottom metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; The material of the bottom conductive layer is one or a combination of more than one of graphene, indium tin oxide, aluminum-doped zinc oxide, and fluorine-doped tin oxide; The material of the top conductive layer is one or a combination of more than one of graphene, indium tin oxide, aluminum-doped zinc oxide, and fluorine-doped tin oxide.

17. The micro light-emitting diode chip according to claim 1, wherein The top of the second-type semiconductor layer further includes a metal island layer; the metal island layer contains multiple mutually isolated metal particles.

18. The micro light-emitting diode chip according to claim 1 further includes a driving backplane, the driving backplane includes a driving circuit, and the driving circuit is electrically connected to each first bottom contact hole in the micro mesa array.

19. The micro light-emitting diode chip according to claim 1, wherein The side wall of the micro mesa has a step, and the step 126 includes a flat portion on the side wall of the second-type semiconductor layer.

20. The micro light-emitting diode chip according to claim 1, wherein, The side wall of the micro mesa is inclined, and the inclination angle range is: 60° to 85°.

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