Tin-tellurium alloy-based novel phase change storage material and storage and calculation integrated array

Abstract

The invention discloses a novel phase change storage material based on tin-tellurium alloy and a storage and calculation integrated array, the chemical formula of the tin-tellurium alloy is SnxTe100-x, x is more than or equal to 30 and less than or equal to 70, Sn atoms and Te atoms in an amorphous phase structure of the tin-tellurium alloy mainly form an octahedron or defect octahedron local structure, no obvious Piers distortion exists, and no obvious resistance drift phenomenon is caused; each storage unit of the tin-tellurium alloy-based phase change storage and calculation integrated array at least comprises a bottom electrode, a dielectric layer, a functional layer and a top electrode, the thickness of the functional layer is smaller than or equal to 7nm, the top electrode and the bottom electrode of each storage unit are arranged in a crossed mode, programming can be carried out by loading electrical pulses with different amplitudes and pulse widths, and programming is carried out by loading the electrical pulses with different amplitudes and pulse widths. Multi-logic-state long-time stable recognition of a single node is achieved, and the array scale can be expanded in the plane direction and the vertical direction.

Description

Technical Field

[0001] The present invention relates to the technical field of phase change memory, and particularly to a novel phase change storage material based on tin telluride alloy and a memory-computation integrated array. Background Art

[0002] Phase change memory technology utilizes the rapid reversible phase change between the amorphous phase and the crystalline phase of phase change materials and the huge resistance difference to achieve the switching of logical states "0" (RESET state) and "1" (SET state) for data storage. The resistance window of the commercial phase change material germanium antimony telluride can reach more than 1000 times. By means of gradual phase change, multiple logical state identifications can be realized in a single storage cell, namely the phase change "multi-value storage" technology. Based on this, a cross-structured storage cell array can be constructed, and the matrix-vector multiplication can be directly solved through electrical measurement, namely the "memory-computation integration" technology. This technology can greatly improve computing power. The more logical values that can be recognized by a single storage cell, the higher the operation efficiency of the array.

[0003] However, the amorphous phase of germanium antimony telluride will undergo spontaneous structural relaxation at room temperature, resulting in a continuous increase in the resistance value of the storage cell over time, that is, the resistance drift phenomenon. The root cause is that the local octahedral structure in the amorphous has Peierls distortion, and the distortion gradually increases over time. In addition, the germanium tetrahedral defects gradually decrease over time, leading to an increase in the band gap. This phenomenon greatly limits the number of logical states that can be recognized in a single storage cell and seriously affects the accurate identification of encoded data, resulting in a high error rate, which is one of the main bottlenecks for improving the computing power of phase change memory-computation integrated chips.

[0004] Therefore, there is an urgent need to develop a phase change storage material and a memory-computation integrated array with intrinsic low resistance drift characteristics. Summary of the Invention

[0005] In order to overcome the above defects existing in the prior art, the present invention provides a novel phase change storage material based on tin telluride alloy and a memory-computation integrated array. This phase change storage material has ultra-low resistance drift, overcoming the problem of resistance value drift over time in the existing phase change multi-value storage and memory-computation integration technologies.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] A novel phase change storage material based on tin telluride alloy, with the chemical formula Sn x Te 100-x , where 30 ≤ x ≤ 70;

[0008] The amorphous phase of the phase change memory material is semiconducting with a high corresponding resistance value, and the crystalline phase is metallic with a low corresponding resistance value. The transition between its amorphous phase and crystalline phase is a semiconductor / metal transition, rather than the semiconductor / semiconductor transition of traditional phase change materials. Therefore, the resistance value difference between the amorphous phase and crystalline phase of the tin telluride alloy is large, having a large resistance recognition window.

[0009] In the local structure with Sn or Te as the central atom of the amorphous phase structure of the phase change memory material, more than 80% forms an octahedral or defective octahedral local structure. The bond lengths between atoms in the octahedron are basically equal, and there is no obvious Peierls distortion. Therefore, its structural relaxation will not cause obvious resistance drift, that is, the resistance value will not change significantly over time. In the amorphous phase of traditional germanium antimony telluride alloy, the octahedral local structure has obvious Peierls distortion and gradually increases with time, resulting in resistance drift. Therefore, the tin telluride amorphous phase will not cause obvious resistance drift.

[0010] There are obvious electrical property differences between the amorphous phase and crystalline phase of the phase change memory material, while both the crystal and amorphous phases of traditional germanium antimony telluride alloy are semiconducting.

[0011] The content of tetrahedrons in the amorphous phase is < 7%.

[0012] The novel phase change memory material based on tin telluride alloy has a large resistance recognition window and can program more recognizable logic states at a single node.

[0013] The phase change memory material is applied to a phase change memory and computing integrated array. The storage unit of the array includes a bottom electrode layer, a dielectric layer, a functional layer, and a top electrode arranged in sequence. The functional layer is Sn x Te 100-x phase change memory material, and 0 < thickness ≤ 7 nm; where 30 ≤ x ≤ 70. The amorphous phase of the phase change memory material is semiconducting with a high corresponding resistance value, and the crystalline phase is metallic with a low corresponding resistance value. Therefore, the transition between its amorphous phase and crystalline phase is a semiconductor / metal transition, and the resistance value difference between the two is large, having a large resistance recognition window.

[0014] In the phase change memory and computing integrated array, the top electrode layer and bottom electrode layer of each storage unit are arranged in a cross pattern to form word lines, bit lines, and source lines, and the array scale can be expanded in the plane direction.

[0015] In the phase change memory and computing integrated array, each storage unit can be programmed for logic states by applying a certain current or voltage pulse, and the amplitude range is 0.5 - 10 V, and the pulse width unit is 10 ns - 2000 ns. This process corresponds to the partial crystallization or partial amorphization of the Sn x Te 100-x material, and the larger the pulse amplitude and pulse width, the corresponding Snx Te 100-x The larger the area where the material crystallizes or becomes amorphous, the greater the change in the resistance value of the device unit.

[0016] In the array, the logic state of the device unit is reconstructed through SET or RESET operations, that is, the Sn in the device x Te 100-x The functional region of the thin film crystallizes or becomes completely amorphous, making the resistance value of the device unit reach the minimum or maximum, corresponding to the minimum or maximum logic state of the unit.

[0017] Advantages of the present invention:

[0018] The present invention proposes a novel phase change memory material based on tin telluride alloy. The content of tetrahedrons in its amorphous phase is <7%, much lower than that of the amorphous phase of germanium antimony telluride. Therefore, the influence of tetrahedrons on structural relaxation is extremely small; more than 80% of the atomic local structures in the amorphous phase are octahedrons or defective octahedrons, and more than 85% of the Sn atoms form octahedron or defective octahedron structures, and the bond lengths between the atoms in the octahedron are basically equal, without obvious Peierls distortion. Combining the above two factors, the amorphous structure relaxation of the tin telluride alloy will not cause obvious resistance drift, that is, the resistance value will not change significantly over time. Therefore, it has ultra-low resistance drift.

[0019] The present invention proposes a novel phase change memory material based on tin telluride alloy. Its amorphous phase is semiconducting and its crystalline phase is metallic, while the amorphous and crystalline phases of traditional phase change materials are both semiconducting. Therefore, the tin telluride alloy has a larger resistance recognition window and can program more recognizable logic states at a single node.

[0020] Phase change multi-value storage and memory-computation integrated array have the ability of multi-logic state programming and recognition in a single storage unit. The recognizable logic states include the SET state of all crystals, the RESET state of all amorphous, and multiple logic states of crystal and amorphous mixtures. All logic states except the SET state have amorphous phase structures. The storage units based on traditional phase change materials will all have resistance drift, resulting in a high error rate during data decoding. The phase change multi-value storage and memory-computation integrated array of the present invention uses a tin telluride alloy with an ultra-low resistance drift coefficient, which limits resistance drift at the source. Therefore, the logic states of each device in the array can be maintained stable for a long time, effectively increasing the number of recognizable logic states at a single node and reducing the error rate of data decoding.

[0021] The present invention proposes a memory-computation integrated array based on tin telluride alloy, where the functional layer of the storage unit is Sn x Te 100-xPhase change memory material, where 0 < thickness ≤ 7 nm, and the thickness is much lower than the dozens to hundreds of nanometers of traditional devices. Therefore, it can greatly improve the integration density in the vertical direction and increase the storage capacity of the device array.

[0022] The novel phase change memory material and memory-computation integrated array based on tin telluride alloy proposed by the present invention, its preparation method includes but is not limited to magnetron sputtering method, atomic layer deposition method, ultraviolet exposure, electron beam lithography, dry etching or wet etching, etc., all of which are compatible with the existing mature CMOS semiconductor processing technology, easy to achieve large-scale integration and engineering preparation, and have broad application prospects and important application values in the fields of data-intensive multi-value storage, embedded non-volatile storage, memory-computation integration and neuron-inspired brain computing. Brief Description of the Drawings

[0023] Figure 1 It is the atomic model of the amorphous tin telluride phase change memory material.

[0024] Figure 2 It is the ratio comparison diagram of tetrahedrons and octahedrons in the amorphous tin telluride phase change memory material.

[0025] Figure 3 It is the Peierls distortion analysis diagram of the amorphous tin telluride phase change memory material.

[0026] Figure 4 It is the density of states analysis diagram of the amorphous and crystalline phases of the tin telluride phase change memory material.

[0027] Figure 5 It is the schematic diagram of the storage unit of the tin telluride phase change memory-computation integrated array. Detailed Description of the Embodiments

[0028] The present invention will be further described in detail below with reference to the accompanying drawings.

[0029] Figure 1 It is the atomic model of the amorphous tin telluride phase change memory material. In the figure, the light and dark small balls represent Sn and Te atoms respectively. Among them, Sn atoms and Te atoms mainly form octahedrons or defective octahedron local structures, and both Sn atoms and Te atoms can be the central atoms of octahedrons or defective octahedrons.

[0030] Figure 2It is a comparison diagram of the ratio of tetrahedrons to octahedrons in the amorphous tin telluride phase change memory material. In the figure, the proportions of tetrahedrons and octahedrons in the local structures centered on Sn and Te are analyzed respectively. In the local structure centered on Sn, the proportion of octahedrons is close to 90%, while the proportion of tetrahedrons is less than 6%; in the local structure centered on Te, the proportion of octahedrons is close to 85%, while the proportion of tetrahedrons is less than 7%. The inset shows the schematic atomic models of the octahedral local structures centered on Sn and Te. In the amorphous phase of the traditional phase change memory material germanium antimony telluride, ~33% of germanium atoms are in the tetrahedral structure, and the defect states gradually decrease with time, resulting in an increase in the band gap and a gradual increase in the resistance value.

[0031] Figure 3 It is an analysis diagram of the Peierls distortion of the amorphous tin telluride phase change memory material. The Peierls distortion refers to the state of the distribution of long and short bonds in a locally collinear structure where the bond angle of three-atom bonding is greater than 155°. The ratio of the bond lengths of long bonds to short bonds describes the degree of Peierls distortion, and the larger the value, the stronger the Peierls distortion, which can be intuitively represented by the Angular limited three body correlation function (ALTBC). In the Sn-Te system, the bond lengths are uniformly distributed near the diagonal, and there are no obvious separate peaks for long and short bonds, so the degree of Peierls distortion is low, which is consistent with the behavior of similar bond lengths in the rock salt phase crystal structure of the tin telluride alloy. The analysis of the bond lengths of the amorphous phase structure of the traditional phase change material germanium antimony telluride shows that its bond lengths exhibit obvious separate peaks, with obvious long and short bonds, so it has obvious Peierls distortion, and the distortion gradually increases with time, resulting in a spontaneous increase in the resistance value.

[0032] Figure 4 It is a density of states analysis diagram of the amorphous and crystal phases of the tin telluride phase change memory material. There are differences in the electronic structures of the amorphous and crystal phases of the tin telluride alloy. The amorphous phase has a band gap of ~0.45 eV near the Fermi level and is a narrow-bandgap semiconductor, while the crystal phase shows a peak near the Fermi level and exhibits metallicity. Therefore, there are electrical property differences between the two phases, and different logic states can be identified based on this. Both the crystal and amorphous forms of the traditional phase change material germanium antimony telluride exhibit semiconductivity.

[0033] Figure 5 It is a schematic diagram of the storage unit of the tin telluride phase change memory and computing integrated array. In the figure, 1 - bottom electrode layer; 2 - functional layer; 3 - dielectric layer; 4 - top electrode layer. The crystallization temperature of the tin telluride alloy is relatively low, and the thermal stability of the amorphous phase can be improved through the nano-size effect. Therefore, the thickness of the functional layer in the storage unit should not exceed 20 nm.

[0034] The following takes specific embodiments as examples to further illustrate the present invention.

[0035] Example 1

[0036] This example is a low-resistance drift phase change memory material based on a tin telluride alloy, with the chemical formula Sn 50 Te 50 , in its amorphous phase structure, Sn atoms and Te atoms mainly form octahedral or defective octahedral local structures, only containing a very small amount of tetrahedral structures; the bond lengths between atoms in the octahedron are basically equal, and there is no obvious Peierls distortion. Therefore, Sn 50 Te 50 's amorphous phase has ultra-low resistance drift. The amorphous phase of Sn 50 Te 50 is semiconducting, and the crystalline phase is metallic. There are obvious differences in electrical properties between the two phases, and different logic states can be identified based on this.

[0037] A low-resistance drift phase change memory and computing integrated array based on a tin telluride alloy. The storage units of the array at least include a bottom electrode, a dielectric layer, a functional layer, and a top electrode. Its functional layer is Sn 50 Te 50 phase change memory material, with a thickness of 5 nm. The top electrodes and bottom electrodes of each storage unit in this memory and computing integrated array are arranged in a cross pattern to form word lines, bit lines, and source lines, and the array scale can be expanded in the plane direction. Each storage unit in the array can be logically programmed by applying a current or voltage pulse with a certain amplitude and pulse width, corresponding to partial crystallization or partial amorphization of the Sn 50 Te 50 thin film. Logic state reconstruction can be performed through SET or RESET operations, corresponding to complete crystallization or complete amorphization of the Sn 50 Te 50 thin film. The resistance values corresponding to different logic states of each device in the array do not show obvious resistance drift phenomena, and long-term stable identification can be achieved.

[0038] Example 2

[0039] This example is a low-resistance drift phase change memory material based on a tin telluride alloy, with the chemical formula Sn 45 Te 55 , in its amorphous phase structure, Sn atoms and Te atoms mainly form octahedral or defective octahedral local structures, only containing a very small amount of tetrahedral structures; the bond lengths between atoms in the octahedron are basically equal, and there is no obvious Peierls distortion. Therefore, Sn 45 Te 55 's amorphous phase has ultra-low resistance drift. The amorphous phase of Sn 45 Te 55The amorphous phase is semiconducting, and the crystalline phase is metallic. There are obvious differences in electrical properties between the two phases, and different logic states can be identified based on this.

[0040] A low-resistance drift phase-change memory and computing integrated array based on a tin telluride alloy. The storage unit of the array includes at least a bottom electrode, a dielectric layer, a functional layer, and a top electrode. The functional layer is Sn 45 Te 55 phase-change memory material with a thickness of 10 nm. The top electrodes and bottom electrodes of each storage unit in the memory and computing integrated array are arranged in a cross manner to form word lines, bit lines, and source lines, and the array scale can be expanded in the planar direction. Each storage unit in the array can be logically programmed by applying a current or voltage pulse with a certain amplitude and pulse width, corresponding to partial crystallization or partial amorphousization of the Sn 45 Te 55 thin film. Logic state reconstruction can be performed through SET or RESET operations, corresponding to complete crystallization or complete amorphousization of the Sn 45 Te 55 thin film. The resistance values corresponding to different logic states of each device in the array do not exhibit obvious resistance drift phenomena, enabling long-term stable identification.

Claims

1. A novel phase change memory material based on tin telluride alloy, characterized in that, Its chemical formula is Sn x Te 100-x , where 30 ≤ x ≤ 70; The amorphous phase of the phase change memory material is semiconducting with a high resistance value, and the crystalline phase is metallic with a low resistance value. The transition between the amorphous phase and the crystalline phase is a semiconductor / metal transition.

2. A novel phase change memory material based on a tin telluride alloy according to claim 1, characterized in that, In the local structure with Sn or Te as the central atom, more than 80% of the amorphous phase of the phase change memory material forms an octahedral or defective octahedral local structure. The bond lengths between atoms in the octahedron are basically equal, and there is no obvious Peierls distortion. The structural relaxation will not cause obvious resistance drift, that is, the resistance value will not change significantly over time.

3. A novel phase change memory material based on a tin telluride alloy according to claim 1, characterized in that, The tetrahedron content in the amorphous phase is <7%.

4. A novel phase change memory material based on a tin telluride alloy according to claim 1, characterized in that, The novel phase change memory material based on the tin telluride alloy has a large resistance identification window and can program more recognizable logic states at a single node.

5. A novel phase change memory material based on tin telluride alloy is applied to a phase change memory and computing integrated array, characterized in that, The storage cells of the array include a bottom electrode layer (1), a dielectric layer (2), a functional layer (3), and a top electrode layer (4) arranged in sequence. The functional layer (3) is Sn x Te 100-x a phase change memory material with 0 < thickness ≤ 7 nm, where 30 ≤ x ≤ 70; the amorphous phase of the phase change memory material is semiconducting with a high corresponding resistance value, and the crystalline phase is metallic with a low corresponding resistance value.

6. The phase change memory and computing integrated array according to claim 5, wherein The top electrode layers (4) and the bottom electrode layers (1) of each memory cell are arranged in a cross manner to form word lines, bit lines and source lines, and the array scale can be expanded in the plane direction.

7. The phase change memory and computing integrated array according to claim 5, wherein Each storage cell is programmed in a logical state by applying a certain current or voltage pulse, with an amplitude range of 0.5 - 10 V and a pulse width in the unit of 10 ns - 2000 ns, corresponding to Sn x Te 100-x partial crystallization or partial amorphization of the material, and the larger the pulse amplitude and pulse width, the larger the area of crystallization or amorphization of the corresponding Sn x Te 100-x material, and the greater the change in the resistance value of the device unit.

8. The phase change memory and computing integrated array according to claim 5, wherein The device units in the array perform logic state reconstruction through SET or RESET operations, that is, operating on Sn in the device x Te 100-x Crystallization or complete amorphousization occurs in the functional region of the thin film, making the resistance value of the device unit reach the minimum or maximum, corresponding to the minimum or maximum logic state of the unit.

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