Data transmission system and method

Abstract

The invention discloses a data transmission system and method, and relates to the technical field of prototype verification of an integrated circuit, and the method comprises the steps: adding a monitoring module in a first logic programming device, adding a time delay processing module in a second logic programming device, and enabling the monitoring module to monitor that the first logic programming device is in the time delay processing module and the second logic programming device is in the time delay processing module; the interrupt signal is later than the data for a time length. Moreover, the data is delayed to arrive compared with the interrupt signal after being transmitted by the cross-logic programming device, so that the delay processing module can be used for monitoring the earlier time length of the interrupt signal compared with the data. According to the method, the first interrupt signal is generated through the operation duration indication information and the delay duration indication information, the interrupt signal used for indicating completion of the write operation and the original time sequence of the data can be restored, and the first interrupt signal can accurately indicate that the write operation of the storage module is completed.

Description

Technical Field

[0001] This application relates to the field of prototype verification technology for integrated circuits, and particularly to data transmission systems and methods. Background Art

[0002] In the field of prototype verification technology for integrated circuits, generally, logic programming devices are used for verification. For example, a Field-Programmable Gate Array (FPGA) can be used to transplant the Register-Transfer Level (RTL) to the FPGA to verify the functions and performance of application-specific integrated circuits. Among them, RTL is an abstract level of a hardware description language used to describe the design of digital circuits. However, the resources of a single logic programming device may be insufficient. Therefore, multiple logic programming devices are required to verify integrated circuits, that is, the component modules of the integrated circuit are distributed on different logic programming devices.

[0003] Since data transmission between different logic programming devices needs to be carried out through Chip2Chip (C2C) transmission, and the interrupt signals between different logic programming devices are generally implemented through general-purpose input / output interfaces, the transmission delay of the interrupt signal is shorter than that of the data. This may cause the target logic programming device (i.e., the data receiving end of the two logic programming devices) to receive the interrupt signal indicating the completion of the write operation earlier than the moment when the target logic programming device completes the write operation, resulting in the interrupt signal being unable to correctly indicate whether the write operation is completed. Summary of the Invention

[0004] This application provides a data transmission system, method, electronic device, storage solution, and program product to solve the problem that the interrupt signal cannot correctly indicate whether the write operation is completed.

[0005] This application provides a data transmission system, which includes a first logic programming device and a second logic programming device. Among them, the first logic programming device includes a monitoring module and a write data module, and the second logic programming device includes a delay processing module, a storage module, and a central processing unit; The write data module is configured to initiate and execute a write operation to the storage module; The monitoring module is configured to obtain the operation duration indication information of the write data module executing the write operation; and send the operation duration indication information to the delay processing module; A delay processing module, configured to generate a first interrupt signal according to the operation duration indication information and the delay duration indication information when receiving the operation duration indication information and obtaining the delay duration indication information corresponding to the transmission write operation, where the first interrupt signal is used to indicate that the write operation has been completed; and send the first interrupt signal to the central processing unit.

[0006] This application also provides a data transmission method, which is applied to a data transmission system. The data transmission system includes a first logic programming device and a second logic programming device. The first logic programming device includes a monitoring module and a write data module, and the second logic programming device includes a delay processing module, a storage module, and a central processing unit. The method includes: The write data module initiates and executes a write operation to the storage module; The monitoring module obtains the operation duration indication information of the write data module executing the write operation; and sends the operation duration indication information to the delay processing module; When receiving the operation duration indication information and obtaining the delay duration indication information corresponding to the transmission write operation, the delay processing module generates a first interrupt signal according to the operation duration indication information and the delay duration indication information, where the first interrupt signal is used to indicate that the write operation has been completed; and sends the first interrupt signal to the central processing unit.

[0007] This application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any of the above data transmission methods when executing the computer program.

[0008] This application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above data transmission methods are implemented.

[0009] This application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of any of the above data transmission methods are implemented.

[0010] Through this application, a monitoring module is added to the first logic programming device, and a delay processing module is added to the second logic programming device. The monitoring module can monitor the duration by which the interrupt signal arrives later than the data in the first logic programming device. And since the data will be delayed compared to the interrupt signal after being transmitted across logic programming devices (and needs to be processed by other modules on the way), the delay processing module can monitor the duration by which the interrupt signal arrives earlier than the data. By generating the first interrupt signal through the operation duration indication information and the delay duration indication information, the original timing sequence of the interrupt signal and the data for indicating the completion of the write operation can be restored, that is, the first interrupt signal can accurately indicate that the storage module has completed the write operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0012] Figure 1 Schematic diagram of the architecture of a data transmission system provided by an embodiment of the present application; Figure 2 Schematic diagram of the architecture of another data transmission system provided by an embodiment of the present application; Figure 3 Schematic diagram of the architecture of yet another data transmission system provided by an embodiment of the present application; Figure 4 Schematic diagram of the architecture of yet another data transmission system provided by an embodiment of the present application; Figure 5 Schematic diagram of processing an interrupt signal through a shift register provided by an embodiment of the present application; Figure 6 Schematic diagram of the architecture of yet another data transmission system provided by an embodiment of the present application; Figure 7 Schematic diagram of the architecture of yet another data transmission system provided by an embodiment of the present application; Figure 8 Schematic diagram of the architecture of yet another data transmission system provided by an embodiment of the present application; Figure 9 Schematic diagram of the architecture of yet another data transmission system provided by an embodiment of the present application; Figure 10 Schematic diagram of the flow of a data transmission method provided by an embodiment of the present application; Figure 11 Schematic diagram of the structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0014] It should be noted that in the description of this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0015] To enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific embodiments.

[0016] This application provides a data transmission system, as Figure 1 shown. The data transmission system includes a first logic programming device 10 and a second logic programming device 20.

[0017] Among them, the first logic programming device may include a write data module 101 and a monitoring module 102, and the second logic programming device 20 includes a delay processing module 201, a central processing unit (CPU) 202, and a storage module 203. The monitoring module 102 can be connected to the write data module 101 and the delay processing module 201. The write data module 101 can be connected to the storage module 203. The delay processing module 201 can be respectively connected to the central processing unit 202 and the write data module 101. The central processing unit 202 can be connected to the storage module 203. Both the first logic programming device 10 and the second logic programming device 20 can be field-programmable gate arrays (FPGAs). The storage module 203 can be a storage device and a storage controller. For example, the storage controller can be a double data rate controller (DDR). The write data module 101 can be a universal serial bus (USB). The connections between the various modules included in the second logic programming device 20 can be implemented through a bus. The bus can be an advanced extensible interface interconnect (AXI) bus, and the architecture of the central processing unit 202 can be an advanced reduced instruction set computer (ARM) architecture.

[0018] The write data module 101 can be used to initiate and execute a write operation to the storage module 203. The monitoring module 102 can be used to obtain the operation duration indication information of the write data module 101 when executing the write operation, and send the operation duration indication information to the delay processing module 201. When receiving the operation duration indication information and obtaining the delay duration indication information corresponding to the transmission of the write operation, a first interrupt signal (Interrupt Request, IRQ) is generated according to the operation duration indication information and the delay duration indication information, where the first interrupt signal is used to indicate that the write operation has been completed, and the first interrupt signal is sent to the central processing unit 202.

[0019] Among them, the interrupt signal can have two states. One is the high-level state, which is used to indicate the occurrence of a special event (for example, the completion of the write operation). The other is the low-level state, which is used to indicate that no processing is required. The first interrupt signal can be used to indicate that the write operation has been completed, that is, the interrupt signal in the high-level state. The operation duration indication information can be used to indicate the interval duration between the start of the write operation by the write data module 101 and the issuance of the interrupt signal. The delay duration indication information can be used to indicate the interval duration between the detection of the interrupt signal by the delay processing module 201 and the arrival of the first data corresponding to the write operation at the storage module 203.

[0020] Specifically, when the write data module 101 completes the configuration operation, the write data module 101 can initiate and execute a write operation to the storage module 203. The monitoring module 102 can monitor the write data module 101 and obtain the operation duration indication information of its execution of the write operation. To avoid the problem of asynchronous data transmission between the interrupt signal and the write operation, the monitoring module 102 can send the operation duration indication information to the delay processing module 201 of the second logic programming device 20, so that the delay processing module 201 can understand the synchronization information between the interrupt signal and the first data.

[0021] In addition, considering the delay in the transmission process of the write data signal, the delay processing module 201 can also obtain the delay duration indication information of the write operation. Furthermore, when the delay processing module 201 obtains the delay duration indication information and receives the operation duration indication information transmitted by the monitoring module 102, a first interrupt signal is generated according to the delay duration indication information and the operation duration indication information, and sent to the central processing unit 202. In this way, the central processing unit 202 can receive the first interrupt signal only after the first data has completed the write operation.

[0022] In the data transmission system according to the embodiments of the present application, a monitoring module 102 is added to the first logic programming device 10, and a delay processing module 201 is added to the second logic programming device 20. The monitoring module 102 can monitor the duration by which the interrupt signal arrives later than the data in the first logic programming device 10. Moreover, since the data will arrive later than the interrupt signal after being transmitted across programming devices (and needs to be processed by other modules on the way), the delay processing module 201 can monitor the duration by which the interrupt signal arrives earlier than the data. By operating on the operation duration indication information and the delay duration indication information, a first interrupt signal is generated, which can restore the original timing and interval duration of the interrupt signal indicating the completion of the write operation and the data in the first logic programming device 10 (i.e., the timing on the side of the first logic programming device), that is, the first interrupt signal can accurately indicate that the storage module 203 has completed the data write operation.

[0023] First, in the above process, the step of the monitoring module 102 obtaining the operation duration indication information may include the following two methods: Method 1, as Figure 2 shown, the monitoring module 102 may include a first timer 102a (Counter, CNT). Correspondingly, when the monitoring module 102 detects that the write data module 101 issues a write data enable signal, it starts the first timer 102a for timing operation. When it detects that the write data module 101 issues a second interrupt signal, it stops the first timer 102a from timing operation. The first timing information is extracted from the first timer 102a as the operation duration indication information.

[0024] Among them, the second interrupt signal is the interrupt signal issued by the write data module 101 when it ends the write operation, and the level state of the second interrupt signal is a high level state. The first timing information may be the timing duration or the number of clock cycles.

[0025] Specifically, when the monitoring module 102 detects that the write data module 101 transmits a write data enable signal, it indicates that the write data module 101 initiates a write operation to the storage module 203 and starts transmitting data. At this time, the monitoring module 102 can start the first timer 102a for timing operation. After the write data module 101 has sent out all the data, it issues a write data invalid signal and a second interrupt signal. In this way, the monitoring module 102 can monitor the second interrupt signal transmitted by the write data module 101. At this time, the monitoring module 102 ends the timing operation of the first timer 102a and extracts the first timing information from the first timer 102a as the operation duration indication information. By the timer performing the timing operation, it is more accurate and more suitable for solutions with higher requirements for signal timing.

[0026] Method 2: The monitoring module 102 records the first moment when it detects that the write data module 101 issues a write data enable signal. Also, it records the second moment when it detects that the write data module 101 issues a second interrupt signal. Based on the first moment and the second moment, the operation duration indication information is determined.

[0027] Specifically, when the monitoring module 102 detects that the write data module 101 issues a write data enable signal, it can record the first moment when the write data enable signal is issued. Also, when it detects that the write data module 101 issues a second interrupt signal, it can record the second moment when the second interrupt signal is issued. Finally, based on the first moment and the second moment, the operation duration indication information can be determined. For example, the difference obtained by subtracting the first moment from the second moment can be determined as the first delay duration. The first delay duration is used as the operation duration indication information. By recording the moments, hardware resources can be saved.

[0028] Second, in the above process, the step in which the delay processing module 201 obtains the delay duration indication information can include the following two methods: Method 1, as Figure 3 shown, the delay processing module 201 can include a second timer 201a. Correspondingly, when receiving the second interrupt signal sent by the write data module 101, the second timer 201a is started for timing. When it is detected that the first data corresponding to the write operation arrives at the storage module 203, the second timer 201a is turned off to stop timing. The second timing information is extracted from the second timer 201a as the delay duration indication information.

[0029] Among them, the second timing information can be the timing duration or the number of clock cycles.

[0030] Specifically, when the delay processing module 201 receives the second interrupt signal transmitted by the write data module 101, it can start the second timer 201a to start the timing operation. When it is detected that the first data corresponding to the write operation arrives at the storage module 203, the second timer 201a can be turned off to stop the timing operation. Furthermore, the second timing information is extracted from the second timer 201a as the delay duration indication information. By using the timer to perform the timing operation, it is more accurate and more suitable for solutions with higher requirements for signal timing.

[0031] Method 2: The delay processing module 201 records the third moment when it detects that it has received the second interrupt signal. Also, it records the fourth moment when the first data corresponding to the write operation arrives at the storage module 203. Based on the third moment and the fourth moment, the delay duration indication information is determined.

[0032] Specifically, when the delay processing module 201 receives the second interrupt signal, it can record the third moment when the second interrupt signal is received. When it detects that the first data corresponding to the write operation arrives at the storage module 203, it can record the fourth moment when the first data corresponding to the write operation arrives at the storage module 203. Finally, it can determine the operation duration indication information according to the fourth moment and the third moment. For example, the difference obtained by subtracting the third moment from the fourth moment can be determined as the second delay duration. The second delay duration is used as the delay duration indication information. By recording the moments, hardware resources can be saved.

[0033] Thirdly, in the above process, generating the first interrupt signal according to the operation duration indication information and the delay duration indication information may specifically include: Step 1, determine the total delay indication information according to the operation duration indication information and the delay duration indication information.

[0034] Step 2, obtain the target interrupt indication information corresponding to the total delay indication information according to the total delay indication information.

[0035] Step 3, generate an interrupt signal corresponding to the target interrupt indication information based on the target interrupt indication information.

[0036] Among them, the interrupt signal corresponding to the target interrupt indication information is the first interrupt signal.

[0037] Specifically, when both the operation duration indication information and the delay duration indication information are the number of clock cycles, the delay processing module 201 can determine the sum value of the operation duration indication information and the delay duration indication information as the target bit identification information, and the target bit identification information is the total delay indication information. Or, when both the operation duration indication information and the delay duration indication information are timing durations, the sum value of the operation duration indication information and the delay duration indication information can be calculated first, and then the ratio of the sum value to the length of the clock cycle can be determined as the target bit identification information. Further, the delay processing module 201 can determine the storage location corresponding to the target bit identification information among multiple preset storage locations according to the target bit identification information, extract the target interrupt indication information therefrom, and then generate a corresponding interrupt signal based on this target interrupt indication information.

[0038] In some alternative embodiments, the above-mentioned delay processing module 201 can also be used to perform delay operations on the interrupt signals of each clock cycle transmitted by the write data module 101.

[0039] Among them, the delay processing module 201 can include multiple storage units (which can be the above-mentioned storage locations), and the multiple storage units can be arranged in a preset order. The storage unit can be a flip-flop in the shift register 201b. For example, the shift register 201b can be a 64-bit register. Correspondingly, the data transmission system can be asFigure 4 as shown

[0040] Specifically, the steps for the delay processing module 201 to perform a delay operation may specifically include: Step 1, in the current clock cycle, identify the first state information of the interrupt signal received in the current clock cycle.

[0041] Among them, the clock cycle may be the clock cycle of the data bus domain.

[0042] Step 2, according to the sorting of each storage unit, perform a shift operation on the state information stored in each storage unit in sequence.

[0043] Step 3, when the shift operation of each storage unit is completed, store the first state information in the initial storage unit.

[0044] Among them, the initial storage unit is the storage unit ranked first among the multiple storage units.

[0045] Specifically, since the interrupt signal transmitted from the write data module 101 to the delay processing module 201 is continuous, in order to be able to send the interrupt signal indicating that the write operation has been completed to the central processing unit 202 after the storage module 203 completes the write operation, the delay processing module 201 can also be used to perform a delay operation on the interrupt signal of each clock cycle transmitted by the write data module 101.

[0046] Taking the flip-flop in the shift register 201b as the storage unit as an example, in each clock cycle, the delay processing module 201 can identify and store the state information of the interrupt signal received in that clock cycle. Since the number of storage units included in the shift register 201b is limited, for the state information stored in the storage unit ranked last, it can be shifted out. For the storage unit whose ranking is not the last (taking the first storage unit as an example), the state information stored in the first storage unit can be shifted to the second storage unit ranked after the first storage unit, and the state information stored in the third storage unit ranked before the first storage unit can be shifted to the first storage unit, and so on, to complete the shift operation of the state information stored in each storage unit. In this way, the initial storage unit ranked first can be vacated, and the first state information of the current clock cycle can be written into the first storage unit.

[0047] Under such a mechanism, when the delay processing module 201 detects the status information of the second interrupt signal sent by the write data module 101 upon completion of the write operation, it can be recorded in a certain storage unit of the shift register 201b. By sequentially transmitting the status information of the interrupt signal between different flip-flops of the shift register, the delay time of the signal can be very precisely controlled according to the number of clock cycles of the required delay. This is particularly important for application scenarios that require precise synchronization in this solution.

[0048] As Figure 5 shown, at time 0, the 0 storage unit stores the status information (IRQ0) of the interrupt signal recognized at time 0. At time 1, the status information of the interrupt signal recognized at time 0 is shifted to the 1 storage unit, and the status information (IRQ1) of the interrupt signal recognized at time 1 is recorded in the 0 storage unit. At time 2, the status information of the interrupt signal recognized at time 0 is shifted to the 2 storage unit, the status information of the interrupt signal recognized at time 1 is shifted to the 1 storage unit, and the status information (IRQ2) of the interrupt signal recognized at time 2 is recorded in the 0 storage unit. At time 3, the status information of the interrupt signal recognized at time 0 is shifted to the 3 storage unit, the status information of the interrupt signal recognized at time 1 is shifted to the 2 storage unit, the status information of the interrupt signal recognized at time 2 is shifted to the 1 storage unit, and the status information (IRQ3) of the interrupt signal recognized at time 3 is shifted to the 0 storage unit.

[0049] Under the above shift mechanism, when the delay processing module 201 determines the target bit identification information, it can, according to the target bit identification information, determine the target storage unit corresponding to the target bit identification information among multiple storage units, and extract the second status information from the target storage unit as the target interrupt indication information.

[0050] For example, when the target bit identification information is 15, the storage unit ranked 15 in the shift register 201b can be determined, and the status information of the first interrupt signal is extracted therefrom. The storage unit ranked 15 is Figure 5 the storage unit with the identification information 14 in

[0051] In the first logic programming device 10, it is recorded that the second interrupt signal arrives 10 beats (the number of clock cycles) later than the write data enable signal. Due to the data transmission delay, in the second logic programming device 20, it is recorded that the second interrupt signal arrives 5 beats earlier than the data. Thus, in order to enable the second interrupt signal to also arrive 10 beats later than the write data enable signal on the second logic programming device 20 and then be transmitted to the central processing unit 202, it is necessary to delay the received second interrupt signal by 10 + 5 = 15 beats (that is, determine that the target bit identification information is 15). Correspondingly, the status information indicating the completion of the write operation can be read from the storage unit ranked 15 (that is, the 14th storage unit) in the shift register 201b, and a corresponding interrupt signal (that is, the first interrupt signal) is generated and then transmitted to the central processing unit 202.

[0052] In the data transmission system according to the embodiments of the present application, the interrupt signal indicating the completion of the write operation in the first logic programming device 10 arrives later than the write data enable signal. In the second logic programming device 20, the first interrupt signal arrives earlier than the timing when the storage module 203 completes the write operation. Therefore, in the second logic programming device 20, the shift register 201b can be used to record the historical information of the interrupt signal. When it is determined that the storage module 203 completes the write operation, the status information of the first interrupt signal can be obtained from the historical information, and based on this status information, a second interrupt signal is issued, which can ensure that the interrupt signal indicating the completion of the write operation is transmitted to the central processing unit 202 after the data is completely written, so that the central processing unit 202 can obtain accurate write data completion information.

[0053] In some alternative embodiments, when the storage module 203 is a storage controller, the data transmission system may further include a memory 30, and the memory 30 may be a DDR memory and is connected to the storage module 203, as Figure 6 shown. Correspondingly, the central processing unit 202 can be used to send a target read request to the storage module 203 when receiving the first interrupt signal. The storage module 203 can be used to read the second data corresponding to the target read request from the memory 30 based on the target read request when receiving the target read request and feedback the second data to the central processing unit 202. In this way, the central processing unit 202 can read accurate data from the memory 30 through the first interrupt signal after restoring the timing. Further, the accuracy of the dual logic programming device prototype verification can be improved.

[0054] In some alternative embodiments, the first logic programming device 10 may include a first General-Purpose Input / Output (GPIO) interface, the second logic programming device 20 may include a second General-Purpose Input / Output interface, the monitoring module 102 may be connected to the first General-Purpose Input / Output interface, the first General-Purpose Input / Output interface may be connected to the second General-Purpose Input / Output interface, and the second General-Purpose Input / Output interface may be connected to the delay processing module 201. Accordingly, the connection channels among the monitoring module 102, the first General-Purpose Input / Output interface, the second General-Purpose Input / Output interface, and the delay processing module 201 form a target communication link. The monitoring module 102 may be specifically configured to: send the operation duration indication information to the delay processing module 201 through the target communication link. In this way, by transmitting the operation duration indication information through the General-Purpose Input / Output interface, the transmission speed is faster.

[0055] The following uses a specific example to illustrate the advantages of the data transmission system provided by this application.

[0056] As Figure 7 shown in the data transmission system, it includes a DDR memory and an FPGA. Among them, the FPGA includes a DDR controller, a USB module, a central processing unit 202 with an ARM architecture, and an AXI interconnect bus. That is, when the hardware resources of a single FPGA are sufficient, the CPU with an ARM architecture and the USB module are all placed in one FPGA. In the work process, the CPU with an ARM architecture and the USB module can transmit write data through the AXI interconnect bus inside the FPGA.

[0057] In Figure 7 the shown architecture, the CPU with an ARM architecture can configure the USB module through the AXI interconnect bus. After the configuration is completed, the USB module can send data to the DDR controller through the AXI interconnect bus, and the DDR controller can store the received data in the DDR memory. When the USB module completes the write operation, by setting the interrupt signal to a high level state and sending it to the CPU with an ARM architecture to inform the CPU with an ARM architecture that the write operation has been completed, the interrupt signal in the high level state can be a 1-bit (Bit) indication information. After detecting the interrupt signal in the high level state, the CPU with an ARM architecture can access the DDR controller through the AXI interconnect bus, and the DDR controller reads the corresponding data from the DDR memory, so as to obtain the data written by the USB module into the DDR memory.

[0058] When the resources of a single FPGA are insufficient, for example, when performing large-scale System on Chip (SoC) prototype verification, the prototype design of the system on chip can be segmented, as Figure 8As shown in the figure, the USB module is placed on FPGA1, and the CPU with the ARM architecture is placed on FPGA0. The CPU with the ARM architecture and the USB module need to transfer data through Chip2Chip (C2C).

[0059] Under such an architecture, the CPU with the ARM architecture can transfer the configuration information of the USB module to the C2C of FPGA0 through the bus. The C2C of FPGA0 then transfers the configuration information to the C2C of FPGA1. Further, the C2C of FPGA1 can perform a configuration operation on the USB module based on the received configuration information. After the configuration operation is completed, the USB module initiates and executes a write operation to the DDR controller through its own internal Direct Memory Access (DMA) function. Specifically, it can be: transferring the write data to the C2C of FPGA1, the C2C of FPGA1 then transfers the write data to the C2C of FPGA0, and the C2C of FPGA0 then transfers the write data to the DDR controller through the AXI interconnect bus. The DDR controller writes the write data into the DDR memory. After the USB module completes the write operation, it sends an interrupt signal indicating the completion of the write operation to the CPU with the ARM architecture through the general-purpose input / output interface. After detecting this interrupt signal, the CPU with the ARM architecture can send a target read request to the DDR controller through the AXI interconnect bus to read the data corresponding to the target read request from the DDR memory through the DDR controller. For example, it reads the write data transferred by the USB module.

[0060] However, during the process of the USB module writing data to the DDR memory, it passes through two C2Cs (i.e., the C2C of FPGA0 and the C2C of FPGA1), and passes through the communication route between the two FPGAs. Therefore, there is a relatively large delay in the whole process from the USB module sending the write data to the DDR controller writing the write data. And the interrupt signal is directly transmitted to the CPU with the ARM architecture through the general-purpose input / output interface, so the delay of the interrupt signal is much smaller than the delay of writing data. Therefore, in the case of a large write data delay, when the CPU with the ARM architecture reads data from the DDR memory after responding to the interrupt signal indicating the completion of the write operation, the write data transferred by the USB module has not been completely written into the DDR memory, resulting in the CPU with the ARM architecture being unable to read accurate data.

[0061] To solve the above problems caused by splitting the various modules of the integrated circuit into different logic programming devices, a data transmission system as shown in Figure 9 can be adopted. In Figure 9 it still remains Figure 8Module segmentation layout of an integrated circuit. On this basis, cnt1 (i.e., the above-mentioned monitoring module 102) is set in FPGA1, and cnt0 (i.e., the above-mentioned delay processing module 201) is set in FPGA0. cnt1 is used to calculate the number of clock cycles spent from the USB module on FPGA1 sending write data to the DDR memory until the interrupt signal is pulled high. Moreover, cnt1 runs in the data bus clock domain. The number of clock cycles recorded in cnt1 is transmitted to FPGA0 through the general input / output interface. FPGA0 sets a shift register 201b with a bit width of 64 to shift the interrupt signal pulled high from FPGA1 to the high bit. The shift register 201b also works in the data bus clock domain. At the FPGA0 end, the rising time of the interrupt signal and the data arrival time are detected, and cnt0 is used to calculate the number of clock cycles by which the interrupt signal arrives earlier than the data signal. Since the shift register 201b has already delayed the prematurely arriving and pulled high interrupt signal, accordingly, based on the number of clock cycles recorded in cnt1 and the number of clock cycles recorded in cnt0, the corresponding bit (i.e., the above-mentioned storage unit) can be determined in the shift register 201b, and a pulled high interrupt signal is generated based on this and sent to the CPU of the ARM architecture, that is, the pulled high interrupt signal is delayed and transmitted to the CPU of the ARM architecture.

[0062] It can be seen from the above comparison that by using the number of clock cycles respectively recorded by cnt0 and cnt1, the interval duration and the sequence between the pulled high interrupt signal and the data can be accurately restored, so that the pulled high interrupt signal can be sent to the CPU of the ARM architecture only after the data is written into the DDR memory, that is, it can be ensured that the pulled high interrupt signal can accurately indicate that the data has been written, and further, the CPU can read accurate data from the DDR memory.

[0063] An embodiment of the present application provides a data transmission method, which can be applied to the data transmission system as described above, such as Figure 10 shown. The specific processing steps of the data transmission method may include: Step S1001, the write data module initiates and executes a write operation to the storage module.

[0064] Step S1002, the monitoring module obtains the operation duration indication information of the write data module executing the write operation.

[0065] Step S1003, the monitoring module sends the operation duration indication information to the delay processing module.

[0066] Step S1004, when the delay processing module receives the operation duration indication information and obtains the delay duration indication information corresponding to the write operation, it generates a first interrupt signal according to the operation duration indication information and the delay duration indication information.

[0067] Among them, the first interrupt signal is used to indicate that the write operation has been completed.

[0068] Step S1005, the delay processing module sends the first interrupt signal to the central processing unit.

[0069] For the specific processing of steps S1001 to S1005, reference can be made to the above description of the data transmission system, which will not be elaborated here.

[0070] In the data transmission method of the embodiment of the present application, a monitoring module is added to the first logic programming device, and a delay processing module is added to the second logic programming device. The monitoring module can monitor the duration by which the interrupt signal arrives later than the data in the first logic programming device. And, since the data will be delayed in arriving compared to the interrupt signal after being transmitted across programming devices (and needs to be processed by other modules on the way), the delay processing module can obtain the duration by which the interrupt signal arrives earlier than the data. By using the operation duration indication information and the delay duration indication information to generate the first interrupt signal, the timing of the interrupt signal used to indicate the completion of the write operation and the data on the side of the first logic programming device can be restored, that is, the first interrupt signal can accurately indicate that the storage module has completed the data write operation.

[0071] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0072] The embodiment of the present application also provides an electronic device, as Figure 11 shown, including a memory 110 and a processor 120. A computer program is stored in the memory 110, and the processor 120 is configured to run the computer program to execute the steps in any one of the above data transmission method embodiments. The electronic device can be the above-mentioned first logic programming device or second logic programming device.

[0073] The embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. Among them, the computer program is configured to execute the steps in any one of the above data transmission method embodiments when running.

[0074] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (abbreviated as ROM), random access memories (abbreviated as RAM), mobile hard disks, magnetic disks, or optical discs and other various media that can store computer programs.

[0075] An embodiment of the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above-described embodiments of the data transmission method are implemented.

[0076] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-described embodiments of the data transmission method are implemented.

[0077] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0078] The above has introduced in detail a data transmission system and method provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A data transmission system, characterized in that, The data transmission system includes a first logic programming device and a second logic programming device. Among them, the first logic programming device includes a monitoring module and a write data module, and the second logic programming device includes a delay processing module, a storage module, and a central processing unit; The write data module is used to initiate and execute a write operation to the storage module; The monitoring module is used to obtain operation duration indication information of the write data module executing the write operation; and send the operation duration indication information to the delay processing module; The delay processing module is used to generate a first interrupt signal according to the operation duration indication information and the delay duration indication information when receiving the operation duration indication information and obtaining delay duration indication information corresponding to transmitting the write operation, where the first interrupt signal is used to indicate that the write operation has been completed; and send the first interrupt signal to the central processing unit.

2. The data transmission system according to claim 1, characterized in that, The monitoring module includes a first timer; specifically, the monitoring module is used to: When detecting that the write data module issues a write data enable signal, start the first timer for timing operation; When detecting that the write data module issues a second interrupt signal, stop the first timer to stop the timing operation; Extract first timing information from the first timer as the operation duration indication information.

3. The data transmission system according to claim 2, wherein The delay processing module includes a second timer; specifically, the delay processing module is used to: When receiving the second interrupt signal sent by the write data module, start the second timer for timing; When detecting that the first data corresponding to the write operation arrives at the storage module, stop the second timer to stop the timing; Extract second timing information from the second timer as the delay duration indication information.

4. The data transmission system according to claim 1, characterized in that The monitoring module is specifically used to: Record the first moment when it is detected that the write data module issues a write data enable signal; And record the second moment when it is detected that the write data module issues a second interrupt signal; Determine the operation duration indication information according to the first moment and the second moment.

5. The data transmission system according to claim 4, wherein The monitoring module is specifically used to: Determine the difference obtained by subtracting the first moment from the second moment as the first delay duration; Use the first delay duration as the operation duration indication information.

6. The data transmission system according to claim 4, wherein The delay processing module is specifically used to: Record the third moment when it is detected that the second interrupt signal is received; And record the fourth moment when the first data corresponding to the write operation arrives at the storage module; Determine the delay duration indication information according to the third moment and the fourth moment.

7. The data transmission system according to claim 6, characterized in that, The delay processing module is specifically used to: Determine the difference obtained by subtracting the third moment from the fourth moment as the second delay duration; Determine the second delay duration as the delay duration indication information.

8. The data transmission system according to any one of claims 1 to 7, characterized in that The delay processing module is specifically used to: Determine total delay indication information according to the operation duration indication information and the delay duration indication information; Obtain target interrupt indication information corresponding to the total delay indication information according to the total delay indication information; Generate an interrupt signal corresponding to the target interrupt indication information based on the target interrupt indication information, where the interrupt signal corresponding to the target interrupt indication information is the first interrupt signal.

9. The data transmission system according to claim 8, wherein Both the operation duration indication information and the delay duration indication information are the number of clock cycles, and the total delay indication information is the target bit identification information; specifically, the delay processing module is configured to: Determine the sum value of the operation duration indication information and the delay duration indication information as the target bit identification information.

10. The data transmission system according to claim 9, characterized in that, The delay processing module is further configured to perform a delay operation on the interrupt signal of each clock cycle transmitted by the write data module.

11. The data transmission system according to claim 10, wherein The delay processing module further includes a plurality of storage units, and the plurality of storage units are arranged in a preset order; specifically, the delay processing module is configured to: In the current clock cycle, identify the first status information of the interrupt signal received in the current clock cycle. And, according to the order of each storage unit, perform a shift operation on the status information stored in each storage unit in sequence. After completing the shift operation of each storage unit, store the first status information in the initial storage unit, where the initial storage unit is the storage unit with the first order among the plurality of storage units.

12. The data transmission system according to claim 11, wherein The delay processing module is specifically configured to: Determine a target storage unit corresponding to the target bit identification information from the plurality of storage units according to the target bit identification information. Extract the second status information from the target storage unit as the target interrupt indication information.

13. The data transmission system according to any one of claims 1 to 7, characterized in that, When the storage module is a storage controller, the data transmission system further includes a memory, and the storage controller is connected to the memory; the central processing unit is further configured to: When receiving the first interrupt signal sent by the delay processing module, send a target read request to the storage module. The storage module is configured to, when receiving the target read request, read second data corresponding to the target read request from the memory based on the target read request and feed back the second data to the central processing unit.

14. The data transmission system according to any one of claims 1 to 7, characterized in that, The first logic programming device includes a first general-purpose input / output interface, the second logic programming device includes a second general-purpose input / output interface, the monitoring module is connected to the first general-purpose input / output interface, the first general-purpose input / output interface is connected to the second general-purpose input / output interface, the second general-purpose input / output interface is connected to the delay processing module, and the connection channels among the monitoring module, the first general-purpose input / output interface, the second general-purpose input / output interface, and the delay processing module form a target communication link; The monitoring module is specifically configured to: Send the operation duration indication information to the delay processing module through the target communication link.

15. A method for initiating an interrupt signal, characterized in that, The method is applied to a data transmission system as described in any one of claims 1 to 14. The data transmission system includes a first logic programming device and a second logic programming device. Among them, the first logic programming device includes a monitoring module and a data writing module, and the second logic programming device includes a delay processing module, a storage module, and a central processing unit; The method includes: The data writing module initiates and executes a write operation to the storage module; The monitoring module obtains operation duration indication information of the data writing module executing the write operation; and sends the operation duration indication information to the delay processing module; When receiving the operation duration indication information and obtaining delay duration indication information corresponding to transmitting the write operation, the delay processing module generates a first interrupt signal according to the operation duration indication information and the delay duration indication information, where the first interrupt signal is used to indicate that the write operation has been completed; and sends the first interrupt signal to the central processing unit.

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