Digital circuit engineering correction method and related equipment

Abstract

The invention belongs to the technical field of semiconductor design automation, and provides a digital circuit engineering correction method and related equipment. The method comprises the following steps: after wiring of a digital circuit is completed, performing static time sequence analysis based on actual circuit resistance-capacitance parasitic parameters of a time sequence path in the digital circuit to obtain global time sequence information of the time sequence path, and screening out an abnormal time sequence path containing an abnormal logic unit from the digital circuit based on the global time sequence information; performing logic unit change on the abnormal time sequence path containing the abnormal logic unit, and performing wiring change on the digital circuit after the logic unit change; and if the wiring violation does not exist in the digital circuit, returning to execute the step of performing the static time sequence analysis based on the actual circuit resistance-capacitance parasitic parameter of each time sequence path in the digital circuit until the abnormal time sequence path does not exist in the digital circuit. According to the technical scheme provided by the invention, the correction efficiency of the digital circuit engineering can be improved.

Description

Technical Field

[0001] This application belongs to the technical field of semiconductor design automation, and particularly relates to a method for correcting digital circuit engineering and related devices. Background Art

[0002] With the rapid development of semiconductor technology, the scale and complexity of digital circuits (such as digital integrated circuits) are constantly increasing, which makes wiring a crucial link in the field of Electronic Design Automation (EDA). Especially in the FinFET process, the wiring complexity in digital circuit design has increased significantly. Currently, anomalies such as timing violations often occur in the later stage of digital circuit design. If a complete layout and wiring process is redone, not only will it consume a large amount of time and resources, but it may also introduce new anomaly problems. Therefore, how to improve the correction efficiency of digital circuit engineering has become a technical problem to be solved urgently. Summary of the Invention

[0003] Embodiments of this application provide a method for correcting digital circuit engineering, a device, a computer program product, a computer-readable storage medium, and an electronic device, which can thus improve the correction efficiency of digital circuit engineering to a certain extent.

[0004] Other features and advantages of this application will become apparent through the following detailed description, or be learned in part through the practice of this application.

[0005] According to a first aspect of the embodiments of this application, a method for correcting digital circuit engineering is provided. The method includes: after completing the wiring of a digital circuit, performing static timing analysis based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit to obtain the global timing information of each timing path; based on the global timing information of each timing path, screening out abnormal timing paths containing abnormal logic units from the digital circuit; performing logic unit change on the abnormal timing paths containing abnormal logic units, and performing wiring change on the digital circuit after the logic unit change; if it is checked by a design rule check engine that there is no wiring violation in the digital circuit after the wiring change, then return to execute the step of performing static timing analysis based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit until there are no abnormal timing paths in the digital circuit.

[0006] In some embodiments of the present application, based on the foregoing solution, static timing analysis is performed based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit to obtain the global timing information of each timing path, including: based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit, a static timing analysis engine is called to calculate the timing parameter values of each logic unit in each timing path in at least one dimension, as the global timing information of each timing path.

[0007] In some embodiments of the present application, based on the foregoing solution, the abnormal timing paths including abnormal logic units are screened out from the digital circuit based on the global timing information of each timing path, including: obtaining a preset timing parameter threshold; if the timing parameter value of any logic unit in the digital circuit satisfies a preset size relationship with the timing parameter threshold, then the any logic unit is determined as an abnormal logic unit, and the timing path to which the abnormal logic unit belongs is determined as an abnormal timing path.

[0008] In some embodiments of the present application, based on the foregoing solution, the logic unit change for the abnormal timing path including the abnormal logic unit includes: obtaining a pre-constructed abnormal list and an alternative list, where the abnormal list is used to record the abnormal timing paths screened out from the digital circuit and the abnormal logic units in the abnormal timing paths, and the alternative list is used to record logic units of different configurable unit types, and the unit types include functional units and filling units; selecting a target abnormal timing path to be changed and a target abnormal logic unit in the target abnormal timing path from the abnormal list, determining the target change type of the logic unit, and selecting a logic unit to be placed from the alternative list; where the change type of the logic unit at least includes adding a logic unit, replacing a logic unit, and deleting a logic unit; based on the logic unit to be placed and the target abnormal logic unit, the logic unit change is performed on the target abnormal timing path according to the target change type.

[0009] In some embodiments of the present application, based on the foregoing solution, if the target change type is to add a logic unit, the logic unit to be placed is a first functional unit, and the logic unit change for the target abnormal timing path includes: placing the first functional unit in a target site area close to the target abnormal logic unit on the target abnormal timing path, where the site is a basic position unit on the timing path.

[0010] In some embodiments of the present application, based on the foregoing solution, the placing the first functional unit in the target site area on the target abnormal timing path close to the target abnormal logic unit includes: determining logic units within a preset radius centered on the target abnormal logic unit on the target abnormal timing path to obtain a logic unit list; sequentially traversing the sizes of the fill units in the logic unit list according to a set traversal order; when the size of any one fill unit is greater than or equal to the size of the first functional unit, or when the sum of the sizes of any group of sequentially adjacent fill units is greater than or equal to the size of the first functional unit, determining the site area occupied by the any one fill unit or the site area occupied by the any group of sequentially adjacent fill units as the target site area; deleting the fill units in the target site area, and placing the first functional unit in the target site area.

[0011] In some embodiments of the present application, based on the foregoing solution, the placing the first functional unit in the target site area includes: if the size of the target site area is greater than the size of the first functional unit, then based on the size difference between the size of the target site area and the size of the first functional unit, searching for one or more fill units from the alternative list according to a set search logic; combining the first functional unit with the one or more fill units to obtain a combined unit, where the size of the target site area is equal to the size of the combined unit; placing the combined unit in the target site area.

[0012] In some embodiments of the present application, based on the foregoing solution, the method further includes: if the first functional unit is a buffer unit, then calculating a radius threshold based on a signal integrity analysis engine; determining the preset radius, where the preset radius is greater than or equal to the radius threshold.

[0013] In some embodiments of the present application, based on the foregoing solution, if the target change type is replacing a logic unit, the logic unit to be placed is a second functional unit whose size is adapted to the target abnormal logic unit, and the changing the logic unit on the target abnormal timing path includes: deleting the target abnormal logic unit, and placing the second functional unit in the site area occupied by the target abnormal logic unit.

[0014] In some embodiments of the present application, based on the foregoing solution, if the target change type is to delete a logic unit, the logic unit to be placed is a filling unit or a combination of filling units that is dimensionally adapted to the target abnormal logic unit. The logic unit change to the target abnormal timing path includes: deleting the target abnormal logic unit and placing a filling unit or a combination of filling units that is dimensionally adapted to the target abnormal logic unit in the site area occupied by the target abnormal logic unit.

[0015] In some embodiments of the present application, based on the foregoing solution, the routing change to the digital circuit after the logic unit change includes: performing a local routing change on the digital circuit after the logic unit change; or performing a global routing change on the digital circuit after the logic unit change.

[0016] In some embodiments of the present application, based on the foregoing solution, the local routing change to the digital circuit after the logic unit change includes: taking a memory snapshot of the routing data of other timing paths except the abnormal timing path and clearing the routing data of the abnormal timing path; obtaining the routing data of the other timing paths in the memory and, based on the routing data of the other timing paths, calling a three-dimensional routing algorithm to re-route the abnormal timing path.

[0017] According to a second aspect of the embodiments of the present application, there is provided a digital circuit engineering correction device, the device including: an analysis unit, configured to perform static timing analysis based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit after the digital circuit routing is completed, to obtain the global timing information of each timing path; a screening unit, configured to screen out abnormal timing paths including abnormal logic units from the digital circuit based on the global timing information of each timing path; a change unit, configured to perform a logic unit change on the abnormal timing paths including abnormal logic units and perform a routing change on the digital circuit after the logic unit change; an inspection unit, configured to, if it is checked by a design rule checking engine that there is no routing violation in the digital circuit after the routing change, return to execute the step of performing static timing analysis based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit until there are no abnormal timing paths in the digital circuit.

[0018] According to a third aspect of the embodiments of the present application, there is provided a computer program product, the computer program product including computer instructions, the computer instructions being stored in a computer-readable storage medium and being adapted to be read and executed by a processor so that a computer device having the processor performs operations to implement the operations performed by the method as described in the first aspect above.

[0019] According to a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided. At least one computer program instruction is stored in the computer-readable storage medium, and the at least one computer program instruction is loaded and executed by a processor to implement the operations performed by the method described in the first aspect above.

[0020] According to a fifth aspect of the embodiments of the present application, an electronic device is provided. The electronic device includes one or more processors and one or more memories. At least one computer program instruction is stored in the one or more memories, and the at least one computer program instruction is loaded and executed by the one or more processors to implement the operations performed by the method described in the first aspect above.

[0021] Based on the technical solution proposed in the present application, the correction efficiency of digital circuit engineering can be significantly improved. Specifically, first, after the wiring is completed, static timing analysis based on the resistance-capacitance parasitic parameters of the actual circuit can obtain more real and accurate global timing information, avoiding the timing analysis deviation caused by inaccurate parameters before wiring in the traditional ECO method, thereby improving the accuracy of timing violation detection. Second, by changing the logic units included in the abnormal timing paths and combining means such as incremental wiring, only the local wiring can be quickly changed without re-performing global placement and routing, which can greatly shorten the correction cycle of digital circuit engineering and improve the iteration efficiency of digital circuits. In addition, the present application uses a design rule check engine to real-time verify the digital circuit after wiring changes, ensuring that wiring violations can be detected and eliminated in a timely manner after each local correction, which can guarantee the reliability and design quality of the digital circuit correction process. Circular iterative analysis and correction until all timing paths are normal can further ensure that the timing performance of the final digital circuit meets the design requirements.

[0022] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings: Figure 1 A flowchart of the digital circuit engineering correction method in the embodiments of the present application is shown; Figure 2 A first schematic diagram of adding a logic unit in a digital circuit in the embodiments of the present application is shown; Figure 3 The second schematic diagram showing the addition of logic units in a digital circuit in an embodiment of the present application; Figure 4 The block diagram of a digital circuit engineering correction device in an embodiment of the present application; Figure 5 The structural schematic diagram of an electronic device in an embodiment of the present application. Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0025] In addition, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be used. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present application.

[0026] The block diagrams shown in the accompanying drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. It should also be noted that in the accompanying drawings, for the sake of simplicity of the drawings, some components that do not affect the explanation of the technical solutions of the present application are adaptively omitted.

[0027] The flowcharts shown in the accompanying drawings are only exemplary illustrations and do not necessarily include all the contents and operations / steps, nor do they necessarily need to be executed in the described order. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined. Therefore, the actual execution order may change according to the actual situation.

[0028] In the description of this application, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0029] To enable those skilled in the art to better understand this application, the technical concepts and application backgrounds involved in this application will be briefly described first.

[0030] Digital Circuit (DC): A digital circuit refers to an electronic circuit that uses digital signals (i.e., only taking a finite number of discrete values, usually "0" and "1") as information carriers and processes, transmits, and stores information through electronic devices such as logic gates. Digital circuits are based on Boolean algebra and can implement various logical operations, arithmetic operations, data storage, and control functions. They are the core components of modern computer, communication, and automatic control systems.

[0031] Digital Circuit Routing (DCR): Digital circuit routing generally refers to the process of connecting various functional units, logic gates, and circuit blocks inside a chip (such as FPGA, CPU, GPU, etc.) according to design requirements through metal interconnects.

[0032] Currently, with the continuous progress of semiconductor technology, the scale and complexity of digital circuits are increasing day by day. In the design process of digital circuits, routing is an extremely critical link. Especially under advanced process nodes such as FinFET, due to the changes in process physical characteristics, the parasitic parameters such as circuit impedance and capacitance become more complex, thereby greatly increasing the difficulty of routing and the complexity of timing analysis.

[0033] In the later stage of digital circuit design, abnormal problems such as timing violations often occur. In response, the traditional solution is generally to re-layout and route the entire digital circuit, but this not only consumes a large amount of time and computing resources but may also introduce new abnormal problems due to large-scale changes. In this case, this application proposes a digital circuit engineering correction scheme, which can improve the efficiency of digital circuit engineering correction to quickly and efficiently correct abnormal timing paths in digital circuits while ensuring the correctness of the design.

[0034] The implementation details of the technical solutions of the embodiments of this application will be elaborated below: Refer to Figure 1, which shows the flowchart of the digital circuit engineering correction method in the embodiments of the present application. This digital circuit engineering correction method can be executed by a device with computing and processing capabilities. Refer to Figure 1 As shown, this digital circuit engineering correction method at least includes steps 110 to 140, which are introduced in detail as follows: Refer to Figure 1 , in step 110, after the digital circuit wiring is completed, static timing analysis is performed based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit to obtain the global timing information of each timing path.

[0035] In the present application, there are multiple timing paths (which can also be called timing channels, timing links, signal paths, signal / timing networks, etc.) in the digital circuit. Specifically, a timing path refers to the signal transmission path in the digital circuit where the signal starts from the output end of a clock flip-flop (such as a flip-flop, latch, register, storage unit, etc.), passes through several logic cells (Cells) and wiring, and finally reaches the input end of another clock flip-flop. According to the different starting and ending points, timing paths can generally be divided into data paths, clock paths, input paths, output paths, cross-domain paths, etc.

[0036] In the present application, after the digital circuit wiring is completed, the parasitic parameters of the completed wiring data can be read through a physical design tool to obtain the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit. The circuit resistance-capacitance parasitic parameters, which can be abbreviated as RC parasitic parameters, refer to the parasitic resistance (R) and parasitic capacitance (C) inevitably generated due to metal interconnects, vias, metal layer interfaces, adjacent signal lines, etc. during the physical implementation of the digital circuit. These parameters can reflect the additional electrical characteristics introduced by the physical structure and material properties in the actual physical circuit in addition to the ideal logic cells.

[0037] During the digital circuit design process, after the wiring is completed, the actual circuit physical characteristics (such as wiring length, metal layer distribution, coupling relationship, etc.) will directly affect the signal delay on each timing path. That is to say, the actual delay of each timing path not only depends on the delay of the logic gate itself but is also significantly affected by the parasitic parameters such as resistance (R) and capacitance (C) introduced by the wiring. Therefore, after the wiring is completed, the global timing information of each timing path can be determined according to the extracted actual circuit resistance-capacitance parasitic parameters of each timing path.

[0038] In this application, static timing analysis is performed based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit, and the global timing information of each timing path is obtained, which can be executed according to the following step 111: Step 111: Based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit, call a static timing analysis engine to calculate the timing parameter values of each logic cell in each timing path in at least one dimension as the global timing information of each timing path.

[0039] In this application, the actual circuit resistance-capacitance parasitic parameters on each timing path can be associated with the logic netlist to form a physical-level real path model. Then, a static timing analysis (STA) engine can be called to load the netlist, process library, and actual circuit resistance-capacitance parasitic parameters, perform timing calculations on each timing path level by level, and obtain the multi-dimensional timing parameter values of each logic cell. Finally, the critical timing parameters of all logic cells on each timing path are summarized to form the global timing information of the path. Since the resistance-capacitance parasitic parameters obtained after routing can truly reflect the additional electrical characteristics introduced in the physical implementation process of the digital circuit, the global timing information of the timing path can be accurately estimated according to these resistance-capacitance parasitic parameter information through the static timing analysis algorithm, thereby providing a precise basis for the subsequent correction of the digital circuit and improving the correction efficiency of the digital circuit project.

[0040] In this application, the timing parameter values can specifically include at least one of the following dimensions: Delay: Delay refers to the time it takes for a signal to travel from one point to another in a circuit. It can reflect the time lag generated when the signal passes through components such as logic gates and wires; Setup Time: Setup Time is the minimum time that a data signal must remain stable before the effective edge (such as the rising edge or falling edge) of the clock signal arrives. Simply put, the data needs to be prepared in advance so that the clock signal can correctly sample the stable data; Arrival Time: Arrival Time refers to the actual time when a signal arrives at a specific pin. It is the time point when the signal starts from the signal source, passes through a series of logic gates and wires, and finally arrives at the target pin; Slack: Slack is the difference between the actual arrival time and the required arrival time. It reflects the margin of the signal arrival time and is an important indicator for measuring whether the timing meets the requirements; Required Time: The required time refers to the latest time when a signal must reach a specific pin, which is determined according to the timing requirements of the circuit and the period of the clock signal; Slew: Slew refers to the rate of change of the signal voltage, indicating the time required for the signal to change from one level to another; Load: Load refers to the devices or components connected to the power supply or signal source in a circuit. These devices consume power or receive signals. The characteristics of the load will affect the performance of the circuit, such as current, power, and signal integrity.

[0041] In the actual design process, for example, a certain timing path is Register A → BUF1 → AND2 → INV3 → Register B. Suppose after extracting the resistance-capacitance parasitic parameters of the actual circuit, the global timing information of this timing path is: the delay of BUF1 is 50 ps, the slew is 120 ps, and the load is 0.2 pF; the delay of AND2 is 80 ps, the slew is 180 ps, and the load is 0.35 pF; the delay of INV3 is 60 ps, the slew is 110 ps, and the load is 0.1 pF. Among them, there are large capacitance and coupling capacitance in the wiring between BUF1 and AND2. The STA engine analyzes based on the resistance-capacitance parasitic parameters of the actual circuit and finds that the output slew of AND2 becomes slower, resulting in an increase in the delay of INV3, and finally making the setup margin of the entire timing path -30 ps.

[0042] Based on the technical solution in step 111 above, by introducing the resistance-capacitance parasitic parameters of the actual circuit, the parasitic effects of the resistance and capacitance in the actual circuit can be fully considered, avoiding misjudgment by the ideal static timing analysis engine, achieving high-accuracy timing analysis, and ensuring that the analysis results are highly consistent with the true performance of the digital circuit after physical implementation. At the same time, by calling the static timing analysis engine to calculate the global timing information of each timing path, the timing performance of each logic unit can be analyzed in detail, providing an accurate basis for the subsequent correction of the digital circuit, and thus improving the correction efficiency of the digital circuit project.

[0043] Overall, this step realizes the accurate calculation and summary of multi-dimensional timing parameters of each timing path and its internal logic units through static timing analysis based on the resistance-capacitance parasitic parameters of the actual circuit, providing a solid data foundation for subsequent timing anomaly detection, correction, and optimization, and is a key technical link to achieve high-quality and high-reliability digital circuit design.

[0044] Continue to refer to Figure 1 , in step 120, based on the global timing information of each timing path, abnormal timing paths containing abnormal logic units are screened out from the digital circuit.

[0045] In this application, specifically, based on the global timing information of each timing path, the abnormal timing paths containing abnormal logic units are screened out from the digital circuit, which can be executed according to the following steps 121 to 122: Step 121, obtain a preset timing parameter threshold.

[0046] Step 122, if the preset size relationship is satisfied between the timing parameter value of any logic unit in the digital circuit and the timing parameter threshold, then determine the any logic unit as an abnormal logic unit, and determine the timing path to which the abnormal logic unit belongs as an abnormal timing path.

[0047] In this application, the timing parameter threshold refers to the allowable range set for various timing parameters (such as delay, slew, load, timing margin, etc.) according to design specifications, process requirements, empirical data or simulation results. This threshold can be set separately according to different logic unit types and different timing path categories to meet the diverse needs of complex digital circuit designs. For example, the delay threshold of a certain logic unit can be set to not exceed 200 ps, and the slew threshold can be set to not be greater than 150 ps, etc.

[0048] In this application, the preset size relationship can include comparison symbols such as ">", "<", "≥", "≤", etc., which are used to define the judgment criteria between the timing parameter value and the corresponding timing parameter threshold.

[0049] In the screening process of abnormal logic units and abnormal timing paths, first, all logic units on each timing path can be traversed to check whether the preset size relationship is satisfied between each timing parameter value and its corresponding threshold. For example, judge whether the delay exceeds the threshold, or whether the slew is too slow. Once it is detected that a certain timing parameter value exceeds its corresponding threshold, this logic unit can be marked as an "abnormal logic unit". Subsequently, the entire timing path containing this abnormal logic unit will also be marked as an "abnormal timing path".

[0050] In addition, this application also supports the combined judgment of multiple timing parameter values. For example, it can be configured to determine as abnormal only when both the delay and the slew exceed the corresponding thresholds, so as to implement a flexible abnormal judgment strategy. Further, in the scenario of large-scale circuit design, this application can also automatically and batch screen abnormal logic units and abnormal timing paths to improve the design and verification efficiency.

[0051] Continue to refer to Figure 1 , in step 130, perform logic unit changes on the abnormal timing paths containing abnormal logic units, and perform routing changes on the digital circuit after the logic unit changes.

[0052] In this application, an exception list and an alternative list can be pre-constructed and saved in memory.

[0053] Among them, the exception list can be used to record the abnormal timing paths screened out from the digital circuit and the abnormal logic units in the abnormal timing paths. Specifically, the exception list can include all the screened abnormal timing paths and their corresponding abnormal logic units, as well as relevant timing parameter values (such as delay, slew, etc.); the alternative list can be used to record logic units of different configurable unit types. Specifically, the alternative list includes logic units of different selectable unit types, such as functional units and filler units.

[0054] Specifically, the functional unit, also known as the Standard Cell, refers to the basic circuit unit that undertakes specific logic or storage functions in digital circuit design. They are the "building blocks" for implementing chip functions, such as AND gates, OR gates, NOT gates, flip-flops, latches, adders, etc. For example, the inverter INV_X1 has a driving ability of 1, and for another example, the two-input AND gate AND2_X2 has a driving ability of 2, and also for example, the D flip-flop DFF_X1. The filler unit, also called the Filler Cell, is a unit without any logic function and is only used for physical filling. Its main role is to fill the gaps between standard cells during the Place&Route process to ensure the integrity of the chip's physical structure and process requirements. For example, filler units FILL1, FILL2, FILL4 with different widths (sizes).

[0055] In this application, the logical unit change for the abnormal timing path containing the abnormal logic unit can be performed according to the following steps 131 to 133: Step 131, obtain the pre-constructed exception list and alternative list.

[0056] Step 132, select the target abnormal timing path to be changed and the target abnormal logic unit in the target abnormal timing path from the exception list, determine the target change type of the logic unit, and select the logic unit to be placed from the alternative list. Among them, the change types of the logic unit at least include adding a logic unit, replacing a logic unit, and deleting a logic unit.

[0057] Step 133, based on the logic unit to be placed and the target abnormal logic unit, perform a logical unit change on the target abnormal timing path according to the target change type.

[0058] In this application, the user may select a target abnormal timing path to be changed and a target abnormal logic unit in the target abnormal timing path from the abnormal list, determine the target change type of the logic unit, and select a logic unit to be placed from the alternative list. Alternatively, the target abnormal timing path to be changed and the target abnormal logic unit in the target abnormal timing path may be automatically selected from the abnormal list based on a preset rule, the target change type of the logic unit may be determined, and a logic unit to be placed may be selected from the alternative list. This application does not make excessive limitations in this regard.

[0059] In this application, the selected target abnormal timing path may be any one or more abnormal timing paths in the digital circuit, or all the abnormal timing paths in the digital circuit. This application does not make excessive limitations in this regard. Further, the selected target abnormal logic unit may be any one (or the first one in the timing direction) of the abnormal logic units in the target abnormal timing path, or all the abnormal logic units in the target abnormal timing path. This application does not make excessive limitations in this regard. If the selected target abnormal timing path is all the abnormal timing paths in the digital circuit, batch change of the abnormal timing paths can be implemented subsequently. If the selected target abnormal logic unit is all the abnormal logic units in the target abnormal timing path, batch change of the abnormal logic units can be implemented subsequently.

[0060] In this application, the target abnormal timing path that needs to be corrected first and the target abnormal logic unit therein may also be selected from the abnormal list according to the priority (such as the smallest timing margin, the largest delay exceeding the limit, etc.).

[0061] In this application, the change types of the logic unit may at least include adding a logic unit, replacing a logic unit, and deleting a logic unit. For example, when the driving ability is insufficient or the load is too large, a buffer or a driving enhancement unit may be inserted (i.e., adding a logic unit). For another example, it may be replaced with a similar unit with a larger drive, faster delay, or better slew (i.e., replacing a logic unit). For still another example, redundant gates, invalid buffers, etc. that can shorten the path may be directly removed (i.e., deleting a logic unit).

[0062] In this application, available logic units to be placed (such as logic units with different process dimensions and different driving abilities) may be screened out from the alternative list according to the determined target change type, the process compatibility of the logic unit, the functional requirements, etc.

[0063] In this application, after selecting the target abnormal logic unit, determining the target change type of the logic unit, and selecting the logic unit to be placed, the logic unit change of the target abnormal timing path may be performed based on the logic unit to be placed and the target abnormal logic unit according to the target change type.

[0064] For example, in a certain abnormal timing path, it is detected that the driving ability of INV3 (inverter 3) is insufficient, resulting in a slow output slew. After the system analysis recommends "replace the logic unit", a larger driving ability INV3 can be selected from the alternative list to replace the original INV3. Or there is a long-distance wiring and signal attenuation between BUF1 and AND2 on a certain path. After the system analysis recommends "add logic unit", a buffer BUF2 can be inserted between the two.

[0065] In the present application, by automatically selecting the target abnormal timing path, the target abnormal logic unit, and the appropriate target change type, and performing operations such as adding, replacing, or deleting logic units, efficient and accurate correction of timing anomalies can be achieved. In this way, not only can the efficiency and effect of timing optimization after digital circuit wiring be improved, but also a solid foundation can be provided for the subsequent automated design closed-loop.

[0066] Specifically, in the present application, if the target change type is to add a logic unit, the logic unit to be placed is the first functional unit.

[0067] In the present application, the first functional unit can select a suitable functional unit (such as a buffer or an inverter) according to the abnormal type of the target abnormal unit (such as insufficient drive or excessive delay), and determine its parameters such as drive ability and size.

[0068] Further, the logic unit change for the target abnormal timing path can be performed according to the following step 1331: Step 1331, place the first functional unit in the target site area close to the target abnormal logic unit on the target abnormal timing path, where the site is the basic position unit on the timing path.

[0069] In the present application, the site is the basic position unit in the placement and routing (i.e., on the timing path), usually aligned with the step of the cell library (such as one site per 0.19 μm). According to the position of the target abnormal logic unit, combined with physical layout, congestion situation, power / ground distribution, etc., the target site area close to the target abnormal logic unit can be preferentially selected, and the first functional unit (such as BUF_X2) is placed in the target site area upstream or downstream of the target abnormal logic unit. For example, if the first functional unit is a logic unit with enhanced drive, the first functional unit can be placed upstream of the target abnormal logic unit. If the first functional unit is a logic unit for signal shaping or timing adjustment, the first functional unit can also be placed downstream of the target abnormal logic unit.

[0070] In this application, a specific site area can be directly set according to the actual situation for placing the first functional unit.

[0071] It should be noted that before placing the first functional unit, physical and process verification need to be carried out. First, it is necessary to check whether there is enough space in the target site area to avoid overlap between the first functional unit and other existing functional units on the target abnormal timing path.

[0072] In some embodiments of this application, placing the first functional unit in the target site area on the target abnormal timing path close to the target abnormal logic unit can also be performed according to the following steps 13311 to 13314: Step 13311: Determine the logic units within a preset radius range centered on the target abnormal logic unit on the target abnormal timing path to obtain a logic unit list.

[0073] Step 13312: Traverse the sizes of the filling units in the logic unit list in the set traversal order.

[0074] Step 13313: When the size of any one filling unit is greater than or equal to the size of the first functional unit, or when the sum of the sizes of any group of adjacent filling units in sequence is greater than or equal to the size of the first functional unit, determine the site area occupied by the any one filling unit or the site area occupied by the any group of adjacent filling units in sequence as the target site area.

[0075] Step 13314: Delete the filling units in the target site area and place the first functional unit in the target site area.

[0076] In this application, through fine screening and operation of the area on the target abnormal timing path close to the target abnormal logic unit, precise placement of the first functional unit can be achieved. First, within a preset radius range centered on the target abnormal logic unit, determine the logic units within this range to generate a logic unit list. Then, the three-dimensional layout shape database of the digital circuit can be queried, and in the set traversal order, check the sizes of each filling unit in the logic unit list in turn. When it is found that the size of a certain filling unit is greater than or equal to the size of the first functional unit, or when the sum of the sizes of a group of adjacent filling units is greater than or equal to the first functional unit, the site area occupied by this filling unit or this group of adjacent filling units is determined as the target site area. Finally, delete the filling units in the target site area and accurately place the first functional unit into this target site area, so as to make full use of the space reserved by the filling units without affecting the normal layout of the functional units, and achieve physical optimization of the abnormal timing path.

[0077] Through the above steps 13311 to 13314, the efficiency and performance of digital circuit design can be significantly improved. First of all, clarifying the logic units within the radius centered on the target abnormal logic unit helps to quickly circle the logic units to be analyzed, form a list of logic units, and make subsequent processing more systematic. By setting the traversal order and checking the sizes of the filling units one by one, those filling units that can be replaced can be effectively found. After determining the target site area, deleting unnecessary filling units can not only clean up the redundant parts in the circuit design, but also create space for possible subsequent unit combinations, thus providing a basis for optimizing the design.

[0078] In this application, the following steps 133111 to 133112 can also be executed: Step 133111, if the first functional unit is a buffer unit (Buffer), calculate a radius threshold based on a signal integrity analysis (SI) engine.

[0079] Step 133112, determine the preset radius, where the preset radius is greater than or equal to the radius threshold.

[0080] In this application, for the special case where the first functional unit is a buffer unit (Buffer), the selection process of the preset radius centered on the target abnormal logic unit is further optimized. Specifically, first, the target abnormal timing path is evaluated by a signal integrity analysis (SI) engine to calculate the minimum radius threshold that meets the signal integrity requirements, ensuring that the placement of the buffer unit can effectively improve the signal quality. Subsequently, based on this radius threshold, the preset radius is reasonably determined to be greater than or equal to this radius threshold, so that in the subsequent selection process of the target site area, it is ensured that the layout of the buffer unit not only meets the space requirements, but also takes into account the signal integrity optimization goal, ensuring that the physical position of the buffer helps to improve the signal transmission quality and system stability.

[0081] In the above step 13314, the placement of the first functional unit in the target site area can be executed according to the following step 133141: Step 133141, if the size of the target site area is equal to the size of the first functional unit, the first functional unit can be directly placed in the target site area.

[0082] Furthermore, in the above step 13314, the placement of the first functional unit in the target site area can also be executed according to the following steps 133142 to 133144: Step 133142: If the size of the target site area is greater than the size of the first functional unit, then based on the size difference between the size of the target site area and the size of the first functional unit, search for one or more filling units from the alternative list according to the set search logic.

[0083] Step 133143: Combine the first functional unit with the one or more filling units to obtain a combined unit, where the size of the target site area is equal to the size of the combined unit.

[0084] Step 133144: Place the combined unit in the target site area.

[0085] In this application, to enable those skilled in the art to better understand this application, the following will be described with Figure 2 and Figure 3 by taking a specific embodiment as an example.

[0086] See Figure 2 and Figure 3 , which respectively show the first schematic diagram and the second schematic diagram of adding a logic unit in a digital circuit in the embodiments of this application.

[0087] In practical applications, in the target abnormal timing path as Figure 2 shown, it at least includes logic units A - N, where the timing direction of the logic units A - N is: A → B → C → D → E → F → G → H → I → J → K → L → M → N.

[0088] In addition, in this target abnormal timing path, assume that the functional unit G is the target abnormal logic unit and has insufficient driving ability.

[0089] In this case, logical units within a preset radius φ centered on the functional unit G can be determined in this target abnormal timing path to obtain a list of logical units, where this list of logical units includes filling unit A, functional unit B, filling unit C, filling unit D, functional unit E, filling unit F, filling unit H, functional unit I, filling unit J, functional unit K, filling unit L, functional unit M, and functional unit N.

[0090] Further, the sizes of the padding units in the logic unit list can be traversed in sequence according to the traversal order in the time series direction. Specifically, when traversing to any logic unit that is a padding unit, it can be determined whether the size of the padding unit is greater than or equal to the size of the first functional unit. If so, the site area occupied by the padding unit is determined as the target site area and the traversal is stopped. If not, it is determined whether the next adjacent logic unit is a padding unit. If so, it is determined whether the sum of the sizes of the padding unit and the next padding unit is greater than or equal to the size of the first functional unit. If so, the site area occupied by the padding unit and the next padding unit is determined as the target site area and the traversal is stopped. If not, it continues to determine whether the third logic unit is a padding unit, and so on in a loop until the traversal is stopped when the sum of the sizes of sequentially adjacent padding units is greater than or equal to the size of the first functional unit, or when the traversed logic unit is a functional unit, and then the subsequent padding units are traversed again.

[0091] As Figure 2 shown, when traversing to padding unit A, its size is 1 site, which is smaller than the size of functional unit O to be placed, which is 8 sites. Therefore, the traversal continues to logic unit B. Since logic unit B is a functional unit, the traversal starts again from logic unit C. Since logic unit C is a padding unit and its size is 5 sites, which is smaller than the size of functional unit O to be placed, which is 8 sites, the traversal continues to logic unit D. Since logic unit D is a padding unit, the sum of the sizes of logic unit C and logic unit D is compared, which is 7 sites. Since 7 sites is smaller than the size of functional unit O to be placed, which is 8 sites, the traversal continues to logic unit E. Since logic unit E is a functional unit, the traversal starts again from logic unit F. Since logic unit F is a padding unit and its size is 9 sites, which is greater than the size of functional unit O to be placed, which is 8 sites, the site area occupied by logic unit F can be determined as the target site area and the traversal is stopped.

[0092] After determining the target site area, the padding units in the target site area can be deleted.

[0093] Further, if the size of the target site area is greater than the size of the first functional unit, one or more padding units are searched from the alternative list according to the set search logic based on the size difference between the size of the target site area and the size of the first functional unit. As Figure 3As shown, the size of the target site area 9site is 1 site larger than the size of the functional unit O to be placed 8site. Therefore, the filling unit P with a size of 1 site can be found from the alternative list according to the set search logic (such as the logic of arranging the filling unit sizes from largest to smallest). By combining the functional unit O to be placed and the filling unit P, a combined unit with a size of 9site is obtained, which is equal to the size of the target site area 9site. Finally, this combined unit can be placed in the target site area.

[0094] Through the above steps 133142 to 133144, if the size of the target site area is larger than the size of the first functional unit, by searching for the filling unit in the alternative list and combining them, it is ensured that the size of the combined unit matches the size of the target site area, which can effectively fill the blank position in the target abnormal timing path. In this way, it can not only improve the design flexibility but also reduce potential problems caused by size mismatch. In addition, this process enhances the design controllability, enabling designers to quickly respond and adjust the design in a complex digital circuit environment to meet the timing requirements. Thus, the design cycle can be reduced, the design cost can be lowered, and at the same time, the stability and reliability of the circuit can be improved.

[0095] Generally speaking, through the above method, the fixed-point optimization of the target abnormal logic unit in the target abnormal timing path can be achieved, improving the correction efficiency and effect. It can not only standardize the placement process of the first functional unit for easy automation by EDA tools but also ensure that the placement operation of the functional unit does not damage the physical and technological integrity of the digital circuit, effectively alleviating the timing violation caused by insufficient driving ability or excessive load, improving the correction efficiency of the digital circuit project, and accelerating the convergence and optimization of the digital circuit design.

[0096] In this application, if the target change type is to replace the logic unit, the logic unit to be placed is the second functional unit with a size adapted to the target abnormal logic unit.

[0097] Furthermore, the logic unit change for the target abnormal timing path can be carried out according to the following steps 1332: Step 1332: Delete the target abnormal logic unit and place the second functional unit in the site area occupied by the target abnormal logic unit.

[0098] In this application, when the target change type is replacing a logic unit, optimization is mainly carried out for the case where the target abnormal logic unit has performance or timing problems. First, a second functional unit that is compatible in size and equivalent in function to the target abnormal logic unit can be selected as the logic unit to be placed, so as to ensure that no spatial conflict or function loss is introduced after replacement. Subsequently, the original target abnormal logic unit is deleted, and the second functional unit is directly placed in the site area it originally occupied, realizing a seamless replacement. In this way, not only can the continuity and rationality of the physical layout be ensured, but also the performance index of the target abnormal timing path can be effectively improved, optimizing the timing and function performance of the overall circuit.

[0099] In this application, if the target change type is deleting a logic unit, the logic unit to be placed is a filling unit or a combination of filling units that is adapted in size to the target abnormal logic unit.

[0100] Furthermore, the logic unit change to the target abnormal timing path can be carried out according to the following step 1333: Step 1333, delete the target abnormal logic unit, and place a filling unit or a combination of filling units that is adapted in size to the target abnormal logic unit in the site area occupied by the target abnormal logic unit.

[0101] In this application, when the target change type is deleting a logic unit, for the case where the target abnormal logic unit needs to be removed from the target abnormal timing path, first, a filling unit or a combination of filling units that matches the size of the target abnormal logic unit can be selected as the logic unit to be placed, so as to ensure that there will be no vacancy or layout chaos in the site area after deletion. Then, perform the deletion operation, remove the target abnormal logic unit from its original site area, and accurately place the selected filling unit or combination of filling units in this area. Through this process, not only can the target abnormal logic unit be effectively removed, but also the integrity of the physical structure of the digital circuit and the continuity of the layout can be maintained, preventing process or electrical problems caused by blank areas, thereby improving the reliability of the digital circuit design and the controllability of the manufacturing process.

[0102] In this application, the routing change to the digital circuit after the logic unit change can be carried out according to the following step 134: Step 134, perform a local routing change to the digital circuit after the logic unit change.

[0103] Specifically, the local routing change to the digital circuit after the logic unit change can be carried out according to the following steps 1341 to 1342: Step 1341: Take a memory snapshot of the routing data of other timing paths except the abnormal timing path, and clear the routing data of the abnormal timing path.

[0104] Step 1342: Obtain the routing data of the other timing paths in the memory, and based on the routing data of the other timing paths, call a 3D routing algorithm to re-route the abnormal timing path.

[0105] In this application, first, take a memory snapshot of the routing data of all other timing paths except the abnormal timing path, that is, completely save the current routing status of these timing paths to ensure that subsequent operations will not affect the routing integrity and correctness of the normal timing paths. Subsequently, for the abnormal timing path, all its original routing data is cleared. In this way, it can be ensured that only the abnormal timing path is corrected for routing, avoiding unnecessary disturbances to the routing of the entire circuit. In addition, by only deleting the routing of the abnormal timing path, space is reserved for subsequent re-routing, eliminating congestion or conflicts that may be caused by the original routing. At the same time, using the memory snapshot can ensure that the routing of other paths can be used as a constraint and reference for subsequent routing algorithms.

[0106] In this application, further, the routing data of other timing paths can be obtained and restored from the memory to ensure that the routing information of these timing paths is visible and valid during the execution of the algorithm. Based on the existing routing, the abnormal timing path is pushed into the routing priority queue, the routing mode is set to rip-up and re-route, and a 3D routing algorithm is called to re-route the abnormal timing path. During the routing process, the new routing will fully consider the routing distribution and space occupancy of other timing paths to avoid resource conflicts or design rule violations. The 3D routing algorithm can flexibly allocate routing paths in space and hierarchy, improving the success rate and quality of routing. In addition, since only local optimization is performed on the abnormal timing path, the efficiency of routing correction can be significantly improved, reducing the complexity and risk of global routing.

[0107] Generally speaking, the above steps 1341 to 1342 ensure that the abnormal timing path can obtain efficient and reliable re-routing support without affecting other normal paths through the method of "snapshot - clear - restore - local re-routing", thereby improving the maintainability and design quality in the digital circuit ECO scenario.

[0108] In this application, for the routing change of the digital circuit after the logic unit change, it can also be executed according to the following step 135: Step 135: Perform a global routing change on the digital circuit after the logic unit change.

[0109] In this application, all timing paths and routing resources of the entire digital circuit can be comprehensively re-planned and optimized. That is, reallocate global routing resources, adjust the routing of all timing paths, solve possible congestion, timing, or design rule conflicts, and comprehensively consider the multi-layer (3D) routing layout. Finally, ensure the overall routing quality, timing performance, and full compliance with design rules of the entire digital circuit through the global routing algorithm. To adapt to the situation of large-scale ECO or simultaneous changes in multiple logic units, significantly improve the routing optimization effect and design reliability of the overall circuit.

[0110] In this application, after performing local routing changes on the digital circuit after logic unit changes, or global routing changes on the digital circuit after logic unit changes, a 3D DRC (Design Rule Check) engine can be invoked to perform three-dimensional design rule checks on the routing results of the changed area or the entire digital circuit. This 3D DRC engine can comprehensively analyze the spatial relationships between all routing layers, automatically detect problems such as routing pitch, line width, crossovers, via holes between layers, and possible short circuits and open circuits, ensuring that the routing results meet the process design specifications and electrical safety requirements in three-dimensional space. Through the rapid check of the 3D DRC engine, physical violation problems that may be introduced after routing changes can be promptly discovered and located, thus providing strong guarantee for subsequent routing correction and design convergence, and improving the correctness and reliability of routing design.

[0111] Continue to refer to Figure 1 , in step 140, if there are no routing violations in the digital circuit after routing changes based on the design rule check engine, return to execute the step of performing static timing analysis based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit until there are no abnormal timing paths in the digital circuit.

[0112] In this application, if it is confirmed by the design rule check engine that there are no any routing violations in the digital circuit after routing changes, return to execute step 110 as shown in Figure 1 , that is, re-execute the step of performing static timing analysis based on the actual resistance-capacitance parasitic parameters (RC parameters) of each timing path in the digital circuit. At this time, the latest parasitic parameters after routing changes can be used to analyze each timing path one by one to check whether there are timing abnormal (such as setup or hold violation) paths. If the analysis results show that there are still abnormal timing paths, continue with routing optimization and adjustment, and repeat the above check and analysis process. These steps will be carried out in a loop until all timing paths meet the design requirements and there are no abnormal timing paths, thus ensuring the timing performance and design correctness of the final digital circuit.

[0113] Based on the technical solution proposed in this application, the correction efficiency of digital circuit engineering can be significantly improved. Specifically, first, after the wiring is completed, static timing analysis is performed based on the resistance-capacitance parasitic parameters of the actual circuit, and more realistic and accurate global timing information can be obtained, avoiding the timing analysis deviation caused by inaccurate parameters before wiring in the traditional ECO method, thereby improving the accuracy of timing violation detection. Secondly, by changing the logic units included in the abnormal timing path and combining means such as incremental wiring, only the local wiring is quickly changed without re-performing global placement and routing, which can greatly shorten the correction cycle of digital circuit engineering and improve the iteration efficiency of digital circuits. In addition, this application checks the digital circuit after wiring changes in real time through a design rule checking engine to ensure that wiring violations can be detected and eliminated in time after each local correction, which can ensure the reliability and design quality of the digital circuit correction process. Through cyclic iterative analysis and correction until there are no abnormalities in all timing paths, the timing performance of the final digital circuit can be further ensured to meet the design requirements.

[0114] At the same time, this application makes full use of the global state information after wiring completion and the EVA value of the three-dimensional wiring grid for local incremental wiring, improving the accuracy and efficiency of the wiring algorithm and reducing the global impact caused by local modifications. It can be seen that this application not only improves the accuracy and speed of correction, but also optimizes the usability and applicability of EDA tools, providing a more efficient and reliable ECO correction means for chip backend design, and greatly improving the overall correction efficiency and design quality of digital circuit engineering.

[0115] The following introduces the device embodiments of this application, which can be used to execute the digital circuit engineering correction method in the above embodiments of this application. For the details not disclosed in the device embodiments of this application, please refer to the embodiments of the digital circuit engineering correction method above in this application.

[0116] See Figure 4 , which shows the block diagram of the digital circuit engineering correction device in the embodiments of this application.

[0117] As Figure 4 shown, the digital circuit engineering correction device 400 according to the embodiments of this application includes: an analysis unit 401, a screening unit 402, a change unit 403, and an inspection unit 404.

[0118] Among them, an analysis unit 401 is configured to perform static timing analysis based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit after the digital circuit routing is completed, so as to obtain the global timing information of each timing path; a screening unit 402 is configured to screen out abnormal timing paths including abnormal logic units from the digital circuit based on the global timing information of each timing path; a change unit 403 is configured to perform logic unit change on the abnormal timing paths including abnormal logic units, and perform routing change on the digital circuit after the logic unit change; an inspection unit 404 is configured to, if there is no routing violation in the digital circuit after the routing change is inspected by a design rule inspection engine, return to execute the step of performing static timing analysis based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit until there are no abnormal timing paths in the digital circuit.

[0119] In some embodiments of the present application, based on the foregoing solution, the analysis unit 401 is configured to: based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit, call a static timing analysis engine to calculate the timing parameter values of each logic unit in each timing path in at least one dimension, as the global timing information of each timing path.

[0120] In some embodiments of the present application, based on the foregoing solution, the screening unit 402 is configured to: obtain a preset timing parameter threshold; if the timing parameter value of any logic unit in the digital circuit satisfies a preset size relationship with the timing parameter threshold, determine the any logic unit as an abnormal logic unit, and determine the timing path to which the abnormal logic unit belongs as an abnormal timing path.

[0121] In some embodiments of the present application, based on the foregoing solution, the change unit 403 is configured to: obtain a pre-constructed abnormal list and an alternative list, where the abnormal list is used to record the abnormal timing paths screened out from the digital circuit and the abnormal logic units in the abnormal timing paths, and the alternative list is used to record logic units of different configurable unit types, and the unit types include functional units and filling units; select a target abnormal timing path to be changed and a target abnormal logic unit in the target abnormal timing path from the abnormal list, determine the target change type of the logic unit, and select a logic unit to be placed from the alternative list; where the change type of the logic unit at least includes adding a logic unit, replacing a logic unit, and deleting a logic unit; based on the logic unit to be placed and the target abnormal logic unit, perform logic unit change on the target abnormal timing path according to the target change type.

[0122] In some embodiments of the present application, based on the foregoing solution, if the target change type is to add a logic unit, the logic unit to be placed is a first functional unit, and the change unit 403 is configured to: place the first functional unit in a target site area on the target abnormal timing path close to the target abnormal logic unit, where a site is a basic position unit on the timing path.

[0123] In some embodiments of the present application, based on the foregoing solution, the change unit 403 is configured to: determine logic units within a preset radius range centered on the target abnormal logic unit on the target abnormal timing path to obtain a logic unit list; traverse the sizes of the filling units in the logic unit list in a set traversal order; when the size of any one filling unit is greater than or equal to the size of the first functional unit, or when the sum of the sizes of any group of sequentially adjacent filling units is greater than or equal to the size of the first functional unit, determine the site area occupied by the any one filling unit or the site area occupied by the any group of sequentially adjacent filling units as the target site area; delete the filling units in the target site area, and place the first functional unit in the target site area.

[0124] In some embodiments of the present application, based on the foregoing solution, the change unit 403 is configured to: if the size of the target site area is greater than the size of the first functional unit, based on the size difference between the size of the target site area and the size of the first functional unit, find one or more filling units from the alternative list according to a set search logic; combine the first functional unit with the one or more filling units to obtain a combined unit, and the size of the target site area is equal to the size of the combined unit; place the combined unit in the target site area.

[0125] In some embodiments of the present application, based on the foregoing solution, the change unit 403 is further configured to: if the first functional unit is a buffer unit, calculate a radius threshold based on a signal integrity analysis engine; determine the preset radius, and the preset radius is greater than or equal to the radius threshold.

[0126] In some embodiments of the present application, based on the foregoing solution, if the target change type is to replace a logic unit, the logic unit to be placed is a second functional unit adapted to the size of the target abnormal logic unit, and the change unit 403 is configured to: delete the target abnormal logic unit, and place the second functional unit in the site area occupied by the target abnormal logic unit.

[0127] In some embodiments of the present application, based on the foregoing solution, if the target change type is to delete a logic unit, the logic unit to be placed is a filling unit or a combination of filling units that is dimensionally adapted to the target abnormal logic unit, and the change unit 403 is configured to: delete the target abnormal logic unit, and place a filling unit or a combination of filling units that is dimensionally adapted to the target abnormal logic unit in the site area occupied by the target abnormal logic unit.

[0128] In some embodiments of the present application, based on the foregoing solution, the change unit 403 is configured to: perform local wiring change on the digital circuit after the logic unit change; or, perform global wiring change on the digital circuit after the logic unit change.

[0129] In some embodiments of the present application, based on the foregoing solution, the change unit 403 is configured to: take a memory snapshot of the wiring data of other timing paths except the abnormal timing path, and clear the wiring data of the abnormal timing path; obtain the wiring data of the other timing paths in the memory, and based on the wiring data of the other timing paths, call a three-dimensional wiring algorithm to re-wire the abnormal timing path.

[0130] Based on the same inventive concept, an embodiment of the present application provides a computer program product, the computer program product includes computer instructions, the computer instructions are stored in a computer-readable storage medium, and are adapted to be read and executed by a processor, so that a computer device having the processor executes to implement the operations performed by the digital circuit engineering correction method as described above.

[0131] Based on the same inventive concept, an embodiment of the present application provides a computer-readable storage medium, in which at least one computer program instruction is stored, and the at least one computer program instruction is loaded and executed by a processor to implement the operations performed by the digital circuit engineering correction method as described above.

[0132] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, refer to Figure 5 , which shows a schematic structural diagram of the electronic device in the embodiment of the present application. The electronic device includes one or more memories 504, one or more processors 502, and at least one computer program (computer program instruction) stored on the memory 504 and executable on the processor 502. When the processor 502 executes the computer program, it implements the digital circuit engineering correction method as described above.

[0133] Among them, in Figure 5Among them, a bus architecture (represented by bus 500), bus 500 may include any number of interconnected buses and bridges. Bus 500 will link together various circuits including one or more processors represented by processor 502 and a memory represented by memory 504. Bus 500 may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, etc., which are well known in the art and thus will not be further described herein. Bus interface 505 provides an interface between bus 500 and receiver 501 and transmitter 503. Receiver 501 and transmitter 503 may be the same element, i.e., a transceiver, providing a unit for communicating with various other devices over a transmission medium. Processor 502 is responsible for managing bus 500 and general processing, while memory 504 may be used to store data used by processor 502 when performing operations.

[0134] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope and spirit of this application. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination of these. In addition, each functional unit may be integrated in one processing unit, or each unit may exist physically separately, or two or more units may be integrated in one unit.

[0135] In several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are merely illustrative. For example, the division of the units can be a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of units or modules can be in electrical or other forms.

[0136] The units described as separate components may or may not be physically separated. The components serving as control devices may or may not be physical units, that is, they may be located in one place or distributed to multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0137] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The foregoing storage medium includes: various media such as USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs that can store computer program instructions.

[0138] The foregoing are only embodiments of this application and are not intended to limit this application. For those skilled in the art, this application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims

1. A method for correcting digital circuit engineering, characterized in that The method includes: After the routing of the digital circuit is completed, static timing analysis is performed based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit to obtain the global timing information of each timing path; Based on the global timing information of each timing path, abnormal timing paths containing abnormal logic units are screened out from the digital circuit; Logical unit changes are made to the abnormal timing paths containing abnormal logic units, and routing changes are made to the digital circuit after the logical unit changes; If there are no routing violations in the digital circuit after the routing changes are checked by the design rule check engine, return to execute the step of performing static timing analysis based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit until there are no abnormal timing paths in the digital circuit.

2. The method according to claim 1, characterized in that, The performing static timing analysis based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit to obtain the global timing information of each timing path includes: Based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit, a static timing analysis engine is called to calculate the timing parameter values of each logic unit in each timing path in at least one dimension as the global timing information of each timing path.

3. The method according to claim 2, wherein The screening out abnormal timing paths containing abnormal logic units from the digital circuit based on the global timing information of each timing path includes: Obtaining a preset timing parameter threshold; If the timing parameter value of any logic unit in the digital circuit satisfies a preset size relationship with the timing parameter threshold, then the any logic unit is determined as an abnormal logic unit, and the timing path to which the abnormal logic unit belongs is determined as an abnormal timing path.

4. The method according to claim 3, wherein The making logical unit changes to the abnormal timing paths containing abnormal logic units includes: Obtaining a pre-constructed abnormal list and an alternative list, where the abnormal list is used to record the abnormal timing paths screened out from the digital circuit and the abnormal logic units in the abnormal timing paths, and the alternative list is used to record configurable logic units of different unit types, and the unit types include functional units and filling units; Selecting a target abnormal timing path to be changed and a target abnormal logic unit in the target abnormal timing path from the abnormal list, determining the target change type of the logic unit, and selecting a logic unit to be placed from the alternative list; wherein, the change types of the logic unit at least include adding a logic unit, replacing a logic unit, and deleting a logic unit; Based on the logic unit to be placed and the target abnormal logic unit, the logical unit change is made to the target abnormal timing path according to the target change type.

5. The method according to claim 4, wherein If the target change type is adding a logic unit, the logic unit to be placed is a first functional unit, and the making logical unit changes to the target abnormal timing path includes: Placing the first functional unit in a target site area on the target abnormal timing path close to the target abnormal logic unit, where the site is a basic position unit on the timing path.

6. The method according to claim 5, wherein Placing the first functional unit on a target site area on the target abnormal timing path close to the target abnormal logic unit includes: Determining logic units within a preset radius centered on the target abnormal logic unit on the target abnormal timing path to obtain a logic unit list; Sequentially traversing the sizes of the filling units in the logic unit list according to a set traversal order; When the size of any one filling unit traversed is greater than or equal to the size of the first functional unit, or when the sum of the sizes of any group of sequentially adjacent filling units is greater than or equal to the size of the first functional unit, determining the site area occupied by the any one filling unit or the site area occupied by the any group of sequentially adjacent filling units as the target site area; Deleting the filling units in the target site area and placing the first functional unit in the target site area.

7. The method according to claim 6, characterized in that, Placing the first functional unit in the target site area includes: If the size of the target site area is greater than the size of the first functional unit, based on the size difference between the size of the target site area and the size of the first functional unit, searching for one or more filling units from the alternative list according to a set search logic; Combining the first functional unit with the one or more filling units to obtain a combined unit, and the size of the target site area is equal to the size of the combined unit; Placing the combined unit in the target site area.

8. The method according to claim 6, characterized in that The method further includes: If the first functional unit is a buffer unit, calculating a radius threshold based on a signal integrity analysis engine; Determining the preset radius, and the preset radius is greater than or equal to the radius threshold.

9. The method according to claim 5, wherein If the target change type is to replace a logic unit, the logic unit to be placed is a second functional unit adapted to the size of the target abnormal logic unit. Changing the logic unit on the target abnormal timing path includes: Deleting the target abnormal logic unit and placing the second functional unit in the site area occupied by the target abnormal logic unit.

10. The method according to claim 5, wherein If the target change type is to delete a logic unit, the logic unit to be placed is a filling unit or a combination of filling units adapted to the size of the target abnormal logic unit. Changing the logic unit on the target abnormal timing path includes: Deleting the target abnormal logic unit and placing a filling unit or a combination of filling units adapted to the size of the target abnormal logic unit in the site area occupied by the target abnormal logic unit.

11. The method according to claim 2, wherein Changing the wiring of the digital circuit after the logic unit change includes: Performing a local wiring change on the digital circuit after the logic unit change; or, Performing a global wiring change on the digital circuit after the logic unit change.

12. The method according to claim 11, characterized in that, Performing a local wiring change on the digital circuit after the logic unit change includes: Taking a memory snapshot of the wiring data of other timing paths except the abnormal timing path and clearing the wiring data of the abnormal timing path; Obtain the routing data of the other timing paths in the memory, and based on the routing data of the other timing paths, call a three-dimensional routing algorithm to re-route the abnormal timing path.

13. A digital circuit engineering correction device, characterized in that, The device includes: An analysis unit, configured to perform static timing analysis based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit after the routing of the digital circuit is completed, to obtain the global timing information of each timing path; A screening unit, configured to screen out abnormal timing paths including abnormal logic units from the digital circuit based on the global timing information of each timing path; A change unit, configured to perform logic unit change on the abnormal timing paths including abnormal logic units, and perform routing change on the digital circuit after the logic unit change; An inspection unit, configured to, if there is no routing violation in the digital circuit after the routing change is inspected by a design rule checking engine, return to execute the step of performing static timing analysis based on the actual circuit resistance-capacitance parasitic parameters of each timing path in the digital circuit until there are no abnormal timing paths in the digital circuit.

14. A computer program product, characterized in that, The computer program product includes computer instructions, which are stored in a computer-readable storage medium and are adapted to be read and executed by a processor, so that a computer device having the processor executes the method according to any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that, At least one program code is stored in the computer-readable storage medium, and the at least one program code is loaded and executed by a processor to implement the operations performed by the method according to any one of claims 1 to 12.

16. An electronic device, characterized in that, The electronic device includes one or more processors and one or more memories, and at least one program code is stored in the one or more memories, and the at least one program code is loaded and executed by the one or more processors to implement the method according to any one of claims 1 to 12.

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