Data updating method and device and electronic equipment

Abstract

The invention provides a data updating method which comprises the following steps: in response to a change in a translation lookaside buffer meeting a trigger condition, acquiring a plurality of virtual address ranges associated with the change; according to the plurality of virtual address ranges, a target update range is generated and stored in a target storage space, the target update range at least comprises each virtual address range, and the target storage space can be accessed by a plurality of target processors; and a target instruction is sent, the target instruction is used for indicating each target processor to interrupt the task being executed, the target update range is obtained from the target storage space, and the translation lookaside buffer corresponding to the target processor is updated according to the target update range.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and more particularly, to a data update method, apparatus, and electronic device. Background Art

[0002] In a multi-core server system, to improve the access efficiency of virtual address to physical address mapping, a processor is usually configured with a translation lookaside buffer (TLB) for caching page table information and reducing main memory access latency. When the page table in the system is updated, the TLB content in each processor's local area needs to be refreshed in a timely manner to ensure the consistency of address mapping. The prior art usually adopts an inter-processor interrupt mechanism, where the processor that detects the change sends interrupts to other processors one by one to notify them to refresh the TLB for a specific virtual address range. However, as the scale of the multi-core system continues to expand, especially in scenarios where the number of cores reaches hundreds, the method of separately sending interrupts for each changed address range in the prior art has led to a large number of interrupt surges, greatly increasing the system bus pressure and the overhead of cache coherence maintenance, further resulting in an increase in scheduling latency and a decrease in system response capabilities. Under extreme loads, frequent interrupt processing and resource contention may also cause soft lock-up phenomena, seriously affecting system stability and usage efficiency. Summary of the Invention

[0003] In view of this, the present disclosure provides a data update method, apparatus, and electronic device.

[0004] One aspect of the present disclosure provides a data update method, including: in response to a change in the translation lookaside buffer satisfying a trigger condition, obtaining a plurality of virtual address ranges associated with the change; generating a target update range according to the plurality of virtual address ranges and storing the target update range in a target storage space, the target update range at least including each virtual address range, and the target storage space being accessible by a plurality of target processors; sending a target instruction, the target instruction being used to instruct each target processor to interrupt the task being executed and obtain the target update range from the target storage space, and updating the translation lookaside buffer corresponding to the target processor according to the target update range.

[0005] According to an embodiment of the present disclosure, in response to a change in the translation lookaside buffer satisfying a trigger condition, obtaining a plurality of virtual address ranges associated with the change includes: in response to the change being a change brought about by a process context switch, obtaining, in the translation lookaside buffer after the switch, a plurality of virtual address ranges associated with the change.

[0006] According to an embodiment of the present disclosure, in response to a change in the translation lookaside buffer satisfying a trigger condition, obtaining a plurality of virtual address ranges associated with the change includes: in response to a change occurring in the translation lookaside buffer within a preset time window, obtaining a plurality of virtual address ranges associated with each change.

[0007] According to an embodiment of the present disclosure, in response to a change in the translation lookaside buffer satisfying a trigger condition, a plurality of virtual address ranges associated with the change are obtained, including: in response to the number of changes occurring within a preset time range being greater than or equal to a preset threshold, a plurality of virtual address ranges associated with each change within the preset time range are obtained.

[0008] According to an embodiment of the present disclosure, generating a target update range includes:

[0009] In response to each virtual address range being continuous, each virtual address range is merged to generate a target update range; or, in response to there being discontinuous address ranges among each virtual address range, a target update range is generated according to the minimum virtual address and the maximum virtual address in each virtual address range.

[0010] According to an embodiment of the present disclosure, the data update method further includes: obtaining target load information, where the target load information characterizes the load level of an instruction transmission management module for transmitting management target instructions; in response to the target load information being greater than or equal to a load threshold, a plurality of virtual address ranges associated with changes occurring in the translation lookaside buffer are obtained.

[0011] According to an embodiment of the present disclosure, the target instruction includes execution priority information, and the data update method further includes: determining content priority information according to at least one of a change range corresponding to the change, change urgency, change deferability, and change security; sending a target instruction, including: generating and sending a target instruction according to the content priority information and the target update range, where the execution priority information of the target instruction is generated according to the content priority information, and the execution priority information is used to indicate the order in which the target processor executes the target instruction.

[0012] According to an embodiment of the present disclosure, sending a target instruction includes: in response to the processor being able to communicate with a first target processor based on a cache coherence protocol, sending the target instruction to the first target processor, so that the first target processor updates data within the target update range in the corresponding translation lookaside buffer through the cache coherence protocol.

[0013] Another aspect of the present disclosure provides a data update device, including: a first acquisition module, configured to acquire a plurality of virtual address ranges associated with a change in response to the change in the translation lookaside buffer satisfying a trigger condition; a first generation module, configured to generate a target update range according to the plurality of virtual address ranges and store the target update range in a target storage space, where the target update range at least includes each virtual address range, and the target storage space can be accessed by a plurality of target processors; and a first sending module, configured to send a target instruction, where the target instruction is used to instruct each target processor to interrupt a task being executed, obtain the target update range from the target storage space, and update the translation lookaside buffer corresponding to the target processor according to the target update range.

[0014] Another aspect of the present disclosure provides an electronic device, including: at least one processor; and a memory connected to the at least one processor; where the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the data update method according to any one of the foregoing embodiments.

[0015] Another aspect of the present disclosure provides a computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the data update method according to any one of the foregoing embodiments.

[0016] Another aspect of the present disclosure provides a computer program product, including computer programs / instructions, characterized in that when the computer programs / instructions are executed by a processor, the operations of the data update method according to any one of the foregoing embodiments are implemented. Description of the Drawings

[0017] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0018] Figure 1 Schematically shows a flowchart of the data update method according to an embodiment of the present disclosure;

[0019] Figure 2 Schematically shows another flowchart of the data update method according to an embodiment of the present disclosure;

[0020] Figure 3 Schematically shows another flowchart of the data update method according to an embodiment of the present disclosure;

[0021] Figure 4 Schematically shows another flowchart of the data update method according to an embodiment of the present disclosure;

[0022] Figure 5 Schematically shows another flowchart of the data update method according to an embodiment of the present disclosure;

[0023] Figure 6 Schematically shows a flowchart of obtaining a plurality of virtual address ranges in a data update method according to an embodiment of the present disclosure;

[0024] Figure 7 Schematically shows another flowchart of a data update method according to an embodiment of the present disclosure;

[0025] Figure 8 Schematically shows another flowchart of a data update method according to an embodiment of the present disclosure;

[0026] Figure 9 Schematically shows a TLB refreshing method;

[0027] Figure 10 Schematically shows a TLB refreshing method according to an embodiment of the present disclosure;

[0028] [[ID=2,2]] Figure 11 Schematically shows a block diagram of a data update apparatus according to an embodiment of the present disclosure; and

[0029] Figure 12 Schematically shows a block diagram of an electronic device suitable for implementing the method described above according to an embodiment of the present disclosure. Detailed Embodiments

[0030] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0031] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0033] In the case of using expressions such as "at least one of A, B, and C", generally, it should be interpreted according to the meaning that those skilled in the art usually understand this expression (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0034] In the embodiments of the present disclosure, in aspects such as the collection, update, analysis, processing, use, transmission, provision, disclosure, storage, etc. of the involved data (for example, including but not limited to user personal information), they all comply with the provisions of relevant laws and regulations, are used for legal purposes, and do not violate public order and good customs. In particular, necessary measures are taken for user personal information to prevent illegal access to user personal information data and to safeguard user personal information security, network security, and national security.

[0035] The embodiments of the present disclosure provide a data update method, including: in response to changes in the translation lookaside buffer satisfying a trigger condition, obtaining a plurality of virtual address ranges associated with the changes; generating a target update range according to the plurality of virtual address ranges and storing it in a target storage space, the target update range at least including each virtual address range, and the target storage space can be accessed by a plurality of target processors; sending a target instruction, the target instruction being used to instruct each target processor to interrupt the task being executed and obtain the target update range from the target storage space, and update the translation lookaside buffer corresponding to the target processor according to the target update range.

[0036] Figure 1 A flowchart of the data update method according to the embodiments of the present disclosure is schematically shown.

[0037] As Figure 1 shown, the data update method may at least include operations S110 to S130.

[0038] In operation S110, in response to changes in the translation lookaside buffer satisfying a trigger condition, obtain a plurality of virtual address ranges associated with the changes.

[0039] The translation lookaside buffer (TLB) is a cache structure inside the processor used to cache the mapping relationship between virtual addresses and physical addresses, and its function is to accelerate address conversion and reduce the overhead of accessing the page table in the main memory.

[0040] The changes in the translation lookaside buffer satisfying the trigger condition means that when a specific event occurs, resulting in a change in the mapping relationship between virtual addresses and physical addresses in the TLB, the system detects that the mapping information stored in the TLB is no longer valid, triggering the refresh mechanism.

[0041] Multiple virtual address ranges associated with a change refer to multiple logical address segments that are affected by the current page table update or address mapping change and need to be flushed or invalidated in the TLB. They may be a set of continuous or discontinuous intervals.

[0042] Multiple virtual address ranges associated with a change can be collected in batches for the current change by scanning the address change record table maintained by the kernel or based on the address mapping changes generated before and after the change.

[0043] For example, during a process switch, when the operating system performs a context switch, the virtual memory of the current process is released, and the new process will apply for a new virtual memory area. During this process, the operating system will first mark all virtual address ranges cached in the TLB of the old process as expired or invalid. These invalid virtual address ranges need to be cleared from the TLB of the target processor. When the operating system accesses the virtual address of the new process and misses it in the TLB, the CPU then accesses the page table in memory to find the corresponding virtual address and physical address mapping relationship and loads this mapping into the TLB.

[0044] In operation S120, a target update range is generated based on multiple virtual address ranges and stored in a target storage space. The target update range includes at least each virtual address range, and the target storage space can be accessed by multiple target processors.

[0045] The target update range can refer to a total refresh area formed by integrating multiple virtual address ranges to be refreshed, which is used to guide each processor to locally refresh the TLB content. Specifically, when generating data for refreshing the translation lookaside buffer, the formed target update range needs to cover each virtual address change area collected. That is to say, regardless of whether the individual virtual address ranges are continuous, the target update range should include all virtual address intervals involved in the change to ensure that all mapping relationships to be refreshed can be correctly processed.

[0046] The target processor can refer to a processor core in a multi-core system that needs to refresh its local TLB according to the target update range to maintain address mapping consistency.

[0047] The target storage space can refer to a shared storage area for temporarily storing the data of the target update range, usually set in the high-speed memory or shared cache in a multi-core system for access by each target processor.

[0048] The target storage space can be accessed by multiple target processors, which means that all processors requiring synchronization can read the target update range in this storage space without passing the complete data content through interrupt messages, thus reducing the system interrupt communication load. For example, the target storage space can be located in a high-speed shared memory area local to the node, and through a lock mechanism or version control mechanism, the consistency and reliability during concurrent reading by multiple processors are ensured.

[0049] The target update range includes at least each virtual address range. When generating data for refreshing the translation lookaside buffer, the formed target update range needs to cover each virtual address change area collected. That is to say, regardless of whether the virtual address ranges are continuous or not, the target update range should include all virtual address intervals involved in the changes, so as to ensure that all mapping relationships to be refreshed can be correctly processed.

[0050] For example, if the multiple virtual address ranges collected are 0x1000–0x1FFF, 0x3000–0x3FFF, and 0x5000–0x5FFF respectively, and there are intervals among them in the address space. When generating the target update range, the minimum virtual address 0x1000 and the maximum virtual address 0x5FFF can be extracted to form a coverage interval 0x1000–0x5FFF as the target update range. This target update range includes at least the original three virtual address ranges, ensuring that no address mapping to be updated is missed during the refresh, and at the same time covering all relevant changes through one refresh operation, improving the refresh efficiency and reducing the system overhead.

[0051] In operation S130, a target instruction is sent. The target instruction is used to instruct each target processor to interrupt the task being executed and obtain the target update range from the target storage space, and update the translation lookaside buffer corresponding to the target processor according to the target update range.

[0052] The target instruction refers to a control instruction sent by the source processor and used to trigger the target processor to perform a specific operation (i.e., TLB refresh). It does not carry specific refresh data itself, but only contains the notification information of the refresh task.

[0053] Specifically, the target instruction can adopt the standard IPI (Inter-Processor Interrupt) format, set appropriate interrupt vector numbers and priorities to ensure that the target processor responds in a timely manner and completes the refresh operation according to the data in the shared storage.

[0054] For example, after the source processor completes the integration of the target update range, it broadcasts a flush instruction to all target processors through a single IPI instruction. After receiving the instruction, the target processor interrupts the current task, accesses the storage location in the shared area, and flushes the corresponding TLB mapping relationship according to the target update range pre-stored in the shared area.

[0055] According to the embodiments of the present disclosure, by integrating multiple virtual address ranges when a trigger condition is met and storing them in a shared storage space accessible by multiple processors, and cooperating with sending a single target instruction (IPI interrupt) to notify all target processors to perform a flush, the problems in the conventional technology of frequently generating a large number of IPI interrupts, causing system bus conflicts, increasing cache coherence overhead, and rising scheduling latency are effectively avoided. Especially in the context of the continuous expansion of the multi-core scale, the global interrupt burden is significantly reduced, and the overall concurrent processing ability and stability of the system are improved.

[0056] Figure 2 Another flowchart of the data update method according to the embodiments of the present disclosure is schematically shown.

[0057] As Figure 2 shown, on the basis of the foregoing embodiments, S110 may include operation S210.

[0058] In operation S210, in response to the changes brought about by the process context switch, multiple virtual address ranges associated with the changes in the translation lookaside buffer after the switch are obtained.

[0059] The changes brought about by the process context switch refer to when the operating system performs a process switch, the current processor core needs to remove the page table mapping relationship of the old process from the translation lookaside buffer and load the page table mapping corresponding to the new process at the same time. During this process, due to the overall change in the mapping relationship from the virtual address to the physical address, the content in the translation lookaside buffer needs to be flushed or rebuilt, resulting in changes related to multiple virtual address ranges.

[0060] When a specific event of the process context switch is detected, the system will actively identify multiple virtual address ranges changed due to the switch, including the virtual address range occupied by the old process and the new virtual address range applied for and mapped by the new process. By collecting these virtual address ranges related to the changes at one time, the multiple virtual addresses related to the changes are subsequently integrated into a single virtual address.

[0061] For example, when performing a process switch, the virtual address range occupied by the old process is 0x1000–0x2FFF, and the virtual address range used after the new process is loaded is 0x4000–0x5FFF. The system marks 0x1000–0x2FFF as an invalid area during the switch, and at the same time uses 0x4000–0x5FFF as the newly loaded valid area. Subsequently, multiple virtual address ranges occupied by the old process collected will be uniformly generated into a refresh target to notify other processors to refresh their respective TLBs.

[0062] According to the embodiments of the present disclosure, using the process context switch as a trigger condition can capture, at the first moment when the mapping relationship actually undergoes a global change, the large-scale virtual address mapping changes caused by the process switch, and further the changes in the content of the translation lookaside buffer, and uniformly process the virtual addresses corresponding to these changes, avoiding access errors or consistency risks caused by delayed refreshing.

[0063] Figure 3 Another flowchart of the data update method according to the embodiments of the present disclosure is schematically shown.

[0064] As Figure 3 shown, on the basis of the foregoing embodiments, S110 may include operation S310.

[0065] In operation S310, in response to changes occurring in the translation lookaside buffer within a preset time window, obtain multiple virtual address ranges associated with each change.

[0066] The preset time window may refer to a preset time period of a fixed duration, such as 2 seconds, 5 seconds, or other configurable time periods, and all virtual address mapping changes occurring in the translation lookaside buffer (TLB) are counted within this time period. The preset time window can be flexibly adjusted according to the processor load, system configuration, or application scenario to balance the refresh frequency and system overhead.

[0067] During each preset time window, continuously monitor the state change of the TLB. When a change event is detected, record the corresponding virtual address range. When the current time window ends, uniformly collect all the virtual address ranges recorded within this time window and use them as the basis for subsequent update processing. Through this time window aggregation mechanism, the system interruption overhead caused by repeatedly triggering the refresh operation due to single or small-batch changes is effectively avoided.

[0068] Specifically, for example, assume that the preset time window is set to 2 seconds. Within these 2 seconds, there are several virtual address mapping update events in the CPU, which respectively involve virtual address ranges A (0x1000 - 0x1FFF), B (0x3000 - 0x3FFF), and C (0x5000 - 0x5FFF). At the end moment when the time window reaches, the three virtual address ranges A, B, and C are collected uniformly, and a target update range is generated based on these ranges, and then a total refresh instruction (IPI) is sent once to notify each target processor to perform a TLB refresh operation.

[0069] Compared with the traditional method of sending an IPI every time there is a change, this method only sends an IPI once within each time window. By setting the preset time window as the trigger condition, it can detect and integrate the virtual address mapping changes occurring in the translation lookaside buffer in a fixed periodic manner, avoiding the problems of frequent interruptions, resource fragmentation, and sudden increase in system scheduling pressure caused by immediate triggering of refreshes due to individual change events. Using the time window method can make the refresh operation predictable and stable, facilitating the system to perform resource scheduling and load balancing according to the established rhythm, thereby further reducing the overhead of system bus contention and cache coherence maintenance.

[0070] Figure 4 Another flowchart of the data update method according to an embodiment of the present disclosure is schematically shown.

[0071] As Figure 4 shown, on the basis of the foregoing embodiment, S110 may include operation S410.

[0072] In operation S410, in response to the number of changes occurring within a preset time range being greater than or equal to a preset threshold, a plurality of virtual address ranges associated with each change within the preset time range are obtained. [[ID=,17]]

[0073] The preset time range refers to a fixed-duration time period set by the system, such as 1 second, 500 milliseconds, or other appropriate time intervals, for counting the number of virtual address mapping changes occurring in the translation lookaside buffer (TLB) within this time period. The preset time range can be flexibly configured according to system load conditions, application scenario requirements, or processor performance parameters.

[0074] Within the preset time range, the system monitors the occurrence times of TLB change events in real time. When the cumulative number of changes reaches or exceeds the preset threshold (such as 100 times, 200 times, etc.), the system immediately starts the virtual address range collection process, collects the virtual address ranges corresponding to all change events within this time range, as the basis for generating the target update range subsequently.

[0075] For example, assume that the preset time range is set to 1 second and the preset threshold is set to 100 times. When there are more than 100 virtual address mapping changes in the TLB within 1 second, the system immediately collects the virtual address ranges corresponding to each change within this 1 second. For example, address ranges X (0x2000 - 0x2FFF), Y (0x4000 - 0x4FFF), and Z (0x6000 - 0x6FFF). After integrating these address ranges, a target update range is generated, and a combined flush instruction (IPI) is sent for synchronous update. Conversely, if the number of changes does not reach the threshold within the preset time range, the IPI instructions can be sent individually in response to each change in the traditional manner to ensure the refresh accuracy and timeliness.

[0076] According to an embodiment of the present disclosure, the data update method may further include: in response to the number of changes occurring within the preset time range being less than the preset threshold, saving the virtual address ranges corresponding to each change. For each virtual address range with one corresponding change, a target instruction is sent to instruct each target processor to interrupt the task being executed and obtain the virtual address range corresponding to each change from the target storage space. According to the virtual address ranges corresponding to each change, the translation lookaside buffer corresponding to the target processor is updated.

[0077] According to an embodiment of the present disclosure, by using the number of changes occurring within the preset time range reaching the preset threshold as a trigger condition, the refresh strategy can be flexibly adjusted according to the actual activity of the changes. In a high-change-density scenario, the number of interrupts can be effectively reduced, the refresh tasks can be processed in batches, the bus load and interrupt handling overhead can be reduced, and the concurrent processing performance of the multi-core system can be improved. At the same time, in a scenario with a low change frequency, each change is still promptly responded to for refreshing to ensure system data consistency and high responsiveness. Thus, both the refresh efficiency and system stability are taken into account in different load environments.

[0078] According to an embodiment of the present disclosure, it can be combined with Figures 2 to 4 any one or more of the embodiments shown as a trigger condition. For example, when a process context switch is detected ( Figure 2 example), it can be combined with determining whether there is a virtual address mapping change within a preset time window ( Figure 3 example), and counting whether the number of changes within the preset time range reaches the threshold ( Figure 4 example). Meeting any one of these conditions can trigger the operation of obtaining and integrating the virtual address range. Further, different priorities can be set according to different conditions. For example, if a process switch is detected, immediate refresh is prioritized; if there are only changes within the time window, the refresh is delayed, thereby implementing a more flexible and efficient refresh control strategy. By combining different trigger conditions, the system can dynamically adjust the refresh trigger timing according to the actual operating conditions, ensuring both data consistency and optimizing the interrupt overhead and system load distribution.

[0079] Figure 5 Schematically shows another flowchart of the data update method according to an embodiment of the present disclosure.

[0080] As Figure 5 shown, on the basis of the foregoing embodiment, S120 may include operation S510 or S520.

[0081] In operation S510, in response to each virtual address range being continuous, each virtual address range is merged to generate a target update range.

[0082] When it is detected that multiple virtual address ranges are arranged continuously, that is, the end address of the previous virtual address range is adjacent to or overlaps with the start address of the next virtual address range, these continuous virtual address ranges are directly merged into a single larger address range as the target update range.

[0083] Specifically, for example, assume that in a change, the detected virtual address ranges are: 0x1000 - 0x1FFF, 0x2000 - 0x2FFF, 0x3000 - 0x3FFF. Since these ranges are continuously arranged in the address space, they can be merged into an overall target update range of 0x1000 - 0x3FFF for unified refresh processing.

[0084] In operation S520, in response to discontinuous address ranges existing in each virtual address range, a target update range is generated according to the minimum virtual address and the maximum virtual address in each virtual address range.

[0085] When it is detected that there is a discontinuous relationship between multiple virtual address ranges, that is, there is an interval or overlap between the address ranges that is not sufficient for direct merging, the minimum start address and the maximum end address in all changed virtual address ranges are extracted to generate a total enclosing target update range covering all changed ranges. Although this may include some addresses that have not actually changed, it can significantly reduce the number of refresh instructions sent and the processing steps in the refresh operation, improving the system refresh efficiency.

[0086] Specifically, for example, assume that the virtual address ranges involved in the change are: 0x1000 - 0x1FFF, 0x4000 - 0x4FFF, 0x8000 - 0x8FFF. Since there are large discontinuous intervals between these address ranges, a new target update range of 0x1000 - 0x8FFF is generated according to the minimum start address of 0x1000 and the maximum end address of 0x8FFF for subsequent TLB refresh operations.

[0087] Figure 6The flowchart of obtaining multiple virtual address ranges in the data update method according to an embodiment of the present disclosure is schematically shown.

[0088] As Figure 6 shown, on the basis of the foregoing embodiment, the data update method may further include operations S610 to S620.

[0089] In operation S610, target load information is obtained, and the target load information characterizes the load level of the instruction transmission management module for transmitting management target instructions.

[0090] The instruction transmission management module is used to manage target instructions (such as IPI interrupt instructions) sent between processor cores through a bus, including functions such as instruction generation, scheduling, queue management, and transmission control. This module can monitor and optimize the usage of interrupt resources to ensure that interrupt transmission operations can still be effectively completed under high load conditions. Specifically, for example, the instruction transmission management module can be one or more of an interrupt scheduling unit, a bus controller, an interrupt queue management unit, a load detection unit, and a coherence maintenance module.

[0091] Among them, the interrupt scheduling unit is used to manage the interrupt scheduling between cores, determine the sending order and priority of interrupt instructions (such as IPI) in the system bus, and avoid interrupt conflicts and resource preemption; the bus controller is used to control and schedule the transmission of interrupt instructions in the interconnect bus (such as on-chip network NoC, QPI, CCIX, etc.), and manage bandwidth allocation and traffic control; the interrupt queue management unit is used to manage the queuing and dequeuing logic of pending interrupt instructions, monitor the backlog status of current interrupt requests, and dynamically adjust the sending rate of interrupt instructions according to a preset policy; the load detection unit is used to monitor various load metrics related to instruction transmission in real time, such as the length of the interrupt queue, bus utilization rate, cross-node access frequency, etc.; the coherence maintenance module is used to coordinate the transmission of interrupt instructions between cache coherence domains in a multi-node (NUMA) or multi-bus system to ensure cross-node data consistency.

[0092] The target load information, which is used to characterize the load level of the instruction transmission management module at a specific moment, may include but is not limited to: the current backlog length of the IPI processing interrupt queue, the bus bandwidth utilization rate for transmitting IPI interrupt instructions, the frequency or ratio of cross-node access, the average delay time in the instruction transmission link, and other various load metrics. By collecting and analyzing the target load information, the current tightness of the system communication resources can be dynamically evaluated.

[0093] Specifically, the current IPI processing interrupt queue length can be, for example, the number of IPIs waiting to be processed; the bus bandwidth utilization rate can be, for example, the real-time occupancy ratio of the system bus used for interrupt transmission; the cross-node access ratio can be, for example, in a NUMA (Non-Uniform Memory Access) architecture, the ratio of accessing non-local node resources; the average interrupt response latency can be, for example, the average time from sending an interrupt request to the completion of the interrupt response.

[0094] In operation S620, in response to the target load information being greater than or equal to the load threshold, obtain multiple virtual address ranges associated with the changes that occur in the translation lookaside buffer.

[0095] When the instruction transmission management module monitors that the target load information reaches or exceeds the preset load threshold, it determines that the system interrupt transmission resources are approaching saturation. At this time, the collection and integration process of the virtual address change range will be immediately started, and the changes will be processed in batches preferentially instead of being refreshed immediately for each change, so as to avoid further aggravating the communication load and causing interrupt congestion.

[0096] Specifically, for example, when it is detected that the bus bandwidth utilization rate continues to be higher than 80% and the IPI interrupt backlog exceeds 100, it is determined to be in a high-load state. Subsequently, collect all the virtual address change ranges that occur during the current detection period, integrate them into a total target update range, and then initiate a refresh operation uniformly, thereby effectively controlling the instruction sending frequency and bus resource occupancy.

[0097] Through the dynamic trigger mechanism based on the target load information, when the communication resources are tense, the processing strategy of virtual address changes can be actively adjusted, and the batch refresh method is adopted to reduce the number of interrupt requests and the bus transmission pressure, thereby avoiding resource contention, bus blocking or interrupt response timeout problems caused by excessive interrupt requests, and improving the communication stability and processing performance of the multi-core server system in a high-load environment.

[0098] Figure 7 Schematically shows another flowchart of the data update method according to an embodiment of the present disclosure.

[0099] According to an embodiment of the present disclosure, the target instruction includes execution priority information such as Figure 7 As shown, on the basis of the foregoing embodiment, the data update method may further include operation S710.

[0100] In operation S710, determine the content priority information according to at least one of the change range corresponding to the change, the change urgency, the change deferrability, and the change security.

[0101] Priority information, which is used to characterize the urgency and importance of each change event in the refresh operation, is a priority parameter dynamically determined according to the specific attributes of the change event. The priority information can be comprehensively calculated or set based on multi-dimensional features, including but not limited to the size of the change scope, the urgency of the change event, the delayability of the change, and the security requirements of the data involved in the change.

[0102] Determine the content priority information according to the change scope corresponding to the change. The larger the change scope, the more virtual address mappings are involved, and the wider the potential impact range, so the priority is correspondingly increased. For example, when the detected change scope covers the address space of the entire application (such as more than hundreds of megabytes), a higher content priority is assigned; while when only a small number of pages (such as 4KB - 8KB) are involved, a lower content priority is assigned.

[0103] Determine the content priority information according to the urgency of the change corresponding to the change. If the change involves operating system core resources (such as kernel page tables, system critical data structures) or the memory space of critical real-time tasks, it belongs to a high-urgency change and should be processed first. For example, when a change in kernel-mode memory (such as the address segment above 0xC0000000) is detected, this change is assigned a high-urgency priority. On the contrary, local changes in user-mode ordinary memory usually have a lower urgency.

[0104] Determine the content priority information according to the delayability of the change corresponding to the change. If the change can tolerate a certain delay (such as the release of non-critical user data, background batch processing memory changes), a lower priority can be assigned, allowing the system to process it when the load is low. For example, small batches of page releases during the C language free() or Java GC (garbage collection) process can be assigned a low priority to delay the refresh.

[0105] Determine the content priority information according to the security of the change corresponding to the change. If the change is associated with security-sensitive content, such as password storage areas, identity authentication buffers, and operating system security isolation areas, it must be refreshed first to prevent potential data leakage or system exceptions. For example, when a change is detected in the memory area of the security sandbox (such as the memory mapping of the secure execution environment TEE), a high security priority should be immediately assigned.

[0106] According to the embodiments of the present disclosure, operation S130 may include operation S720. In operation S720, according to the content priority information and the target update range, a target instruction is generated and sent, wherein the execution priority information of the target instruction is generated according to the content priority information, and the execution priority information is used to indicate the order in which the target processor executes the target instruction.

[0107] Execution priority information is used to identify the priority of a target instruction when processing an interrupt task and is usually embedded in the Vector field of an interrupt request instruction (such as IPI). The higher the value of the execution priority information, the higher the interrupt priority, and the target processor needs to respond to the interrupt request faster; when the value is lower, the response can be delayed, waiting for the current task to complete or the resources to be idle before processing the refresh operation.

[0108] For example, when the content priority calculated according to the change content is high (such as large-scale, kernel-mode, high-security changes), when generating an IPI interrupt instruction, set the Vector field to a higher value (such as 0xF0); when the content priority is low (such as small-scale, user-mode, delayable changes), set the Vector field to a lower value (such as 0x30). In this way, when the target processor receives multiple IPI interrupt requests, it can decide whether to immediately interrupt the current executing task according to the Vector priority order, give priority to processing high-priority refreshes, or choose to delay processing low-priority refreshes.

[0109] By dynamically determining the content priority information according to the change content and generating the execution priority information based on the content priority, the processing mechanism can achieve fine-grained control of the interrupt response order of the target processor, avoid all interrupt refresh operations from immediately interrupting the current task, reduce the interference of unnecessary high-frequency interruptions on system performance; at the same time, it can ensure that high-urgency and high-importance refresh tasks are executed first, guarantee the consistency and security of system data, and effectively improve the interrupt scheduling intelligence and overall operation efficiency of the multi-core server system in a high-concurrency environment.

[0110] Figure 8 Another flowchart of the data update method according to an embodiment of the present disclosure is schematically shown.

[0111] According to an embodiment of the present disclosure, the data update method can be applied to a processor, that is, the source processor that executes this method, such as Figure 8 As shown, on the basis of the foregoing embodiment, the data update method may further include operation S810.

[0112] In a multi-core processor system, especially in a system adopting a Non-Uniform Memory Access (NUMA) architecture, processor cores are divided into multiple nodes, and each node has local memory and a set of processor cores. The processor cores within a node can communicate through a shared cache and a coherence protocol to achieve low-latency and high-bandwidth data exchange; while communication between nodes needs to be completed through a cross-node interconnect bus, with relatively high communication latency and limited bandwidth. Under this architecture, processors within a node can directly synchronize state changes based on the cache coherence protocol without relying on the system bus to transmit instructions; while processors between nodes need to transmit interrupt instructions (such as IPI) through the bus for flush synchronization. Therefore, adopting different flush synchronization mechanisms according to whether processors are within the same coherence domain helps optimize communication efficiency and reduce bus pressure.

[0113] In operation S810, in response to the processor being able to communicate with the first target processor based on the cache coherence protocol, send a target instruction to the first target processor so that the first target processor updates the data within the target update range in the corresponding translation lookaside buffer through the cache coherence protocol.

[0114] According to an embodiment of the present disclosure, the target processor can be the first target processor or the second target processor.

[0115] The first target processor can be a target processor core that is within the same cache coherence domain as the source processor and can directly perform high-speed data synchronization through a cache coherence protocol (such as MESIF, MOESI, etc.). Usually located within the same physical node or the same physical processor socket.

[0116] The second target processor can be a target processor core that is in a different cache coherence domain from the source processor and cannot directly perform data synchronization through the cache coherence protocol and needs to communicate through cross-node bus transmission. Usually located in different physical nodes or different physical processor sockets.

[0117] When the source processor detects that the target update range needs to be synchronized, if cache coherence communication is supported between the first target processor and the source processor, the system implicitly transmits a flush notification to the first target processor through the cache coherence protocol mechanism, enabling the first target processor to automatically sense and update the corresponding content in its local translation lookaside buffer (TLB), avoiding the use of traditional bus transmission of interrupt instructions, improving communication speed and reducing bus overhead.

[0118] For example, assume that the source processor CPU0 and the target processor CPU1 belong to the same NUMA node and support sharing cache states through the MESIF protocol. When CPU0 triggers a TLB flush, the flush tag can be directly pushed to the corresponding cache line of CPU1 through the MESIF cache coherence protocol. After CPU1 detects the state change, it automatically performs a TLB flush without sending a separate IPI interrupt, thereby reducing bus traffic and accelerating the response speed.

[0119] According to an embodiment of the present disclosure, the data update method further includes S820. In operation S820, in response to the processor and the second target processor being unable to communicate based on the cache coherence protocol, a target instruction is sent to the second target processor based on the instruction transfer management module, so that the second target processor updates the data within the target update range in the corresponding translation lookaside buffer.

[0120] When the source processor detects that the target update range needs to be synchronized, if cache coherence communication is not supported between the second target processor and the source processor (such as across NUMA nodes or different physical processor slots), a traditional IPI interrupt instruction is sent to the second target processor through the instruction transfer management module (such as APIC / GIC, etc.) using the system bus. After receiving the interrupt, the second target processor fetches the target update range from the shared storage space to complete the local TLB flush operation.

[0121] For example, assume that the source processor CPU0 is located in node A and the target processor CPU5 is located in node B. Communication between the two nodes needs to be through cross-node interconnection (such as QPI, Infinity Fabric) and they do not share the cache coherence protocol. At this time, CPU0 sends an IPI instruction through the APIC module, which is transmitted through the system bus to CPU5. After receiving the instruction, CPU5 flushes the local TLB according to the conventional process to maintain system data consistency.

[0122] By selecting different flush instruction transmission methods according to the inter-processor communication capabilities (whether cache coherence protocol is supported), the flush strategy can be optimized for intra-node and cross-node processors respectively. Within the local node, the cache coherence mechanism is maximally utilized to quickly synchronize, reducing bus resource consumption and improving the flush efficiency; in the case of cross-nodes, the traditional interrupt transmission method is still used to ensure the correctness of the flush, thus taking into account both the flush performance and data consistency under different architectures.

[0123] For the convenience of those skilled in the art to understand, the following is through Figure 9 and Figure 10 to illustrate the data flush method provided by the present disclosure.

[0124] Figure 9 Schematically shows a TLB flush method; Figure 10Schematically shows a TLB refresh method according to an embodiment of the present disclosure.

[0125] As Figure 9 shown, the virtual address space includes several virtual address regions (virtual_area), and each virtual address region has a corresponding start address (vm_start) and end address (vm_end). When the virtual address regions virtual_area1 and virtual_area2 change and it is necessary to perform a Remove operation on the data in the virtual address regions virtual_area1 and virtual_area2, for virtual_area1 and virtual_area2, the source processor (such as Core 1) generates independent refresh instructions respectively, and notifies the refresh by sending an Inter-Processor Interrupt (IPI) to each target processor (such as Core 0, Core 2, Core 3, Core 4, Core 5, Core 6, Core 7, Core 8). During this process, every time a change in a virtual address range is detected, the source processor sends a separate IPI interrupt instruction to each target processor respectively. After receiving the interrupt, each target processor refreshes the corresponding address mapping data in its local TLB. Since each virtual address change requires an independent interrupt to be sent, a large number of IPI transmissions are generated in a multi-core system, significantly increasing the bus load and cache coherence maintenance overhead, and easily causing soft lockup or system response latency.

[0126] As Figure 10 shown, the virtual address space also includes multiple virtual address regions (virtual_area), and each region has a corresponding start address (vm_start) and end address (vm_end). When it is detected that a virtual address region needs to be removed, first remove all virtual address regions to be processed, then extract the minimum start address A of all virtual address regions, extract the maximum end address B of all virtual address regions, and based on the address range (Range(A,B)) defined by the start address A and the end address B, generate a unified target update range. Subsequently, the source processor (such as Core 1) only needs to generate a refresh instruction once and send the refresh instruction to each target processor (such as Core 0, Core 2, Core 3, Core 4, Core 5, Core 6, Core 7, Core 8) to notify it to refresh the address mapping covering Range(A,B) in its local TLB.

[0127] Figure 11A block diagram of a data update device according to an embodiment of the present disclosure is schematically shown.

[0128] As Figure 11 shown, the data update device 1100 may include a first acquisition module 1110, a first generation module 1120, and a first transmission module 1130.

[0129] The first acquisition module 1110 is configured to acquire a plurality of virtual address ranges associated with a change in response to the change in the translation lookaside buffer satisfying a trigger condition. In some embodiments, the first acquisition module 1110 may be configured to perform operation S110 in the above data update method, which will not be elaborated herein.

[0130] The first generation module 1120 is configured to generate a target update range according to the plurality of virtual address ranges and store it in a target storage space. The target update range includes at least each virtual address range, and the target storage space can be accessed by a plurality of target processors. In some embodiments, the first generation module 1120 may be configured to perform operation S120 in the above data update method, which will not be elaborated herein.

[0131] The first transmission module 1120 is configured to send a target instruction, which is used to instruct each target processor to interrupt the task being executed, obtain the target update range from the target storage space, and update the translation lookaside buffer corresponding to the target processor according to the target update range. In some embodiments, the first transmission module 1120 may be configured to perform operation S130 in the above data update method, which will not be elaborated herein.

[0132] According to an embodiment of the present disclosure, the first acquisition module may include a second acquisition module.

[0133] The second acquisition module is configured to acquire a plurality of virtual address ranges associated with the change in the translation lookaside buffer after the switch in response to the change brought about by the process context switch. In some embodiments, the second acquisition module may be configured to perform operation S210 in the above data update method, which will not be elaborated herein.

[0134] According to an embodiment of the present disclosure, the first acquisition module may include a third acquisition module.

[0135] The third acquisition module is configured to acquire a plurality of virtual address ranges associated with each change in response to a change occurring in the translation lookaside buffer within a preset time window. In some embodiments, the third acquisition module may be configured to perform operation S310 in the above data update method, which will not be elaborated herein.

[0136] According to an embodiment of the present disclosure, the first acquisition module may include a fourth acquisition module.

[0137] The fourth acquisition module is configured to acquire a plurality of virtual address ranges associated with each change within a preset time range in response to the number of changes occurring within the preset time range being greater than or equal to a preset threshold. In some embodiments, the fourth acquisition module may be configured to perform operation S410 in the above data update method, which will not be elaborated herein.

[0138] According to an embodiment of the present disclosure, the first generation module may include a first sub-generation module or a second sub-generation module.

[0139] The first sub-generation module is configured to merge each virtual address range to generate a target update range in response to each virtual address range being continuous. In some embodiments, the first sub-generation module may be configured to perform operation S510 in the above data update method, which will not be elaborated herein.

[0140] The second sub-generation module is configured to generate a target update range according to the minimum virtual address and the maximum virtual address in each virtual address range in response to there being discontinuous address ranges in each virtual address range. In some embodiments, the second sub-generation module may be configured to perform operation S520 in the above data update method, which will not be elaborated herein.

[0141] According to an embodiment of the present disclosure, the data update device may further include a fifth acquisition module and a sixth acquisition module.

[0142] The fifth acquisition module is configured to acquire target load information, where the target load information characterizes the load level of an instruction transmission management module for transmitting management target instructions. In some embodiments, the fifth acquisition module may be configured to perform operation S610 in the above data update method, which will not be elaborated herein.

[0143] The sixth acquisition module is configured to acquire a plurality of virtual address ranges associated with changes occurring in the translation lookaside buffer in response to the target load information being greater than or equal to a load threshold. In some embodiments, the sixth acquisition module may be configured to perform operation S620 in the above data update method, which will not be elaborated herein.

[0144] According to an embodiment of the present disclosure, the target instruction includes execution priority information, and the data update device may further include a first determination module, and the first sending module may further include a second sending module.

[0145] The first determination module is configured to determine content priority information according to at least one of a change range corresponding to the change, change urgency, change deferrability, and change security. In some embodiments, the first determination module may be configured to perform operation S710 in the above data update method, which will not be elaborated herein.

[0146] The second sending module is configured to generate and send a target instruction according to the content priority information and the target update range, wherein the execution priority information of the target instruction is generated according to the content priority information, and the execution priority information is used to indicate the order for the target processor to execute the target instruction. In some embodiments, the second sending module may be configured to perform operation S720 in the above data update method, which will not be elaborated herein.

[0147] According to an embodiment of the present disclosure, the first sending module may further include a third sending module.

[0148] The third sending module is configured to send a target instruction to the first target processor in response to the processor being able to communicate with the first target processor based on a cache coherence protocol, so that the first target processor updates the data within the target update range in the corresponding translation lookaside buffer through the cache coherence protocol. In some embodiments, the third sending module may be configured to perform operation S810 in the above data update method, which will not be elaborated herein.

[0149] According to embodiments of the present disclosure, any plurality of, or at least part of the functions of any one of, the modules, sub-modules, units, and sub-units may be implemented in one module. Any one or more of the modules, sub-modules, units, and sub-units according to embodiments of the present disclosure may be split into multiple modules for implementation. Any one or more of the modules, sub-modules, units, and sub-units according to embodiments of the present disclosure may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on a substrate, a system in a package, an application specific integrated circuit (ASIC), or may be implemented by hardware or firmware in any other reasonable manner of integrating or packaging circuits, or may be implemented in any one of the three implementation manners of software, hardware, and firmware, or in a suitable combination of any several of them. Alternatively, one or more of the modules, sub-modules, units, and sub-units according to embodiments of the present disclosure may be at least partially implemented as a computer program module, and when the computer program module is run, the corresponding functions may be executed.

[0150] For example, any combination of the first acquisition module 1110, the first generation module 1120, and the first transmission module 1130 can be implemented in one module / unit / sub-unit, or any one of the modules / units / sub-units can be split into multiple modules / units / sub-units. Alternatively, at least part of the functions of one or more of these modules / units / sub-units can be combined with at least part of the functions of other modules / units / sub-units and implemented in one module / unit / sub-unit. According to an embodiment of the present disclosure, at least one of the first acquisition module 1110, the first generation module 1120, and the first transmission module 1130 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or any other reasonable way of integrating or packaging circuits, etc., in hardware or firmware, or implemented in any one of the three implementation manners of software, hardware, and firmware, or in an appropriate combination of any several of them. Alternatively, at least one of the first acquisition module 1110, the first generation module 1120, and the first transmission module 1130 can be at least partially implemented as a computer program module, which can perform corresponding functions when the computer program module is run.

[0151] It should be noted that the data processing system part in the embodiments of the present disclosure corresponds to the data processing method part in the embodiments of the present disclosure. For the description of the data processing system part, please refer to the data processing method part specifically, and details will not be repeated here.

[0152] Figure 12 A block diagram of an electronic device suitable for implementing the method described above according to an embodiment of the present disclosure is schematically shown. Figure 12 The electronic device shown is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.

[0153] As Figure 12 shown, the electronic device 1200 according to an embodiment of the present disclosure includes a processor 1201, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1202 or a program loaded from a storage section 1208 into a random access memory (RAM) 1203. The processor 1201 can include, for example, a general microprocessor (such as a CPU), an instruction set processor, and / or a related chipset, and / or a dedicated microprocessor (such as an application specific integrated circuit (ASIC)), etc. The processor 1201 can also include on-board memory for caching purposes. The processor 1201 can include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0154] In the RAM 1203, various programs and data required for the operation of the electronic device 1200 are stored. The processor 1201, the ROM 1202, and the RAM 1203 are connected to each other via a bus 1204. The processor 1201 performs various operations of the method flow according to the embodiments of the present disclosure by executing the programs in the ROM 1202 and / or the RAM 1203. It should be noted that the programs may also be stored in one or more memories other than the ROM 1202 and the RAM 1203. The processor 1201 may also perform various operations of the method flow according to the embodiments of the present disclosure by executing the programs stored in the one or more memories.

[0155] According to an embodiment of the present disclosure, the electronic device 1200 may further include an input / output (I / O) interface 1205, and the input / output (I / O) interface 1205 is also connected to the bus 1204. The electronic device 1200 may further include one or more of the following components connected to the input / output (I / O) interface 1205: an input portion 1206 including a keyboard, a mouse, etc.; an output portion 1207 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage portion 1208 including a hard disk, etc.; and a communication portion 1209 including a network interface card such as a LAN card, a modem, etc. The communication portion 1209 performs communication processing via a network such as the Internet. A drive 1210 is also connected to the input / output (I / O) interface 1205 as needed. A removable medium 1211, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is mounted on the drive 1210 as needed so that a computer program read therefrom can be installed into the storage portion 1208 as needed.

[0156] According to an embodiment of the present disclosure, the method flow according to the embodiments of the present disclosure may be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable storage medium, and the computer program includes program codes for performing the method shown in the flowchart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication portion 1209, and / or installed from the removable medium 1211. When the computer program is executed by the processor 1201, the above-described functions defined in the system according to the embodiments of the present disclosure are executed. According to an embodiment of the present disclosure, the above-described systems, devices, apparatuses, modules, units, etc. may be implemented by computer program modules.

[0157] The present disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or may exist alone without being assembled into the device / apparatus / system. The above computer-readable storage medium carries one or more programs, and when the one or more programs are executed, the method according to the embodiments of the present disclosure is implemented.

[0158] According to an embodiment of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium. For example, it may include but is not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0159] For example, according to an embodiment of the present disclosure, the computer-readable storage medium may include one or more memories other than the above-described ROM 1202 and / or RAM 1203 and / or ROM 1202 and RAM 1203.

[0160] Embodiments of the present disclosure also include a computer program product, which includes a computer program that contains program code for executing the method provided by the embodiments of the present disclosure. When the computer program product runs on an electronic device, the program code is used to cause the electronic device to implement the control method provided by the embodiments of the present disclosure.

[0161] When the computer program is executed by the processor 1201, the above functions defined in the system / apparatus of the embodiments of the present disclosure are executed. According to an embodiment of the present disclosure, the above-described systems, apparatuses, modules, units, etc. may be implemented by computer program modules.

[0162] In one embodiment, the computer program may rely on tangible storage media such as optical storage devices and magnetic storage devices. In another embodiment, the computer program may also be transmitted and distributed in the form of signals on a network medium, and be downloaded and installed through the communication part 1209, and / or be installed from the removable medium 1211. The program code included in the computer program may be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above. According to the embodiments of the present disclosure, the program code for executing the computer program provided by the embodiments of the present disclosure may be written in any combination of one or more programming languages. Specifically, these computing programs may be implemented using high-level procedures and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages include but are not limited to, such as Java, C++, python, the "C" language, or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (for example, by using an Internet service provider to connect through the Internet).

[0163] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and the combinations of blocks in the block diagram or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions. Those skilled in the art can understand that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0164] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A data update method, comprising: Upon the changes in the translation lookaside buffer satisfying a trigger condition, obtaining a plurality of virtual address ranges associated with the changes; Generating a target update range according to the plurality of virtual address ranges and storing the target update range in a target storage space, where the target update range at least includes each of the virtual address ranges, and the target storage space can be accessed by a plurality of target processors; Sending a target instruction, where the target instruction is used to instruct each of the target processors to interrupt the task being executed, obtain the target update range from the target storage space, and update the translation lookaside buffer corresponding to the target processor according to the target update range.

2. The method according to claim 1, where the step of upon the changes in the translation lookaside buffer satisfying a trigger condition, obtaining a plurality of virtual address ranges associated with the changes, includes: Upon the changes being the changes brought about by a process context switch, obtaining a plurality of virtual address ranges associated with the changes in the translation lookaside buffer after the switch.

3. The method according to claim 1, where the step of upon the changes in the translation lookaside buffer satisfying a trigger condition, obtaining a plurality of virtual address ranges associated with the changes, includes: Upon changes occurring in the translation lookaside buffer within a preset time window, obtaining a plurality of virtual address ranges associated with each of the changes.

4. The method according to claim 1, where the step of upon the changes in the translation lookaside buffer satisfying a trigger condition, obtaining a plurality of virtual address ranges associated with the changes, includes: Upon the number of changes occurring within a preset time range being greater than or equal to a preset threshold, obtaining a plurality of virtual address ranges associated with each of the changes within the preset time range.

5. The method according to claim 1, where the step of generating the target update range includes: Upon each of the virtual address ranges being continuous, merging each of the virtual address ranges to generate the target update range; Or, Upon there being discontinuous address ranges among each of the virtual address ranges, generating the target update range according to the minimum virtual address and the maximum virtual address among each of the virtual address ranges.

6. The method according to claim 1, further comprising: Obtaining target load information, where the target load information characterizes the load level of an instruction transmission management module for transmitting and managing the target instruction; Upon the target load information being greater than or equal to a load threshold, obtaining a plurality of virtual address ranges associated with the changes occurring in the translation lookaside buffer.

7. The target instruction according to claim 1 includes execution priority information, and the method further comprises: Determining content priority information according to at least one of the change range, change urgency, change deferability, and change security corresponding to the change; The step of sending the target instruction includes: Generate and send the target instruction according to the content priority information and the target update range, wherein the execution priority information of the target instruction is generated according to the content priority information, and the execution priority information is used to indicate the order for the target processor to execute the target instruction.

8. The method according to claim 1, wherein the method is applied to a processor, and the sending the target instruction includes: In response to the processor being able to communicate with a first target processor based on a cache coherence protocol, send the target instruction to the first target processor, so that the first target processor updates data within the target update range in the corresponding translation lookaside buffer through the cache coherence protocol.

9. A data update device, comprising: A first acquisition module, configured to acquire a plurality of virtual address ranges associated with the change in response to the change in the translation lookaside buffer satisfying a trigger condition; A first generation module, configured to generate a target update range according to the plurality of virtual address ranges and store the target update range in a target storage space, where the target update range at least includes each of the virtual address ranges, and the target storage space can be accessed by a plurality of target processors; And A first sending module, configured to send a target instruction, where the target instruction is used to instruct each of the target processors to interrupt the task being executed, obtain the target update range from the target storage space, and update the translation lookaside buffer corresponding to the target processor according to the target update range.

10. An electronic device, comprising: At least one processor; And A memory connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can perform the following operations: in response to the change in the translation lookaside buffer satisfying a trigger condition, acquire a plurality of virtual address ranges associated with the change; generate a target update range according to the plurality of virtual address ranges and store the target update range in a target storage space, where the target update range at least includes each of the virtual address ranges, and the target storage space can be accessed by a plurality of target processors; Send a target instruction, where the target instruction is used to instruct each of the target processors to interrupt the task being executed, obtain the target update range from the target storage space, and update the translation lookaside buffer corresponding to the target processor according to the target update range.

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